Re: Debugging the Radeon 200M command processor (CP)

[Nigel C. <ni...@ni...>]

Hi guys.

On Wed, 2007-02-21 at 08:51 +0000, Dave Airlie wrote:
> >
> > Which would exactly fit between 0xCFFE0000 - 0xCFFFFFFF.   Yes this is an
> > assumption, but some of the DRI code mentions that PCI express allocates the
> > GART table at the end of the frame buffer, so that is why I was thinking it
> > worked this way.
> 
> Can you dump that memory area? see if it has a GART table in it.. GART 
> tables usually are fairly easy to spot lots of page pointers..
> 
> >
> > Ok.. I read that file.  None of them seem to touch the card directly..  The
> > only bits that I found which actually touch the card are in radeon_cp.c (at
> > least the older git checkout that I have...)
> 
> ati_pcigart.c just creates the tables, the registers to poke are 
> differrent depending on the type of gart..
> >
> > When you say that the card reacts, are you referring to tickling these
> > registers: RADEON_AIC_CNTL, RADEON_AIC_PT_BASE, RADEON_AIC_LO_ADDR,
> > RADEON_AIC_HI_ADDR?  (none of my fglrx traces (libsegfault or kmmio) touch
> > these registers...)
> 
> Yeah I just tried to see if a PCI GART worked, I didn't care if fglrx used 
> it or not,... there is probably something else necessary outside the 
> normal setup regs to get it to work I gave it up on it when it didn't work 
> out of the box..
> 
> Dave.

I was wondering this morning, could it potentially help to dump the
contents of the memory that fglrx allocates when the driver is
suspended? I have a 200M as well (same 32MB config as you, Dave), and so
could see what I got if it would have a hope of being helpful.

Regards,

Nigel