From: Jerome G. <j.g...@gm...> - 2005-02-14 15:13:26
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On Mon, 14 Feb 2005 10:02:07 -0500 (EST), Vladimir Dergachev <vo...@mi...> wrote: > > > On Mon, 14 Feb 2005, Jerome Glisse wrote: > > >> On Mon, 14 Feb 2005 17:17:05 +1100, Paul Mackerras <pa...@sa...> wrote: > >>> Vladimir Dergachev writes: > >>> > >>>> I am a bit puzzled with your patch - do you really need to hard code > >>>> format field in r300_state.c ? > > > > Ok i think i understand, Mesa tell us that the format is > > MESA_FORMAT_RGBA8888_REV on big endiand and > > MESA_FORMAT_RGBA8888 on little endian. Thus if i change > > {0xffffff01, 0}, > > to > > {R300_EASY_TX_FORMAT(Z, Y, X, W, W8Z8Y8X8), 0}, > > > > it works. Vlad does this lead to some strange things on x86 ? > > The reason these entries are as they are is because I (and probably no one > else yet) was not able to trigger them with any test program. > > Of course, it must be possible to debug them by writing a custom program, > but I did not have time for that yet.. Yes but my understanding is that mesa will never give you MESA_FORMAT_RGBA8888_REV on x86 because this tell you that data are in reverse order (see mesa texformat). So i think that all odd entry in this table are for REV order (which we will found on big endian) and all even entry are for "normal" order x86. I think that you can ask mesa to give you texture in REV order on x86 but don't know how. I am really want to commit this simple patch, maybe someone with a better understand of mesa & who know radeon driver could tell us if i am wrong. More over if you look at all table (r200 table or table0 in r300) you will see that allmost all odd entry have the _REV suffix. So every even entry for you x86 and odd for us ppc ;) By the way with which program do you test : {0xffffff11, 0}, ->{R300_EASY_TX_FORMAT(Y, Y, Y, X, Y8X8), 0}, {0xffffff13, 0}, the 0xffffff13 would be {0xffffff11, 0}, {R300_EASY_TX_FORMAT(Y, Y, Y, X, Y8X8), 0}, {R300_EASY_TX_FORMAT(Y, Y, X, Y, Y8X8), 0}, But testing if the result is good is better :) Jerome Glisse |