From: Ian R. <id...@us...> - 2004-09-27 17:22:29
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Patrick McFarland wrote: > On Thu, 23 Sep 2004 16:50:26 +0100, Alan Cox <al...@lx...> wrote: > >>Should do. There is a corner case of SMP with only one CPU having SSE >>but thats already broken in Mesa and many other packages. > > Not to sound ignorant, but isn't that a bug in the > mobo/bios/chipset/processors? That shouldn't even be possible, should > it? (And if it 'is', shouldn't Linux disable SSE usage on both > processors?) It's not a common case by any stretch of the imagination, but it can happen. At the very least, a company called Sequent (where I used to work...until it was bought by IBM about 4 years ago) used to make big ccNUMA boxes that could do it. Basically, the system was a collection of 4-way SMP units, called "quads", connected by a high-speed interconnect. Quads from any generation could be mixed-and-matched to allow easy system expandability. At one point we had an engineering system that had 2 PentiumPro quads (fast 200MHz procs w/1MB cache!), 3 Pentium II Xeon quads, and a Pentium III Xeon quad. Processes could freely migrate from quad to quad. So, at start up you might have MMX and SSE available, but that the next task switch... This wasn't a real problem at the time because our main target was Oracle and the like. I don't know if there are any other real-world examples of mix-and-match systems. I guess that's why I'm not worried about making Mesa test all the CPUs in a box. :) |