From: Andreas S. <A.S...@gm...> - 2003-06-13 13:12:26
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while trying to activate the 3rd TMU on radeon I discovered that "txr" states get emitted even in the yuvsqare (and multiarb) demo (which use only standard textures): (RADEON_DEBUG=3Dstate and yuvsqare demo:) =2E... radeonBindTexture( 0x8132dc8 ) unit=3D0 radeonEmitState radeonEmitState - lost context emit TEX/tex-0/9 emit CTX/context/14 skip state TXR/txr-2 skip state TXR/txr-1 skip state TEX/tex-2 skip state TEX/tex-1 emit ZBS/zbias/3 emit MSC/misc/2 emit VPT/viewport/7 emit TXR/txr-0/3 emit MSK/mask/4 emit LIN/line/5 emit SET/setup/5 =2E... I dont know if its bad, but I think it shouldnt happen. I changed the CHECK in radeon_state_init.c for txr and now it doesnt happen anymore, at least in yuvsquare. radeon_state_init.c:CHECK( txr0, ctx->Texture.Unit[0]._ReallyEnabled=20 & TEXTURE_RECT_BIT) radeon_state_init.c:CHECK( txr1, ctx->Texture.Unit[1]._ReallyEnabled=20 & TEXTURE_RECT_BIT) btw. heres also a patch for mplayer vo_gl.c which uses=20 GL_NV_texture_rectangle. I sent a (sligtly) older version to mplayer-dev-eng, but=20 unfortunately it got caught by some filter/ wasnt released by the mailinglist=20 moderator. best regards, Andreas Am 2003.06.10 17:40:05 +0200 schrieb(en) Keith Whitwell: [.......] >=20 > Here's a patch that mainly works. I've still seen the odd case of=20 > the texture apparently getting uploaded to the backbuffer. >=20 > Keith [...] > RCS file:=20 > /cvsroot/dri/xc/xc/lib/GL/mesa/src/drv/radeon/radeon_state_init.c,v > retrieving revision 1.10 > diff -u -r1.10 radeon_state_init.c > --- radeon_state_init.c 30 Apr 2003 01:50:54 > -0000 1.10 > +++ radeon_state_init.c 10 Jun 2003 15:37:50 -0000 > @@ -134,6 +134,9 @@ > TCL_CHECK( tcl_ucp5, (ctx->Transform.ClipPlanesEnabled & 0x20) ) > TCL_CHECK( tcl_eyespace_or_fog, ctx->_NeedEyeCoords || > ctx->Fog.Enabled ) >=20 > +CHECK( txr0, ctx->Texture.Unit[0]._ReallyEnabled ) > +CHECK( txr1, ctx->Texture.Unit[1]._ReallyEnabled ) > + >=20 >=20 > /* Initialize the context's hardware state. > @@ -246,6 +249,8 @@ > ALLOC_STATE( lit[5], tcl_lit5, LIT_STATE_SIZE, "LIT/light-5", 1 > ); > ALLOC_STATE( lit[6], tcl_lit6, LIT_STATE_SIZE, "LIT/light-6", 1 > ); > ALLOC_STATE( lit[7], tcl_lit7, LIT_STATE_SIZE, "LIT/light-7", 1 > ); > + ALLOC_STATE( txr[0], txr0, TXR_STATE_SIZE, "TXR/txr-0", 0 ); > + ALLOC_STATE( txr[1], txr1, TXR_STATE_SIZE, "TXR/txr-1", 0 ); >=20 >=20 > /* Fill in the packet headers: > @@ -268,6 +273,8 @@ > rmesa->hw.tcl.cmd[TCL_CMD_0] =3D > cmdpkt(RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT); > rmesa->hw.mtl.cmd[MTL_CMD_0] =3D > cmdpkt(RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED); > + rmesa->hw.txr[0].cmd[TXR_CMD_0] =3D > cmdpkt(RADEON_EMIT_PP_TEX_SIZE_0); > + rmesa->hw.txr[1].cmd[TXR_CMD_0] =3D > cmdpkt(RADEON_EMIT_PP_TEX_SIZE_1); > rmesa->hw.grd.cmd[GRD_CMD_0] =3D > cmdscl( RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR, 1, 4 ); > rmesa->hw.fog.cmd[FOG_CMD_0] =3D [...] |