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Re: [Dri-devel] r200WaitForFrameCompletion: drmRadeonIrqWait: -16
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From: Dieter <Die...@ha...> - 2002-09-26 00:22:35
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Am Donnerstag, 26. September 2002 01:46 schrieb Linus Torvalds:
> On Thu, 26 Sep 2002, Dieter N=FCtzel wrote:
> > Can we please change the IRQ code to not share the same IRQ with anot=
her
> > device?
>
> Not up to us. It depends on the physical routing of the interrupt line =
on
> the motherboard (often together with some amount programmability, but
> Linux already tries to some degree to span out the ones that can be
> changed. At least for the cases where the PIRQ table gives enough info
> on how to do so).
That's happening on my board, I think.
<6>ACPI: RSDP (v000 AMD2P ) @ 0x000f6400
<6>ACPI: RSDT (v001 AMD2P AWRDACPI 16944.11825) @ 0x3fff3000
<6>ACPI: FADT (v001 AMD2P AWRDACPI 16944.11825) @ 0x3fff3040
<6>ACPI: MADT (v001 AMD2P AWRDACPI 16944.11825) @ 0x3fff6580
<6>ACPI: Local APIC address 0xfee00000
<6>ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
<4>Processor #0 Pentium(tm) Pro APIC version 16
<6>ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled)
<4>Processor #1 Pentium(tm) Pro APIC version 16
<6>ACPI: IOAPIC (id[0x02] address[0xfec00000] global_irq_base[0x0])
<6>IOAPIC[0]: Assigned apic_id 2
<4>IOAPIC[0]: apic_id 2, version 17, address 0xfec00000, IRQ 0-23
<6>ACPI: INT_SRC_OVR (bus[0] irq[0x0] global_irq[0x2] polarity[0x0]=20
trigger[0x0])
<6>ACPI: INT_SRC_OVR (bus[0] irq[0x9] global_irq[0x9] polarity[0x3]=20
trigger[0x3])
<6>Using ACPI (MADT) for SMP configuration information
<4>CPU1: AMD Athlon(tm) MP stepping 02
<6>Total of 2 processors activated (6389.76 BogoMIPS).
<4>ENABLING IO-APIC IRQs
<7>init IO_APIC IRQs
<7> IO-APIC (apicid-pin) 2-0, 2-16, 2-17, 2-18, 2-19, 2-20, 2-21, 2-22, 2=
-23=20
not connected.
<6>..TIMER: vector=3D0x31 pin1=3D2 pin2=3D0
<7>number of MP IRQ sources: 16.
<7>number of IO-APIC #2 registers: 24.
<6>testing the IO APIC.......................
<4>
<7>IO APIC #2......
<7>.... register #00: 02000000
<7>....... : physical APIC id: 02
<7>.... register #01: 00170011
<7>....... : max redirection entries: 0017
<7>....... : PRQ implemented: 0
<7>....... : IO APIC version: 0011
<7>.... register #02: 00000000
<7>....... : arbitration: 00
<7>.... IRQ redirection table:
<7> NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect:
<7> 00 000 00 1 0 0 0 0 0 0 00
<7> 01 003 03 0 0 0 0 0 1 1 39
<7> 02 003 03 0 0 0 0 0 1 1 31
<7> 03 003 03 0 0 0 0 0 1 1 41
<7> 04 003 03 0 0 0 0 0 1 1 49
<7> 05 003 03 0 0 0 0 0 1 1 51
<7> 06 003 03 0 0 0 0 0 1 1 59
<7> 07 003 03 0 0 0 0 0 1 1 61
<7> 08 003 03 0 0 0 0 0 1 1 69
<7> 09 003 03 1 1 0 1 0 1 1 71
<7> 0a 003 03 0 0 0 0 0 1 1 79
<7> 0b 003 03 0 0 0 0 0 1 1 81
<7> 0c 003 03 0 0 0 0 0 1 1 89
<7> 0d 003 03 0 0 0 0 0 1 1 91
<7> 0e 003 03 0 0 0 0 0 1 1 99
<7> 0f 003 03 0 0 0 0 0 1 1 A1
<7> 10 000 00 1 0 0 0 0 0 0 00
<7> 11 000 00 1 0 0 0 0 0 0 00
<7> 12 000 00 1 0 0 0 0 0 0 00
<7> 13 000 00 1 0 0 0 0 0 0 00
<7> 14 000 00 1 0 0 0 0 0 0 00
<7> 15 000 00 1 0 0 0 0 0 0 00
<7> 16 000 00 1 0 0 0 0 0 0 00
<7> 17 000 00 1 0 0 0 0 0 0 00
<7>IRQ to pin mappings:
<7>IRQ0 -> 0:2
<7>IRQ1 -> 0:1
<7>IRQ3 -> 0:3
<7>IRQ4 -> 0:4
<7>IRQ5 -> 0:5
<7>IRQ6 -> 0:6
<7>IRQ7 -> 0:7
<7>IRQ8 -> 0:8
<7>IRQ9 -> 0:9
<7>IRQ10 -> 0:10
<7>IRQ11 -> 0:11
<7>IRQ12 -> 0:12
<7>IRQ13 -> 0:13
<7>IRQ14 -> 0:14
<7>IRQ15 -> 0:15
<6>.................................... done.
<4>Using local APIC timer interrupts.
<4>calibrating APIC timer ...
<4>..... CPU clock speed is 1600.0293 MHz.
<4>..... host bus clock speed is 266.6712 MHz.
<4>cpu: 0, clocks: 2666712, slice: 888904
<4>CPU0<T0:2666704,T1:1777792,D:8,S:888904,C:2666712>
<4>cpu: 1, clocks: 2666712, slice: 888904
<4>CPU1<T0:2666704,T1:888896,D:0,S:888904,C:2666712>
<4>checking TSC synchronization across CPUs: passed.
<6>ACPI: Subsystem revision 20020815
<6>PCI: PCI BIOS revision 2.10 entry at 0xfb130, last bus=3D2
<6>ACPI: Interpreter enabled
<6>ACPI: Using IOAPIC for interrupt routing
<6>ACPI: System [ACPI] (supports S0 S1 S4 S5)
<6>ACPI: PCI Root Bridge [PCI0] (00:00)
<4>PCI: Probing PCI hardware (bus 00)
<7>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
<7>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.OP2P._PRT]
<7>ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.AGPP._PRT]
<4>ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 *5 6 7 10 11 12 14 15)
<4>ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *10 11 12 14 15)
<4>ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 *11 12 14 15)
<4>ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 10 *11 12 14 15)
<6>PCI: Probing PCI hardware
<7>IOAPIC[0]: Set PCI routing entry (2-16 -> 0xa9 -> IRQ 16)
<7>00:00:08[A] -> 2-16 -> vector 0xa9 -> IRQ 16
<7>IOAPIC[0]: Set PCI routing entry (2-17 -> 0xb1 -> IRQ 17)
<7>00:00:08[B] -> 2-17 -> vector 0xb1 -> IRQ 17
<7>IOAPIC[0]: Set PCI routing entry (2-18 -> 0xb9 -> IRQ 18)
<7>00:00:08[C] -> 2-18 -> vector 0xb9 -> IRQ 18
<7>IOAPIC[0]: Set PCI routing entry (2-19 -> 0xc1 -> IRQ 19)
<7>00:00:08[D] -> 2-19 -> vector 0xc1 -> IRQ 19
<7>Pin 2-17 already programmed
<7>Pin 2-18 already programmed
<7>Pin 2-19 already programmed
<7>Pin 2-16 already programmed
<7>Pin 2-16 already programmed
<7>Pin 2-17 already programmed
<7>Pin 2-18 already programmed
<7>Pin 2-19 already programmed
<7>Pin 2-16 already programmed
<7>Pin 2-17 already programmed
<7>Pin 2-18 already programmed
<7>Pin 2-19 already programmed
<7>Pin 2-16 already programmed
<7>Pin 2-17 already programmed
<7>Pin 2-18 already programmed
<7>Pin 2-19 already programmed
<7>Pin 2-16 already programmed
<7>Pin 2-17 already programmed
<7>Pin 2-18 already programmed
<7>Pin 2-19 already programmed
<7>Pin 2-17 already programmed
<7>Pin 2-18 already programmed
<7>Pin 2-19 already programmed
<7>Pin 2-16 already programmed
<7>Pin 2-18 already programmed
<7>Pin 2-19 already programmed
<7>Pin 2-16 already programmed
<7>Pin 2-17 already programmed
<7>Pin 2-17 already programmed
<7>Pin 2-18 already programmed
<7>Pin 2-19 already programmed
<7>Pin 2-16 already programmed
<7>Pin 2-17 already programmed
<7>Pin 2-18 already programmed
<7>Pin 2-19 already programmed
<7>Pin 2-16 already programmed
> Quite often (on a standard desktop motherboard) there are just 4 physic=
al
> PCI interrupt lines, and they are shared between the different cards an=
d
> the on-board devices. Usually the add-in cards are "staggered", so that=
if
> you move a card around the irq associated with it will change and you c=
an
> try to spread the irq's out a bit that way. That isn't generally an opt=
ion
> for an AGP slot ;)
Jep, I know...
But #9 and #10 (mostly used with gfk) are empty?
One onboard 82559ER and one 82557/8/9 card.
Bus 1, device 5, function 0:
VGA compatible controller: ATI Technologies Inc Radeon QL (rev 0).
IRQ 17.
Master Capable. Latency=3D32. Min Gnt=3D8.
Prefetchable 32 bit memory at 0xe8000000 [0xefffffff].
I/O at 0xb000 [0xb0ff].
Non-prefetchable 32 bit memory at 0xf1000000 [0xf100ffff].
Ethernet controller: Intel Corp. 82557/8/9 [Ethernet Pro 100] (rev 4)=
=2E
IRQ 17.
Master Capable. Latency=3D32. Min Gnt=3D8.Max Lat=3D56.
Prefetchable 32 bit memory at 0xf4000000 [0xf4000fff].
I/O at 0x9800 [0x981f].
Non-prefetchable 32 bit memory at 0xf3000000 [0xf30fffff].
Bus 2, device 9, function 0:
Ethernet controller: Intel Corp. 82559ER (rev 9).
IRQ 17.
Master Capable. Latency=3D32. Min Gnt=3D8.Max Lat=3D56.
Non-prefetchable 32 bit memory at 0xf3121000 [0xf3121fff].
I/O at 0xa000 [0xa03f].
Non-prefetchable 32 bit memory at 0xf3100000 [0xf311ffff].
> Some higher-end boards (ie server-class) have multiple IO-APIC's and ma=
ny
> interrupt sources, and they tend to try to avoid tying irq lines togeth=
er.
> But those board people spent a lot more effort on the board design than
> you see on most regular boards (and they don't need to worry about cost
> etc, so they have more layers etc to route stuff in anyway)
But that's what I have.
Look again.
It is an AMD 760 MPX but without Alan's IRQ routing stuff.
Latest ACPI patch from sf.net.
Any glue about the stuttering with UT?
Thanks,
=09Dieter
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