[Dri-devel] Mach 64 DMA success!

[Leif D. <lde...@re...>]

First off, I haven't checked this in yet, because I need to do some 
cleanup, but I've got synchronous DMA working for vertex buffers on both 
AGP and PCI (PCI for me meaning with agpgart unloaded).  Unfortunately, at 
the moment it's actually slower than MMIO, since it's synchronous (wait 
for idle at the end of every pass) and there's the overhead of the 
descriptor table setup.  So I guess the next thing to do will be to figure 
out the buffer aging.

I set up the descriptor table in PCI space using the pci_pool interface
that the bus master test used, and I keep the handles in dev_priv.  It
took me awhile to figure out how to properly pass the physical address of
the buffers to the card.  What I'm doing for pci is using:

address = (u32) virt_to_phys((void *)buf->address)

and for AGP:

address = (u32) buf->bus_address

and to get a valid pointer for reading/writing the buffer with PCI I use:

u32 *p = (u32 *) buf->address

Jose, you almost had it before, it's just a matter of using the right
types and cast.  I'll try and send you a patch soon when I get things 
cleaned up a bit.

-- 
Leif Delgass 
http://www.retinalburn.net