Re: [Dri-devel] Mach64: luck with alignment, but not with idle

[<AKa...@t-...>]

Frank Earl wrote:
> The engine proceeds to pull values from out of the descriptor table as soon
> as that last write operation is performed- this is by ATI's design.  The
> values placed in the data areas described by the descriptor table are MMIO
> dword offset for the register followed by the data to be put into that
> register.  The engine treats the data in the areas defined by the descriptor
> table as an enormous command fifo.  It grabs the first dword and assumes it's
> an offset in dwords from the base of the register aperture.  It then assumes
> that the second dword is the data that is supposed to be written to that
> register and does just that.  It continues until it reaches the end of the
> descriptor table.  Note that this doesn't turn off the GUI master setup and
> any attempt to write to the GUI registers will re-fire the entire descriptor
> table.  In order to avoid this problem in Utah-GLX, we mprotected the
> register region during the pass and placed a shutdown command (disabling bus
> mastering by toggling the bus master disable flag in the control register) at
> the end along with restoring selected old register values that we had upon
> entry.

There's one strong argument against this theory:
Assume that there are disturbing GUI-commands wich are send in the time
between kick-off and idle check that are supposed to fire of DMA again.
I comment out the kick-off line in the code. By our assumption the
DMA-transfer must be kicked-off though. But it isn't. The engine stays
idle. Contradiction. Therefore this hypothesis is wrong. Or did I miss
something?

-Andreas Karrenbauer