Re: [Dri-devel] A couple of questions re: MGA DMA

[Keith W. <ke...@va...>]

Gareth Hughes wrote:
> 
> I've noticed that most of the DMA commands are:
> 
> 1) Very inefficiently programmed, or
> 2) Done to meet strict requirements or to work around hardware bugs
> 
> Things like:
> 
>         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
>                    MGA_DMAPAD,  0x00000000,
>                    MGA_DWGSYNC, 0x00007100,
>                    MGA_DWGSYNC, 0x00007000 );
> 
> before blits, and
> 
>         /* Force reset of DWGCTL */
>         DMA_BLOCK( MGA_DMAPAD,  0x00000000,
>                    MGA_PLNWT,   ctx->plnwt,
>                    MGA_PITCH,   dev_priv->front_pitch,
>                    MGA_DWGCTL,  dev_priv->dwgctl );
> 
> after blits.  For instance, does DWGCTL have to be the last register in
> the block?  Are there rules about this kind of thing?  The clears are
> particularly redundant, but I'd like to know if there is some reason for
> the way they are.

I should really let Jeff answer, but I think a lot of things like this was
done for reasons that weren't particularly strong.  The fundamental
instability of the dma engine meant that it was never prudent to remove things
that 'might' have prevented lockups...

Keith