From: <ag...@ke...> - 2013-06-28 18:44:57
|
radeon/r600_pci_ids.h | 26 ++++++++++++++++++++++++++ radeon/radeon_surface.c | 3 +++ 2 files changed, 29 insertions(+) New commits: commit 378bb47a784a3808c9b256fe7a52e10a4fcabf92 Author: Alex Deucher <ale...@am...> Date: Thu Jan 24 18:01:59 2013 -0500 radeon: add kabini pci ids Signed-off-by: Alex Deucher <ale...@am...> diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h index 545019e..fbadb82 100644 --- a/radeon/r600_pci_ids.h +++ b/radeon/r600_pci_ids.h @@ -407,3 +407,20 @@ CHIPSET(0x6651, BONAIRE_6651, BONAIRE) CHIPSET(0x6658, BONAIRE_6658, BONAIRE) CHIPSET(0x665C, BONAIRE_665C, BONAIRE) CHIPSET(0x665D, BONAIRE_665D, BONAIRE) + +CHIPSET(0x9830, KABINI_9830, KABINI) +CHIPSET(0x9831, KABINI_9831, KABINI) +CHIPSET(0x9832, KABINI_9832, KABINI) +CHIPSET(0x9833, KABINI_9833, KABINI) +CHIPSET(0x9834, KABINI_9834, KABINI) +CHIPSET(0x9835, KABINI_9835, KABINI) +CHIPSET(0x9836, KABINI_9836, KABINI) +CHIPSET(0x9837, KABINI_9837, KABINI) +CHIPSET(0x9838, KABINI_9838, KABINI) +CHIPSET(0x9839, KABINI_9839, KABINI) +CHIPSET(0x983A, KABINI_983A, KABINI) +CHIPSET(0x983B, KABINI_983B, KABINI) +CHIPSET(0x983C, KABINI_983C, KABINI) +CHIPSET(0x983D, KABINI_983D, KABINI) +CHIPSET(0x983E, KABINI_983E, KABINI) +CHIPSET(0x983F, KABINI_983F, KABINI) commit 96c04c23fca6656483f66ecb0da0679df02eb9c0 Author: Alex Deucher <ale...@am...> Date: Fri Jun 7 13:46:37 2013 -0400 radeon: add Bonaire pci ids Signed-off-by: Alex Deucher <ale...@am...> diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h index 01c900f..545019e 100644 --- a/radeon/r600_pci_ids.h +++ b/radeon/r600_pci_ids.h @@ -398,3 +398,12 @@ CHIPSET(0x6664, HAINAN_6664, HAINAN) CHIPSET(0x6665, HAINAN_6665, HAINAN) CHIPSET(0x6667, HAINAN_6667, HAINAN) CHIPSET(0x666F, HAINAN_666F, HAINAN) + +CHIPSET(0x6640, BONAIRE_6640, BONAIRE) +CHIPSET(0x6641, BONAIRE_6641, BONAIRE) +CHIPSET(0x6649, BONAIRE_6649, BONAIRE) +CHIPSET(0x6650, BONAIRE_6650, BONAIRE) +CHIPSET(0x6651, BONAIRE_6651, BONAIRE) +CHIPSET(0x6658, BONAIRE_6658, BONAIRE) +CHIPSET(0x665C, BONAIRE_665C, BONAIRE) +CHIPSET(0x665D, BONAIRE_665D, BONAIRE) commit 0ff7f2760d052503d5cf65ded34a66fe20ccec28 Author: Alex Deucher <ale...@am...> Date: Fri Jun 7 13:45:30 2013 -0400 radeon: add CIK chip families Signed-off-by: Alex Deucher <ale...@am...> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index a74064c..818e26a 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -74,6 +74,9 @@ enum radeon_family { CHIP_VERDE, CHIP_OLAND, CHIP_HAINAN, + CHIP_BONAIRE, + CHIP_KAVERI, + CHIP_KABINI, CHIP_LAST, }; |
From: <da...@ke...> - 2013-10-01 15:39:09
|
include/drm/drm.h | 16 ++++++++++++++++ include/drm/drm_mode.h | 39 +++++++++++++++++++++++++-------------- xf86drm.c | 7 +++++++ xf86drm.h | 2 ++ xf86drmMode.h | 38 ++++++++++++++++++++++++-------------- 5 files changed, 74 insertions(+), 28 deletions(-) New commits: commit ddbbdb13d80ea7f60e6f71356a444995b905366b Author: Damien Lespiau <dam...@in...> Date: Tue Sep 3 15:34:41 2013 +0100 drm: Introduce a drmSetClientCap() wrapper That wraps around the new DRM_SET_CLIENT_CAP ioctl. v2: SET_CAP -> SET_CLIENT_CAP renaming Signed-off-by: Damien Lespiau <dam...@in...> diff --git a/xf86drm.c b/xf86drm.c index 4791a05..720952f 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -823,6 +823,13 @@ int drmGetCap(int fd, uint64_t capability, uint64_t *value) return 0; } +int drmSetClientCap(int fd, uint64_t capability, uint64_t value) +{ + struct drm_set_client_cap cap = { capability, value }; + + return drmIoctl(fd, DRM_IOCTL_SET_CLIENT_CAP, &cap); +} + /** * Free the bus ID information. * diff --git a/xf86drm.h b/xf86drm.h index 5ecb284..1e763a3 100644 --- a/xf86drm.h +++ b/xf86drm.h @@ -609,6 +609,8 @@ extern int drmUpdateDrawableInfo(int fd, drm_drawable_t handle, unsigned int num, void *data); extern int drmCtlInstHandler(int fd, int irq); extern int drmCtlUninstHandler(int fd); +extern int drmSetClientCap(int fd, uint64_t capability, + uint64_t value); /* General user-level programmer's API: authenticated client and/or X */ extern int drmMap(int fd, commit 2dd7054781876a0d5423c7755a7690815f3c2f5f Author: Damien Lespiau <dam...@in...> Date: Tue Sep 3 15:31:49 2013 +0100 drm: Sync the DRM_SET_CLIENT_CAP ioctl definition v2: SET_CAP -> SET_CLIENT_CAP renaming Signed-off-by: Damien Lespiau <dam...@in...> diff --git a/include/drm/drm.h b/include/drm/drm.h index f400642..725bf51 100644 --- a/include/drm/drm.h +++ b/include/drm/drm.h @@ -618,6 +618,21 @@ struct drm_get_cap { __u64 value; }; +/** + * DRM_CLIENT_CAP_STEREO_3D + * + * if set to 1, the DRM core will expose the stereo 3D capabilities of the + * monitor by advertising the supported 3D layouts in the flags of struct + * drm_mode_modeinfo. + */ +#define DRM_CLIENT_CAP_STEREO_3D 1 + +/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ +struct drm_set_client_cap { + __u64 capability; + __u64 value; +}; + #define DRM_CLOEXEC O_CLOEXEC struct drm_prime_handle { __u32 handle; @@ -650,6 +665,7 @@ struct drm_prime_handle { #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) #define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) +#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap) #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) commit edf5c7cde5e10067076cbf79c0cc5d71aa78d7e2 Author: Damien Lespiau <dam...@in...> Date: Fri Aug 23 15:57:40 2013 +0100 drm: Synchronize the stereo 3D mode flags from the kernel headers v2: stereo layouts are now an enum (Daniel Vetter) Signed-off-by: Damien Lespiau <dam...@in...> diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h index d41d76b..c1bb1a3 100644 --- a/include/drm/drm_mode.h +++ b/include/drm/drm_mode.h @@ -42,20 +42,31 @@ /* Video mode flags */ /* bit compatible with the xorg definitions. */ -#define DRM_MODE_FLAG_PHSYNC (1<<0) -#define DRM_MODE_FLAG_NHSYNC (1<<1) -#define DRM_MODE_FLAG_PVSYNC (1<<2) -#define DRM_MODE_FLAG_NVSYNC (1<<3) -#define DRM_MODE_FLAG_INTERLACE (1<<4) -#define DRM_MODE_FLAG_DBLSCAN (1<<5) -#define DRM_MODE_FLAG_CSYNC (1<<6) -#define DRM_MODE_FLAG_PCSYNC (1<<7) -#define DRM_MODE_FLAG_NCSYNC (1<<8) -#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ -#define DRM_MODE_FLAG_BCAST (1<<10) -#define DRM_MODE_FLAG_PIXMUX (1<<11) -#define DRM_MODE_FLAG_DBLCLK (1<<12) -#define DRM_MODE_FLAG_CLKDIV2 (1<<13) +#define DRM_MODE_FLAG_PHSYNC (1<<0) +#define DRM_MODE_FLAG_NHSYNC (1<<1) +#define DRM_MODE_FLAG_PVSYNC (1<<2) +#define DRM_MODE_FLAG_NVSYNC (1<<3) +#define DRM_MODE_FLAG_INTERLACE (1<<4) +#define DRM_MODE_FLAG_DBLSCAN (1<<5) +#define DRM_MODE_FLAG_CSYNC (1<<6) +#define DRM_MODE_FLAG_PCSYNC (1<<7) +#define DRM_MODE_FLAG_NCSYNC (1<<8) +#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ +#define DRM_MODE_FLAG_BCAST (1<<10) +#define DRM_MODE_FLAG_PIXMUX (1<<11) +#define DRM_MODE_FLAG_DBLCLK (1<<12) +#define DRM_MODE_FLAG_CLKDIV2 (1<<13) +#define DRM_MODE_FLAG_3D_MASK (0x1f<<14) +#define DRM_MODE_FLAG_3D_NONE (0<<14) +#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14) +#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14) +#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14) +#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14) +#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14) +#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14) +#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14) +#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14) + /* DPMS flags */ /* bit compatible with the xorg definitions. */ diff --git a/xf86drmMode.h b/xf86drmMode.h index 5bc60ee..7fc52b6 100644 --- a/xf86drmMode.h +++ b/xf86drmMode.h @@ -81,20 +81,30 @@ extern "C" { /* Video mode flags */ /* bit compatible with the xorg definitions. */ -#define DRM_MODE_FLAG_PHSYNC (1<<0) -#define DRM_MODE_FLAG_NHSYNC (1<<1) -#define DRM_MODE_FLAG_PVSYNC (1<<2) -#define DRM_MODE_FLAG_NVSYNC (1<<3) -#define DRM_MODE_FLAG_INTERLACE (1<<4) -#define DRM_MODE_FLAG_DBLSCAN (1<<5) -#define DRM_MODE_FLAG_CSYNC (1<<6) -#define DRM_MODE_FLAG_PCSYNC (1<<7) -#define DRM_MODE_FLAG_NCSYNC (1<<8) -#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ -#define DRM_MODE_FLAG_BCAST (1<<10) -#define DRM_MODE_FLAG_PIXMUX (1<<11) -#define DRM_MODE_FLAG_DBLCLK (1<<12) -#define DRM_MODE_FLAG_CLKDIV2 (1<<13) +#define DRM_MODE_FLAG_PHSYNC (1<<0) +#define DRM_MODE_FLAG_NHSYNC (1<<1) +#define DRM_MODE_FLAG_PVSYNC (1<<2) +#define DRM_MODE_FLAG_NVSYNC (1<<3) +#define DRM_MODE_FLAG_INTERLACE (1<<4) +#define DRM_MODE_FLAG_DBLSCAN (1<<5) +#define DRM_MODE_FLAG_CSYNC (1<<6) +#define DRM_MODE_FLAG_PCSYNC (1<<7) +#define DRM_MODE_FLAG_NCSYNC (1<<8) +#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ +#define DRM_MODE_FLAG_BCAST (1<<10) +#define DRM_MODE_FLAG_PIXMUX (1<<11) +#define DRM_MODE_FLAG_DBLCLK (1<<12) +#define DRM_MODE_FLAG_CLKDIV2 (1<<13) +#define DRM_MODE_FLAG_3D_MASK (0x1f<<14) +#define DRM_MODE_FLAG_3D_NONE (0<<14) +#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14) +#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14) +#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14) +#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14) +#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14) +#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14) +#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14) +#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14) /* DPMS flags */ /* bit compatible with the xorg definitions. */ |
From: <bwi...@ke...> - 2014-01-10 19:07:06
|
include/drm/i915_drm.h | 113 +++++++++++++++++++++++++++++++++++++++++------ intel/intel_bufmgr_gem.c | 8 ++- 2 files changed, 107 insertions(+), 14 deletions(-) New commits: commit a254cb50414a5def5c872a765c0dd1295a550c6b Author: Ben Widawsky <ben...@in...> Date: Thu Jan 2 11:36:59 2014 -0800 intel: Merge latest i915_drm.h This was not done as a straight copy because reset_stats IOCTL landed in libdrm before upstream kernel. Signed-off-by: Ben Widawsky <be...@bw...> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index c1914d6..2f4eb8c 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -27,12 +27,36 @@ #ifndef _I915_DRM_H_ #define _I915_DRM_H_ -#include "drm.h" +#include <drm.h> /* Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints. */ +/** + * DOC: uevents generated by i915 on it's device node + * + * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch + * event from the gpu l3 cache. Additional information supplied is ROW, + * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep + * track of these events and if a specific cache-line seems to have a + * persistent error remap it with the l3 remapping tool supplied in + * intel-gpu-tools. The value supplied with the event is always 1. + * + * I915_ERROR_UEVENT - Generated upon error detection, currently only via + * hangcheck. The error detection event is a good indicator of when things + * began to go badly. The value supplied with the event is a 1 upon error + * detection, and a 0 upon reset completion, signifying no more error + * exists. NOTE: Disabling hangcheck or reset via module parameter will + * cause the related events to not be seen. + * + * I915_RESET_UEVENT - Event is generated just before an attempt to reset the + * the GPU. The value supplied with the event is always 1. NOTE: Disable + * reset via module parameter will cause this event to not be seen. + */ +#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" +#define I915_ERROR_UEVENT "ERROR" +#define I915_RESET_UEVENT "RESET" /* Each region is a minimum of 16k, and there are at most 255 of them. */ @@ -195,8 +219,8 @@ typedef struct _drm_i915_sarea { #define DRM_I915_GEM_WAIT 0x2c #define DRM_I915_GEM_CONTEXT_CREATE 0x2d #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e -#define DRM_I915_GEM_SET_CACHEING 0x2f -#define DRM_I915_GEM_GET_CACHEING 0x30 +#define DRM_I915_GEM_SET_CACHING 0x2f +#define DRM_I915_GEM_GET_CACHING 0x30 #define DRM_I915_REG_READ 0x31 #define DRM_I915_GET_RESET_STATS 0x32 @@ -223,8 +247,8 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) -#define DRM_IOCTL_I915_GEM_SET_CACHEING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing) -#define DRM_IOCTL_I915_GEM_GET_CACHEING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing) +#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) +#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) @@ -305,7 +329,14 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_HAS_LLC 17 #define I915_PARAM_HAS_ALIASING_PPGTT 18 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 -#define I915_PARAM_HAS_VEBOX 22 +#define I915_PARAM_HAS_SEMAPHORES 20 +#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 +#define I915_PARAM_HAS_VEBOX 22 +#define I915_PARAM_HAS_SECURE_BATCHES 23 +#define I915_PARAM_HAS_PINNED_BATCHES 24 +#define I915_PARAM_HAS_EXEC_NO_RELOC 25 +#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 +#define I915_PARAM_HAS_WT 27 typedef struct drm_i915_getparam { int param; @@ -626,7 +657,11 @@ struct drm_i915_gem_exec_object2 { __u64 offset; #define EXEC_OBJECT_NEEDS_FENCE (1<<0) +#define EXEC_OBJECT_NEEDS_GTT (1<<1) +#define EXEC_OBJECT_WRITE (1<<2) +#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1) __u64 flags; + __u64 rsvd1; __u64 rsvd2; }; @@ -672,6 +707,34 @@ struct drm_i915_gem_execbuffer2 { /** Resets the SO write offset registers for transform feedback on gen7. */ #define I915_EXEC_GEN7_SOL_RESET (1<<8) +/** Request a privileged ("secure") batch buffer. Note only available for + * DRM_ROOT_ONLY | DRM_MASTER processes. + */ +#define I915_EXEC_SECURE (1<<9) + +/** Inform the kernel that the batch is and will always be pinned. This + * negates the requirement for a workaround to be performed to avoid + * an incoherent CS (such as can be found on 830/845). If this flag is + * not passed, the kernel will endeavour to make sure the batch is + * coherent with the CS before execution. If this flag is passed, + * userspace assumes the responsibility for ensuring the same. + */ +#define I915_EXEC_IS_PINNED (1<<10) + +/** Provide a hint to the kernel that the command stream and auxilliary + * state buffers already holds the correct presumed addresses and so the + * relocation process may be skipped if no buffers need to be moved in + * preparation for the execbuffer. + */ +#define I915_EXEC_NO_RELOC (1<<11) + +/** Use the reloc.handle as an index into the exec object array rather + * than as the per-file handle. + */ +#define I915_EXEC_HANDLE_LUT (1<<12) + +#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1) + #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) #define i915_execbuffer2_set_context_id(eb2, context) \ (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK @@ -708,21 +771,45 @@ struct drm_i915_gem_busy { __u32 busy; }; -#define I915_CACHEING_NONE 0 -#define I915_CACHEING_CACHED 1 +/** + * I915_CACHING_NONE + * + * GPU access is not coherent with cpu caches. Default for machines without an + * LLC. + */ +#define I915_CACHING_NONE 0 +/** + * I915_CACHING_CACHED + * + * GPU access is coherent with cpu caches and furthermore the data is cached in + * last-level caches shared between cpu cores and the gpu GT. Default on + * machines with HAS_LLC. + */ +#define I915_CACHING_CACHED 1 +/** + * I915_CACHING_DISPLAY + * + * Special GPU caching mode which is coherent with the scanout engines. + * Transparently falls back to I915_CACHING_NONE on platforms where no special + * cache mode (like write-through or gfdt flushing) is available. The kernel + * automatically sets this mode when using a buffer as a scanout target. + * Userspace can manually set this mode to avoid a costly stall and clflush in + * the hotpath of drawing the first frame. + */ +#define I915_CACHING_DISPLAY 2 -struct drm_i915_gem_cacheing { +struct drm_i915_gem_caching { /** - * Handle of the buffer to set/get the cacheing level of. */ + * Handle of the buffer to set/get the caching level of. */ __u32 handle; /** * Cacheing level to apply or return value * - * bits0-15 are for generic cacheing control (i.e. the above defined + * bits0-15 are for generic caching control (i.e. the above defined * values). bits16-31 are reserved for platform-specific variations * (e.g. l3$ caching on gen7). */ - __u32 cacheing; + __u32 caching; }; #define I915_TILING_NONE 0 @@ -962,4 +1049,4 @@ struct drm_i915_reset_stats { __u32 pad; }; -#endif /* _I915_DRM_H_ */ +#endif /* _I915_DRM_H_ */ commit 3d34fe24957576d77c88877ded22e8ab5d96ca4c Author: Ben Widawsky <ben...@in...> Date: Thu Dec 26 16:37:00 2013 -0800 intel: Handle malloc fails in context create The previous code would just use the potentially unallocated variable, which is probably okay most of the time, but not very nice to the user of the library. Signed-off-by: Ben Widawsky <be...@bw...> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 3b1f584..ad722dd 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -3020,15 +3020,19 @@ drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr) drm_intel_context *context = NULL; int ret; + context = calloc(1, sizeof(*context)); + if (!context) + return NULL; + VG_CLEAR(create); ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE, &create); if (ret != 0) { DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno)); + free(context); return NULL; } - context = calloc(1, sizeof(*context)); context->ctx_id = create.ctx_id; context->bufmgr = bufmgr; commit 743372ea26ed38db3aeca4b545e867c1bc08370d Author: Ben Widawsky <ben...@in...> Date: Thu Dec 26 16:30:09 2013 -0800 intel: squash unused variable 'bo_gem' Signed-off-by: Ben Widawsky <be...@bw...> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 48ff62e..3b1f584 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -1337,7 +1337,9 @@ int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo) int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo) { drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; +#ifdef HAVE_VALGRIND drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; +#endif int ret; /* If the CPU cache isn't coherent with the GTT, then use a |
From: <rob...@ke...> - 2014-03-05 15:50:56
|
freedreno/freedreno_device.c | 30 +++--------------------------- freedreno/kgsl/kgsl_bo.c | 17 ++++------------- 2 files changed, 7 insertions(+), 40 deletions(-) New commits: commit ee8c9a1383d4a50871e146ade2fe15b25f3377d4 Author: Rob Clark <rob...@fr...> Date: Fri Feb 28 10:02:59 2014 -0500 freedreno/kgsl: don't even bother trying CREATE_FD Don't even bother trying DRM_KGSL_GEM_CREATE_FD. It hasn't worked since (afaict) 2.6.35 kernels. And in some cases seems to cause some problems. Instead just allocate a minimum size dummy object (just for purposes of having a handle) and then mmap the framebuffer as user-mem (which is deprecated, but seems to still work.. and as far as I can tell is the best option for now). Signed-off-by: Rob Clark <rob...@fr...> diff --git a/freedreno/kgsl/kgsl_bo.c b/freedreno/kgsl/kgsl_bo.c index dd7b612..19a1008 100644 --- a/freedreno/kgsl/kgsl_bo.c +++ b/freedreno/kgsl/kgsl_bo.c @@ -174,28 +174,18 @@ struct fd_bo * kgsl_bo_from_handle(struct fd_device *dev, struct fd_bo * fd_bo_from_fbdev(struct fd_pipe *pipe, int fbfd, uint32_t size) { - struct drm_kgsl_gem_create_fd req = { - .fd = fbfd, - }; struct fd_bo *bo; - struct kgsl_bo *kgsl_bo; if (!is_kgsl_pipe(pipe)) return NULL; - if (drmCommandWriteRead(pipe->dev->fd, DRM_KGSL_GEM_CREATE_FD, - &req, sizeof(req))) { - return NULL; - } - - bo = fd_bo_from_handle(pipe->dev, req.handle, size); - kgsl_bo = to_kgsl_bo(bo); + bo = fd_bo_new(pipe->dev, 1, 0); /* this is fugly, but works around a bug in the kernel.. * priv->memdesc.size never gets set, so getbufinfo ioctl * thinks the buffer hasn't be allocate and fails */ - if (bo && !kgsl_bo_gpuaddr(kgsl_bo, 0)) { + if (bo) { void *fbmem = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, fbfd, 0); struct kgsl_map_user_mem req = { @@ -204,7 +194,9 @@ struct fd_bo * fd_bo_from_fbdev(struct fd_pipe *pipe, .offset = 0, .hostptr = (unsigned long)fbmem, }; + struct kgsl_bo *kgsl_bo = to_kgsl_bo(bo); int ret; + ret = ioctl(to_kgsl_pipe(pipe)->fd, IOCTL_KGSL_MAP_USER_MEM, &req); if (ret) { ERROR_MSG("mapping user mem failed: %s", commit cd1996470aa62116183485c5a3bf5754d69e3457 Author: Rob Clark <rob...@fr...> Date: Fri Feb 28 09:25:10 2014 -0500 freedreno: fix null ptr in error path Signed-off-by: Rob Clark <rob...@fr...> diff --git a/freedreno/freedreno_device.c b/freedreno/freedreno_device.c index 532e65b..598bdfb 100644 --- a/freedreno/freedreno_device.c +++ b/freedreno/freedreno_device.c @@ -117,7 +117,8 @@ struct fd_device * fd_device_new(int fd) struct fd_device * fd_device_new_dup(int fd) { struct fd_device *dev = fd_device_new(dup(fd)); - dev->closefd = 1; + if (dev) + dev->closefd = 1; return dev; } commit 5a3324638b3abb19b30e91ea4dfdd6e1764d6340 Author: Rob Clark <rob...@fr...> Date: Fri Feb 28 09:24:39 2014 -0500 freedreno: simplify device creation Signed-off-by: Rob Clark <rob...@fr...> diff --git a/freedreno/freedreno_device.c b/freedreno/freedreno_device.c index 23e086b..532e65b 100644 --- a/freedreno/freedreno_device.c +++ b/freedreno/freedreno_device.c @@ -34,7 +34,6 @@ #include "freedreno_priv.h" static pthread_mutex_t table_lock = PTHREAD_MUTEX_INITIALIZER; -static void * dev_table; struct fd_device * kgsl_device_new(int fd); struct fd_device * msm_device_new(int fd); @@ -77,7 +76,7 @@ init_cache_buckets(struct fd_device *dev) } } -static struct fd_device * fd_device_new_impl(int fd) +struct fd_device * fd_device_new(int fd) { struct fd_device *dev; drmVersionPtr version; @@ -112,29 +111,6 @@ static struct fd_device * fd_device_new_impl(int fd) return dev; } -struct fd_device * fd_device_new(int fd) -{ - struct fd_device *dev = NULL; - int key = fd; - - pthread_mutex_lock(&table_lock); - - if (!dev_table) - dev_table = drmHashCreate(); - - if (drmHashLookup(dev_table, key, (void **)&dev)) { - dev = fd_device_new_impl(fd); - if (dev) - drmHashInsert(dev_table, key, dev); - } else { - dev = fd_device_ref(dev); - } - - pthread_mutex_unlock(&table_lock); - - return dev; -} - /* like fd_device_new() but creates it's own private dup() of the fd * which is close()d when the device is finalized. */ @@ -156,7 +132,6 @@ static void fd_device_del_impl(struct fd_device *dev) fd_cleanup_bo_cache(dev, 0); drmHashDestroy(dev->handle_table); drmHashDestroy(dev->name_table); - drmHashDelete(dev_table, dev->fd); if (dev->closefd) close(dev->fd); dev->funcs->destroy(dev); diff --git a/freedreno/kgsl/kgsl_bo.c b/freedreno/kgsl/kgsl_bo.c index 76d1f27..dd7b612 100644 --- a/freedreno/kgsl/kgsl_bo.c +++ b/freedreno/kgsl/kgsl_bo.c @@ -222,7 +222,6 @@ fail: return NULL; } - uint32_t kgsl_bo_gpuaddr(struct kgsl_bo *kgsl_bo, uint32_t offset) { struct fd_bo *bo = &kgsl_bo->base; |
From: <rob...@ke...> - 2014-06-20 19:53:23
|
exynos/exynos_fimg2d.c | 4 ++-- exynos/fimg2d.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) New commits: commit e8c3c1358ecaf4e90f7d43762357ae6f8e2022b6 Author: Tobias Jakobi <tj...@ma...> Date: Sun Jun 1 18:04:06 2014 +0200 exynos: fix scaling factor computation in g2d_copy_with_scale When division of source and destination width yields the scaling factor for the x-coordinate, then it should be source/destination _height_ for y. Signed-off-by: Tobias Jakobi <tj...@ma...> Signed-off-by: Inki Dae <ink...@sa...> diff --git a/exynos/exynos_fimg2d.c b/exynos/exynos_fimg2d.c index a565910..fc281b6 100644 --- a/exynos/exynos_fimg2d.c +++ b/exynos/exynos_fimg2d.c @@ -451,7 +451,7 @@ int g2d_copy_with_scale(struct g2d_context *ctx, struct g2d_image *src, else { scale = 1; scale_x = (double)src_w / (double)dst_w; - scale_y = (double)src_w / (double)dst_h; + scale_y = (double)src_h / (double)dst_h; } if (src_x + src_w > src->width) commit 3001c232d14a07153c36a0722e196041d6536d30 Author: Tobias Jakobi <tj...@ma...> Date: Sun Jun 1 18:04:05 2014 +0200 exynos: fix G2D_DOUBLE_TO_FIXED for non-integer input The hardware accepts scaling factors formatted in a fixed-point format. The current macro casts to integer first, then multiplies by the fp conversion factor. This does not make any sense. In particular, truly 'fractional' inputs, like 1.5, won't work that way. Signed-off-by: Tobias Jakobi <tj...@ma...> Signed-off-by: Inki Dae <ink...@sa...> diff --git a/exynos/fimg2d.h b/exynos/fimg2d.h index 1aac378..4785e2f 100644 --- a/exynos/fimg2d.h +++ b/exynos/fimg2d.h @@ -25,7 +25,7 @@ #define G2D_MAX_CMD_LIST_NR 64 #define G2D_PLANE_MAX_NR 2 -#define G2D_DOUBLE_TO_FIXED(d) ((unsigned int)(d) * 65536.0) +#define G2D_DOUBLE_TO_FIXED(d) ((unsigned int)((d) * 65536.0)) enum e_g2d_color_mode { /* COLOR FORMAT */ commit 63f51fc4d34814c80d452e03814b5b495548987b Author: Tobias Jakobi <tj...@ma...> Date: Sun Jun 1 18:04:04 2014 +0200 exynos: fix coordinate computation in g2d_copy The right-bottom register isn't set correctly. Looks like a copy-and-paste error. Signed-off-by: Tobias Jakobi <tj...@ma...> Signed-off-by: Inki Dae <ink...@sa...> diff --git a/exynos/exynos_fimg2d.c b/exynos/exynos_fimg2d.c index 0b14618..a565910 100644 --- a/exynos/exynos_fimg2d.c +++ b/exynos/exynos_fimg2d.c @@ -382,7 +382,7 @@ int g2d_copy(struct g2d_context *ctx, struct g2d_image *src, g2d_add_cmd(ctx, DST_LEFT_TOP_REG, pt.val); pt.val = 0; pt.data.x = dst_x + w; - pt.data.y = dst_x + h; + pt.data.y = dst_y + h; g2d_add_cmd(ctx, DST_RIGHT_BOTTOM_REG, pt.val); rop4.val = 0; |
From: <da...@ke...> - 2014-09-30 11:20:02
|
intel/intel_bufmgr_gem.c | 2 ++ intel/intel_chipset.h | 43 ++++++++++++++++++++++++++++++++++++++++++- intel/intel_decode.c | 4 +++- 3 files changed, 47 insertions(+), 2 deletions(-) New commits: commit 00847fa48b83a85b0cb882594a12ed1511f780db Author: Damien Lespiau <dam...@in...> Date: Wed Feb 13 16:09:38 2013 +0000 intel/skl: add gen9 to the CS decoding init Signed-off-by: Damien Lespiau <dam...@in...> Reviewed-by: Kenneth Graunke <ke...@wh...> Signed-off-by: Ben Widawsky <be...@bw...> diff --git a/intel/intel_decode.c b/intel/intel_decode.c index a5d6e04..7d5cbe5 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -3829,7 +3829,9 @@ drm_intel_decode_context_alloc(uint32_t devid) ctx->devid = devid; ctx->out = stdout; - if (IS_GEN8(devid)) + if (IS_GEN9(devid)) + ctx->gen = 9; + else if (IS_GEN8(devid)) ctx->gen = 8; else if (IS_GEN7(devid)) ctx->gen = 7; commit f1e15d1221288bcc010a743d46ffe37d4216dbea Author: Damien Lespiau <dam...@in...> Date: Wed Feb 13 16:09:37 2013 +0000 intel/skl: Add gen9 to the buffer manager init Signed-off-by: Damien Lespiau <dam...@in...> Reviewed-by: Kenneth Graunke <ke...@wh...> Signed-off-by: Ben Widawsky <be...@bw...> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index ee69cf8..f2f4fea 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -3478,6 +3478,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) bufmgr_gem->gen = 7; else if (IS_GEN8(bufmgr_gem->pci_device)) bufmgr_gem->gen = 8; + else if (IS_GEN9(bufmgr_gem->pci_device)) + bufmgr_gem->gen = 9; else { free(bufmgr_gem); bufmgr_gem = NULL; commit c19a9867ab35834b0fc6a8b0cb8d19382424ff07 Author: Damien Lespiau <dam...@in...> Date: Mon Jan 20 19:40:39 2014 +0000 intel/skl: Add SKL PCI ids v2: Add more PCI IDs (Michael H. Nguyen) v3: Synchronize one more with the kernel PCI IDs (Damien) Reviewed-by: Thomas Wood <tho...@in...> Signed-off-by: Damien Lespiau <dam...@in...> Signed-off-by: Ben Widawsky <ben...@in...> Signed-off-by: Michael H. Nguyen <mic...@in...> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 6f9bfad..e22a867 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -165,6 +165,22 @@ #define PCI_CHIP_CHERRYVIEW_2 0x22b2 #define PCI_CHIP_CHERRYVIEW_3 0x22b3 +#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916 +#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906 +#define PCI_CHIP_SKYLAKE_ULT_GT3 0x1926 +#define PCI_CHIP_SKYLAKE_ULT_GT2F 0x1921 +#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E +#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E +#define PCI_CHIP_SKYLAKE_DT_GT2 0x1912 +#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902 +#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B +#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B +#define PCI_CHIP_SKYLAKE_HALO_GT1 0x190B +#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A +#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192A +#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A +#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D + #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ (devid) == PCI_CHIP_I945_GM || \ @@ -324,12 +340,37 @@ #define IS_GEN8(devid) (IS_BROADWELL(devid) || \ IS_CHERRYVIEW(devid)) +#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \ + (devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \ + (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ + (devid) == PCI_CHIP_SKYLAKE_HALO_GT1 || \ + (devid) == PCI_CHIP_SKYLAKE_SRV_GT1) + +#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \ + (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F || \ + (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \ + (devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \ + (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \ + (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \ + (devid) == PCI_CHIP_SKYLAKE_WKS_GT2) + +#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3 || \ + (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \ + (devid) == PCI_CHIP_SKYLAKE_SRV_GT3) + +#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ + IS_SKL_GT2(devid) || \ + IS_SKL_GT3(devid)) + +#define IS_GEN9(devid) IS_SKYLAKE(devid) + #define IS_9XX(dev) (IS_GEN3(dev) || \ IS_GEN4(dev) || \ IS_GEN5(dev) || \ IS_GEN6(dev) || \ IS_GEN7(dev) || \ - IS_GEN8(dev)) + IS_GEN8(dev) || \ + IS_GEN9(dev)) #endif /* _INTEL_CHIPSET_H */ |
From: <eve...@ke...> - 2015-02-23 09:34:09
|
freedreno/Android.mk | 3 --- intel/Android.mk | 2 -- libdrm.h | 2 +- nouveau/Android.mk | 3 --- radeon/Android.mk | 3 --- xf86drm.c | 39 +++++++++++++++++++++++++++++++++++++++ xf86drm.h | 1 + 7 files changed, 41 insertions(+), 12 deletions(-) New commits: commit 1f73578df32f895a678a41758f6c563f49484347 Author: Frank Binns <fra...@im...> Date: Fri Feb 13 10:51:15 2015 +0000 Add new drmGetNodeTypeFromFd function Add a helper function that returns the type of device node from an fd. Signed-off-by: Frank Binns <fra...@im...> Reviewed-by: Emil Velikov <emi...@gm...> diff --git a/xf86drm.c b/xf86drm.c index d85115c..e117bc6 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -505,6 +505,23 @@ static int drmGetMinorBase(int type) }; } +static int drmGetMinorType(int minor) +{ + int type = minor >> 6; + + if (minor < 0) + return -1; + + switch (type) { + case DRM_NODE_PRIMARY: + case DRM_NODE_CONTROL: + case DRM_NODE_RENDER: + return type; + default: + return -1; + } +} + /** * Open the device by bus ID. * @@ -2667,6 +2684,28 @@ char *drmGetDeviceNameFromFd(int fd) return strdup(name); } +int drmGetNodeTypeFromFd(int fd) +{ + struct stat sbuf; + int maj, min, type; + + if (fstat(fd, &sbuf)) + return -1; + + maj = major(sbuf.st_rdev); + min = minor(sbuf.st_rdev); + + if (maj != DRM_MAJOR || !S_ISCHR(sbuf.st_mode)) { + errno = EINVAL; + return -1; + } + + type = drmGetMinorType(min); + if (type == -1) + errno = ENODEV; + return type; +} + int drmPrimeHandleToFD(int fd, uint32_t handle, uint32_t flags, int *prime_fd) { struct drm_prime_handle args; diff --git a/xf86drm.h b/xf86drm.h index 77937eb..afd38a1 100644 --- a/xf86drm.h +++ b/xf86drm.h @@ -744,6 +744,7 @@ typedef struct _drmEventContext { extern int drmHandleEvent(int fd, drmEventContextPtr evctx); extern char *drmGetDeviceNameFromFd(int fd); +extern int drmGetNodeTypeFromFd(int fd); extern int drmPrimeHandleToFD(int fd, uint32_t handle, uint32_t flags, int *prime_fd); extern int drmPrimeFDToHandle(int fd, int prime_fd, uint32_t *handle); commit 5c1c09e0d28cde4341777b966c21568fd9b51516 Author: Chih-Wei Huang <cw...@li...> Date: Fri Jan 23 14:25:10 2015 +0800 android: remove duplicate libdrm in LOCAL_SHARED_LIBRARIES v2: Fold libpciaccess and libdrm into a single local_shared_libraries Acked-by: Jan Vesely <jan...@ru...> Signed-off-by: Chih-Wei Huang <cw...@li...> Signed-off-by: Emil Velikov <emi...@gm...> diff --git a/freedreno/Android.mk b/freedreno/Android.mk index 243a1e2..22520fb 100644 --- a/freedreno/Android.mk +++ b/freedreno/Android.mk @@ -24,7 +24,4 @@ LOCAL_CFLAGS := \ LOCAL_COPY_HEADERS := $(LIBDRM_FREEDRENO_H_FILES) LOCAL_COPY_HEADERS_TO := freedreno -LOCAL_SHARED_LIBRARIES := \ - libdrm - include $(BUILD_SHARED_LIBRARY) diff --git a/intel/Android.mk b/intel/Android.mk index f2f21b9..202c0d5 100644 --- a/intel/Android.mk +++ b/intel/Android.mk @@ -30,8 +30,6 @@ include $(LOCAL_PATH)/Makefile.sources LOCAL_MODULE := libdrm_intel LOCAL_MODULE_TAGS := optional -LOCAL_SHARED_LIBRARIES := libdrm - LOCAL_SRC_FILES := $(LIBDRM_INTEL_FILES) LOCAL_EXPORT_C_INCLUDE_DIRS += \ $(LOCAL_PATH)/intel diff --git a/nouveau/Android.mk b/nouveau/Android.mk index 734fc21..93c9ec2 100644 --- a/nouveau/Android.mk +++ b/nouveau/Android.mk @@ -24,7 +24,4 @@ LOCAL_CFLAGS := \ LOCAL_COPY_HEADERS := $(LIBDRM_NOUVEAU_H_FILES) LOCAL_COPY_HEADERS_TO := libdrm -LOCAL_SHARED_LIBRARIES := \ - libdrm - include $(BUILD_SHARED_LIBRARY) diff --git a/radeon/Android.mk b/radeon/Android.mk index 9cba546..71c58bd 100644 --- a/radeon/Android.mk +++ b/radeon/Android.mk @@ -24,7 +24,4 @@ LOCAL_CFLAGS := \ LOCAL_COPY_HEADERS := $(LIBDRM_RADEON_H_FILES) LOCAL_COPY_HEADERS_TO := libdrm -LOCAL_SHARED_LIBRARIES := \ - libdrm - include $(BUILD_SHARED_LIBRARY) commit 8eb1da817e115cc4210699d899b0d85f26e9e30a Author: Emil Velikov <emi...@gm...> Date: Thu Jan 29 02:04:35 2015 +0000 libdrm: fix the Android 64bit build With 64bit bionic mmap now handles 64bit offset, thus we no longer need the __mmap2 trick. Fix from Chih-Wei Huang, over at the google forums. Cc: Chih-Wei Huang <cw...@an...> Signed-off-by: Emil Velikov <emi...@gm...> diff --git a/libdrm.h b/libdrm.h index acfada5..6c3cd59 100644 --- a/libdrm.h +++ b/libdrm.h @@ -45,7 +45,7 @@ #include <sys/mman.h> -#if defined(ANDROID) +#if defined(ANDROID) && !defined(__LP64__) #include <errno.h> /* for EINVAL */ extern void *__mmap2(void *, size_t, int, int, int, size_t); |
From: <da...@ke...> - 2015-03-20 15:56:39
|
RELEASING | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) New commits: commit e2acca4e40c87b00af75a5ffedafc26a099b657c Author: Damien Lespiau <dam...@in...> Date: Thu Mar 19 16:29:52 2015 +0000 RELEASING: Fix annouce typo That's the only typo :set spell found. v2: Fix typo in commit message (Ilia Mirkin) Reviewed-by: Emil Velikov <emi...@gm...> Signed-off-by: Damien Lespiau <dam...@in...> diff --git a/RELEASING b/RELEASING index 203b88b..62c5be9 100644 --- a/RELEASING +++ b/RELEASING @@ -51,7 +51,7 @@ Follow these steps to release a new version of libdrm: 7) Use the release.sh script from the xorg/util/modular repo to upload the tarballs to the freedesktop.org download area and - create an annouce email template. The script takes one argument: + create an announce email template. The script takes one argument: the path to the libdrm checkout. So, if a checkout of modular is at the same level than the libdrm repo: commit 992940ca645f8dcda24015770d48afad0fd95b9d Author: Damien Lespiau <dam...@in...> Date: Thu Mar 19 16:27:31 2015 +0000 RELEASING: Fix the step numbering v2: Really fix the numbering (Emil Velikov) Reviewed-by: Emil Velikov <emi...@gm...> Signed-off-by: Damien Lespiau <dam...@in...> diff --git a/RELEASING b/RELEASING index e17dbea..203b88b 100644 --- a/RELEASING +++ b/RELEASING @@ -13,14 +13,14 @@ Follow these steps to release a new version of libdrm: modifications. You're probably in a good state if both "git diff HEAD" and "git log master..origin/master" give no output. - 3) Bump the version number in configure.ac. We seem to have settled + 2) Bump the version number in configure.ac. We seem to have settled for 2.4.x as the versioning scheme for libdrm, so just bump the micro version. - 4) Run autoconf and then re-run ./configure so the build system + 3) Run autoconf and then re-run ./configure so the build system picks up the new version number. - 5) (optional step, release.sh will make distcheck for you, but it can be + 4) (optional step, release.sh will make distcheck for you, but it can be heart warming to verify that make distcheck passes) Verify that the code passes "make distcheck". Running "make @@ -36,20 +36,20 @@ Follow these steps to release a new version of libdrm: Make sure that the version number reported by distcheck and in the tarball names matches the number you bumped to in configure.ac. - 6) Commit the configure.ac change and make an annotated tag for that + 5) Commit the configure.ac change and make an annotated tag for that commit with the version number of the release as the name and a message of "libdrm X.Y.Z". For example, for the 2.4.16 release the command is: git tag -a 2.4.16 -m "libdrm 2.4.16" - 7) Push the commit and tag by saying + 6) Push the commit and tag by saying git push --tags origin master assuming the remote for the upstream libdrm repo is called origin. - 6) Use the release.sh script from the xorg/util/modular repo to + 7) Use the release.sh script from the xorg/util/modular repo to upload the tarballs to the freedesktop.org download area and create an annouce email template. The script takes one argument: the path to the libdrm checkout. So, if a checkout of modular is commit 8f245b777b21e8c0151f9a254a56a7cb23b66d15 Author: Damien Lespiau <dam...@in...> Date: Thu Mar 19 16:24:49 2015 +0000 RELEASING: Fix releasing instructions to match the latest release.sh It seems that the tests don't need DRM master anymore? at least make distcheck passes when X is running. release.sh is also invoked with just the path to the libdrm git checkout and we don't want to pass additional arguments that will be treated as additional modules we want to release. Also, make a note that release.sh will run make distcheck for you, so we don't strickly need to run it beforehand. Reviewed-by: Emil Velikov <emi...@gm...> Signed-off-by: Damien Lespiau <dam...@in...> diff --git a/RELEASING b/RELEASING index 3f07146..e17dbea 100644 --- a/RELEASING +++ b/RELEASING @@ -20,13 +20,12 @@ Follow these steps to release a new version of libdrm: 4) Run autoconf and then re-run ./configure so the build system picks up the new version number. - 5) Verify that the code passes "make distcheck". libdrm is tricky - to distcheck since the test suite will need to become drm master. - This means that you need to run it outside X, that is, in text - mode (KMS or no KMS doesn't matter). + 5) (optional step, release.sh will make distcheck for you, but it can be + heart warming to verify that make distcheck passes) - Running "make distcheck" should result in no warnings or errors - and end with a message of the form: + Verify that the code passes "make distcheck". Running "make + distcheck" should result in no warnings or errors and end with a + message of the form: ============================================= libdrm-X.Y.Z archives ready for distribution: @@ -52,11 +51,11 @@ Follow these steps to release a new version of libdrm: 6) Use the release.sh script from the xorg/util/modular repo to upload the tarballs to the freedesktop.org download area and - create an annouce email template. The script takes three - arguments: a "section", the previous tag and the new tag we just - created. For 2.4.16 again, the command is: + create an annouce email template. The script takes one argument: + the path to the libdrm checkout. So, if a checkout of modular is + at the same level than the libdrm repo: - ../modular/release.sh libdrm 2.4.15 2.4.16 + ./modular/release.sh libdrm This copies the two tarballs to freedesktop.org and creates libdrm-2.4.16.announce which has a detailed summary of the |
From: <eve...@ke...> - 2015-04-29 18:42:38
|
Android.mk | 1 + freedreno/Makefile.am | 5 ++++- tests/modetest/buffers.c | 4 ++-- 3 files changed, 7 insertions(+), 3 deletions(-) New commits: commit b4a6f50f2afdbd1b3762bb518f680aa88d44c517 Author: Emil Velikov <emi...@gm...> Date: Wed Apr 1 16:53:42 2015 +0100 freedreno: link against CLOCK_LIB Required by clock_gettime() Cc: Rob Clark <rob...@gm...> Signed-off-by: Emil Velikov <emi...@gm...> diff --git a/freedreno/Makefile.am b/freedreno/Makefile.am index 0720867..9b7ec7d 100644 --- a/freedreno/Makefile.am +++ b/freedreno/Makefile.am @@ -10,7 +10,10 @@ AM_CFLAGS = \ libdrm_freedreno_la_LTLIBRARIES = libdrm_freedreno.la libdrm_freedreno_ladir = $(libdir) libdrm_freedreno_la_LDFLAGS = -version-number 1:0:0 -no-undefined -libdrm_freedreno_la_LIBADD = ../libdrm.la @PTHREADSTUBS_LIBS@ +libdrm_freedreno_la_LIBADD = \ + ../libdrm.la \ + @PTHREADSTUBS_LIBS@ \ + @CLOCK_LIB@ libdrm_freedreno_la_SOURCES = $(LIBDRM_FREEDRENO_FILES) if HAVE_FREEDRENO_KGSL commit 9dd2e8e552a5c290bc52190e074db1b3843faaf8 Author: Emil Velikov <emi...@gm...> Date: Wed Apr 1 16:54:26 2015 +0100 android: set the HAVE_VISIBILITY define ... in order to limit the exported symbols only to the required ones. Both compilers used with Android (GCC and LLVM) support this, so set it unconditionally. Cc: Chih-Wei Huang <cw...@li...> Signed-off-by: Emil Velikov <emi...@gm...> diff --git a/Android.mk b/Android.mk index 7038c3c..90cdcb3 100644 --- a/Android.mk +++ b/Android.mk @@ -39,6 +39,7 @@ LOCAL_C_INCLUDES := \ $(LOCAL_PATH)/include/drm LOCAL_CFLAGS := \ + -DHAVE_VISIBILITY=1 \ -DHAVE_LIBDRM_ATOMIC_PRIMITIVES=1 include $(BUILD_SHARED_LIBRARY) commit b091ecdbf93fca76521868863fb1f20e0bfe7268 Author: Joonyoung Shim <jy0...@sa...> Date: Fri Apr 17 13:13:59 2015 +0900 modetest: fix the arguments of the MAKE_RGB_INFO define The current order (rbg) seems wrong. Signed-off-by: Joonyoung Shim <jy0...@sa...> [Emil Velikov: Tweak the commit message.] Reviewed-by: Emil Velikov <emi...@gm...> diff --git a/tests/modetest/buffers.c b/tests/modetest/buffers.c index 878b64e..6f5feab 100644 --- a/tests/modetest/buffers.c +++ b/tests/modetest/buffers.c @@ -98,8 +98,8 @@ struct format_info { const struct yuv_info yuv; }; -#define MAKE_RGB_INFO(rl, ro, bl, bo, gl, go, al, ao) \ - .rgb = { { (rl), (ro) }, { (bl), (bo) }, { (gl), (go) }, { (al), (ao) } } +#define MAKE_RGB_INFO(rl, ro, gl, go, bl, bo, al, ao) \ + .rgb = { { (rl), (ro) }, { (gl), (go) }, { (bl), (bo) }, { (al), (ao) } } #define MAKE_YUV_INFO(order, xsub, ysub, chroma_stride) \ .yuv = { (order), (xsub), (ysub), (chroma_stride) } |
From: <tp...@ke...> - 2015-08-10 08:31:20
|
intel/intel_bufmgr.h | 8 ++++++++ libkms/libkms.h | 4 ++-- tests/modeprint/modeprint.c | 4 +--- xf86drm.h | 4 ++-- xf86drmMode.h | 4 ++-- 5 files changed, 15 insertions(+), 9 deletions(-) New commits: commit d7f58da11a51cec48e56299ac722c5f0ca1aec32 Author: Tapani Pälli <tap...@in...> Date: Fri Aug 7 10:37:58 2015 +0300 modeprint: cleanup, remove compile warnings Signed-off-by: Tapani Pälli <tap...@in...> Reviewed-by: Thierry Reding <tr...@nv...> Reviewed-by: Emil Velikov <emi...@gm...> diff --git a/tests/modeprint/modeprint.c b/tests/modeprint/modeprint.c index e6c6553..5e953f7 100644 --- a/tests/modeprint/modeprint.c +++ b/tests/modeprint/modeprint.c @@ -61,6 +61,7 @@ static const char* getConnectionText(drmModeConnection conn) return "connected"; case DRM_MODE_DISCONNECTED: return "disconnected"; + case DRM_MODE_UNKNOWNCONNECTION: default: return "unknown"; } @@ -124,9 +125,6 @@ static int printProperty(int fd, drmModeResPtr res, drmModePropertyPtr props, ui } } else { - if (!strncmp(props->name, "DPMS", 4)) - ; - for (j = 0; j < props->count_enums; j++) { printf("\t\t%lld = %s\n", props->enums[j].value, props->enums[j].name); if (props->enums[j].value == value) commit f1468e88461239d3060f146fae6c36cc7b85f366 Author: Tapani Pälli <tap...@in...> Date: Fri Aug 7 10:37:57 2015 +0300 intel: wrap intel_bufmgr.h C code for C++ compilation/linking We need this include in porting changes for the OpenGL ES conformance suite. v2: remove c_plusplus usage Signed-off-by: Tapani Pälli <tap...@in...> Reviewed-by: Emil Velikov <emi...@gm...> diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h index 285919e..95eecb8 100644 --- a/intel/intel_bufmgr.h +++ b/intel/intel_bufmgr.h @@ -38,6 +38,10 @@ #include <stdint.h> #include <stdio.h> +#if defined(__cplusplus) +extern "C" { +#endif + struct drm_clip_rect; typedef struct _drm_intel_bufmgr drm_intel_bufmgr; @@ -308,4 +312,8 @@ int drm_intel_get_eu_total(int fd, unsigned int *eu_total); /** @{ */ +#if defined(__cplusplus) +} +#endif + #endif /* INTEL_BUFMGR_H */ commit 1c205749fe2171aaa69ce053a8f248e329bd72f7 Author: Tapani Pälli <tap...@in...> Date: Fri Aug 7 10:37:56 2015 +0300 remove usage of 'c_plusplus' preprocessor macro Use only __cplusplus which is supported by the C++ standard. Signed-off-by: Tapani Pälli <tap...@in...> Reviewed-by: Emil Velikov <emi...@gm...> diff --git a/libkms/libkms.h b/libkms/libkms.h index c00b159..930a2bf 100644 --- a/libkms/libkms.h +++ b/libkms/libkms.h @@ -29,7 +29,7 @@ #ifndef _LIBKMS_H_ #define _LIBKMS_H_ -#if defined(__cplusplus) || defined(c_plusplus) +#if defined(__cplusplus) extern "C" { #endif @@ -75,7 +75,7 @@ int kms_bo_map(struct kms_bo *bo, void **out); int kms_bo_unmap(struct kms_bo *bo); int kms_bo_destroy(struct kms_bo **bo); -#if defined(__cplusplus) || defined(c_plusplus) +#if defined(__cplusplus) }; #endif diff --git a/xf86drm.h b/xf86drm.h index e3a19dc..360e04a 100644 --- a/xf86drm.h +++ b/xf86drm.h @@ -39,7 +39,7 @@ #include <stdint.h> #include <drm.h> -#if defined(__cplusplus) || defined(c_plusplus) +#if defined(__cplusplus) extern "C" { #endif @@ -759,7 +759,7 @@ extern int drmPrimeFDToHandle(int fd, int prime_fd, uint32_t *handle); extern char *drmGetPrimaryDeviceNameFromFd(int fd); extern char *drmGetRenderDeviceNameFromFd(int fd); -#if defined(__cplusplus) || defined(c_plusplus) +#if defined(__cplusplus) } #endif diff --git a/xf86drmMode.h b/xf86drmMode.h index 1c10023..4de7bbb 100644 --- a/xf86drmMode.h +++ b/xf86drmMode.h @@ -36,7 +36,7 @@ #ifndef _XF86DRMMODE_H_ #define _XF86DRMMODE_H_ -#if defined(__cplusplus) || defined(c_plusplus) +#if defined(__cplusplus) extern "C" { #endif @@ -508,7 +508,7 @@ extern int drmModeCreatePropertyBlob(int fd, const void *data, size_t size, extern int drmModeDestroyPropertyBlob(int fd, uint32_t id); -#if defined(__cplusplus) || defined(c_plusplus) +#if defined(__cplusplus) } #endif |
From: <ag...@ke...> - 2015-08-17 20:35:45
|
amdgpu/amdgpu.h | 5 +++ amdgpu/amdgpu_device.c | 33 +++++++++++++++++++++++- amdgpu/amdgpu_internal.h | 13 +++++---- amdgpu/amdgpu_vamgr.c | 63 ++++++++++++++++++++++------------------------- 4 files changed, 73 insertions(+), 41 deletions(-) New commits: commit 56d8dd6a9c03680700e0b0043cb56e0af7e3e3de Author: Jammy Zhou <Jam...@am...> Date: Mon Aug 17 11:09:09 2015 +0800 amdgpu: make vamgr per device v2 Each device can have its own vamgr, so make it per device now. This can fix the failure with multiple GPUs used in one single process. v2: rebase Signed-off-by: Jammy Zhou <Jam...@am...> Reviewed-by: Christian König <chr...@am...> diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index e16cd24..75b12e2 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -130,7 +130,8 @@ static int amdgpu_get_auth(int fd, int *auth) static void amdgpu_device_free_internal(amdgpu_device_handle dev) { - amdgpu_vamgr_reference(&dev->vamgr, NULL); + amdgpu_vamgr_deinit(dev->vamgr); + free(dev->vamgr); util_hash_table_destroy(dev->bo_flink_names); util_hash_table_destroy(dev->bo_handles); pthread_mutex_destroy(&dev->bo_table_mutex); @@ -251,7 +252,13 @@ int amdgpu_device_initialize(int fd, if (r) goto cleanup; - dev->vamgr = amdgpu_vamgr_get_global(dev); + dev->vamgr = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); + if (dev->vamgr == NULL) + goto cleanup; + + amdgpu_vamgr_init(dev->vamgr, dev->dev_info.virtual_address_offset, + dev->dev_info.virtual_address_max, + dev->dev_info.virtual_address_alignment); max = MIN2(dev->dev_info.virtual_address_max, 0xffffffff); start = amdgpu_vamgr_find_va(dev->vamgr, @@ -278,6 +285,8 @@ free_va: r = -ENOMEM; amdgpu_vamgr_free_va(dev->vamgr, start, max - dev->dev_info.virtual_address_offset); + amdgpu_vamgr_deinit(dev->vamgr); + free(dev->vamgr); cleanup: if (dev->fd >= 0) diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 3ce0969..5d86603 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -52,7 +52,6 @@ struct amdgpu_bo_va_hole { }; struct amdgpu_bo_va_mgr { - atomic_t refcount; /* the start virtual address */ uint64_t va_offset; uint64_t va_max; @@ -125,13 +124,6 @@ struct amdgpu_context { drm_private void amdgpu_bo_free_internal(amdgpu_bo_handle bo); -drm_private struct amdgpu_bo_va_mgr* -amdgpu_vamgr_get_global(struct amdgpu_device *dev); - -drm_private void -amdgpu_vamgr_reference(struct amdgpu_bo_va_mgr **dst, - struct amdgpu_bo_va_mgr *src); - drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, uint64_t max, uint64_t alignment); diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index 507a73a..04d2881 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -33,8 +33,6 @@ #include "amdgpu_internal.h" #include "util_math.h" -static struct amdgpu_bo_va_mgr vamgr = {{0}}; - int amdgpu_va_range_query(amdgpu_device_handle dev, enum amdgpu_gpu_va_range type, uint64_t *start, uint64_t *end) { @@ -67,28 +65,6 @@ drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr) pthread_mutex_destroy(&mgr->bo_va_mutex); } -drm_private struct amdgpu_bo_va_mgr * -amdgpu_vamgr_get_global(struct amdgpu_device *dev) -{ - int ref; - ref = atomic_inc_return(&vamgr.refcount); - - if (ref == 1) - amdgpu_vamgr_init(&vamgr, dev->dev_info.virtual_address_offset, - dev->dev_info.virtual_address_max, - dev->dev_info.virtual_address_alignment); - return &vamgr; -} - -drm_private void -amdgpu_vamgr_reference(struct amdgpu_bo_va_mgr **dst, - struct amdgpu_bo_va_mgr *src) -{ - if (update_references(&(*dst)->refcount, NULL)) - amdgpu_vamgr_deinit(*dst); - *dst = src; -} - drm_private uint64_t amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, uint64_t alignment, uint64_t base_required) @@ -105,7 +81,7 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, pthread_mutex_lock(&mgr->bo_va_mutex); /* TODO: using more appropriate way to track the holes */ /* first look for a hole */ - LIST_FOR_EACH_ENTRY_SAFE(hole, n, &vamgr.va_holes, list) { + LIST_FOR_EACH_ENTRY_SAFE(hole, n, &mgr->va_holes, list) { if (base_required) { if(hole->offset > base_required || (hole->offset + hole->size) < (base_required + size)) commit ffa305d0fc926418e4dff432381ead8907dc18d9 Author: Jammy Zhou <Jam...@am...> Date: Mon Aug 17 11:09:08 2015 +0800 amdgpu: add flag to support 32bit VA address v4 The AMDGPU_VA_RANGE_32_BIT flag is added to request VA range in the 32bit address space for amdgpu_va_range_alloc. The 32bit address space is reserved at initialization time, and managed with a separate VAMGR as part of the global VAMGR. And if no enough VA space available in range above 4GB, this reserved range can be used as fallback. v2: add comment for AMDGPU_VA_RANGE_32_BIT, and add vamgr to va_range v3: rebase to Emil's drm_private series v4: fix one warning Signed-off-by: Jammy Zhou <Jam...@am...> Reviewed-by: Christian König <chr...@am...> diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index a3eea84..e44d802 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -1075,6 +1075,11 @@ int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset, uint32_t *values); /** + * Flag to request VA address range in the 32bit address space +*/ +#define AMDGPU_VA_RANGE_32_BIT 0x1 + +/** * Allocate virtual address range * * \param dev - [in] Device handle. See #amdgpu_device_initialize() diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index c6bbae8..e16cd24 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -43,6 +43,7 @@ #include "amdgpu_drm.h" #include "amdgpu_internal.h" #include "util_hash_table.h" +#include "util_math.h" #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x))) #define UINT_TO_PTR(x) ((void *)((intptr_t)(x))) @@ -173,6 +174,7 @@ int amdgpu_device_initialize(int fd, int flag_auth = 0; int flag_authexist=0; uint32_t accel_working = 0; + uint64_t start, max; *device_handle = NULL; @@ -251,6 +253,19 @@ int amdgpu_device_initialize(int fd, dev->vamgr = amdgpu_vamgr_get_global(dev); + max = MIN2(dev->dev_info.virtual_address_max, 0xffffffff); + start = amdgpu_vamgr_find_va(dev->vamgr, + max - dev->dev_info.virtual_address_offset, + dev->dev_info.virtual_address_alignment, 0); + if (start > 0xffffffff) + goto free_va; /* shouldn't get here */ + + dev->vamgr_32 = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); + if (dev->vamgr_32 == NULL) + goto free_va; + amdgpu_vamgr_init(dev->vamgr_32, start, max, + dev->dev_info.virtual_address_alignment); + *major_version = dev->major_version; *minor_version = dev->minor_version; *device_handle = dev; @@ -259,6 +274,11 @@ int amdgpu_device_initialize(int fd, return 0; +free_va: + r = -ENOMEM; + amdgpu_vamgr_free_va(dev->vamgr, start, + max - dev->dev_info.virtual_address_offset); + cleanup: if (dev->fd >= 0) close(dev->fd); diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 4b07aff..3ce0969 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -66,6 +66,7 @@ struct amdgpu_va { uint64_t address; uint64_t size; enum amdgpu_gpu_va_range range; + struct amdgpu_bo_va_mgr *vamgr; }; struct amdgpu_device { @@ -83,7 +84,10 @@ struct amdgpu_device { pthread_mutex_t bo_table_mutex; struct drm_amdgpu_info_device dev_info; struct amdgpu_gpu_info info; + /** The global VA manager for the whole virtual address space */ struct amdgpu_bo_va_mgr *vamgr; + /** The VA manager for the 32bit address space */ + struct amdgpu_bo_va_mgr *vamgr_32; }; struct amdgpu_bo { @@ -128,6 +132,11 @@ drm_private void amdgpu_vamgr_reference(struct amdgpu_bo_va_mgr **dst, struct amdgpu_bo_va_mgr *src); +drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, + uint64_t max, uint64_t alignment); + +drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr); + drm_private uint64_t amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, uint64_t alignment, uint64_t base_required); diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index eef8a71..507a73a 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -46,7 +46,7 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, return -EINVAL; } -static void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, +drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, uint64_t max, uint64_t alignment) { mgr->va_offset = start; @@ -57,7 +57,7 @@ static void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, pthread_mutex_init(&mgr->bo_va_mutex, NULL); } -static void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr) +drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr) { struct amdgpu_bo_va_hole *hole; LIST_FOR_EACH_ENTRY(hole, &mgr->va_holes, list) { @@ -255,23 +255,39 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, amdgpu_va_handle *va_range_handle, uint64_t flags) { - va_base_alignment = MAX2(va_base_alignment, dev->vamgr->va_alignment); - size = ALIGN(size, vamgr.va_alignment); + struct amdgpu_bo_va_mgr *vamgr; - *va_base_allocated = amdgpu_vamgr_find_va(dev->vamgr, size, + if (flags & AMDGPU_VA_RANGE_32_BIT) + vamgr = dev->vamgr_32; + else + vamgr = dev->vamgr; + + va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); + size = ALIGN(size, vamgr->va_alignment); + + *va_base_allocated = amdgpu_vamgr_find_va(vamgr, size, + va_base_alignment, va_base_required); + + if (!(flags & AMDGPU_VA_RANGE_32_BIT) && + (*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) { + /* fallback to 32bit address */ + vamgr = dev->vamgr_32; + *va_base_allocated = amdgpu_vamgr_find_va(vamgr, size, va_base_alignment, va_base_required); + } if (*va_base_allocated != AMDGPU_INVALID_VA_ADDRESS) { struct amdgpu_va* va; va = calloc(1, sizeof(struct amdgpu_va)); if(!va){ - amdgpu_vamgr_free_va(dev->vamgr, *va_base_allocated, size); + amdgpu_vamgr_free_va(vamgr, *va_base_allocated, size); return -ENOMEM; } va->dev = dev; va->address = *va_base_allocated; va->size = size; va->range = va_range_type; + va->vamgr = vamgr; *va_range_handle = va; } else { return -EINVAL; @@ -284,7 +300,9 @@ int amdgpu_va_range_free(amdgpu_va_handle va_range_handle) { if(!va_range_handle || !va_range_handle->address) return 0; - amdgpu_vamgr_free_va(va_range_handle->dev->vamgr, va_range_handle->address, + + amdgpu_vamgr_free_va(va_range_handle->vamgr, + va_range_handle->address, va_range_handle->size); free(va_range_handle); return 0; commit 102ab6f0049c2c85857fd19f098bc5b51e2a8a60 Author: Jammy Zhou <Jam...@am...> Date: Mon Aug 17 11:09:07 2015 +0800 amdgpu: improve amdgpu_vamgr_init Make it a generic function independent of the device info. Signed-off-by: Jammy Zhou <Jam...@am...> Reviewed-by: Christian König <chr...@am...> diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index b5d330f..eef8a71 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -46,11 +46,12 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, return -EINVAL; } -static void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, struct amdgpu_device *dev) +static void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, + uint64_t max, uint64_t alignment) { - mgr->va_offset = dev->dev_info.virtual_address_offset; - mgr->va_max = dev->dev_info.virtual_address_max; - mgr->va_alignment = dev->dev_info.virtual_address_alignment; + mgr->va_offset = start; + mgr->va_max = max; + mgr->va_alignment = alignment; list_inithead(&mgr->va_holes); pthread_mutex_init(&mgr->bo_va_mutex, NULL); @@ -73,7 +74,9 @@ amdgpu_vamgr_get_global(struct amdgpu_device *dev) ref = atomic_inc_return(&vamgr.refcount); if (ref == 1) - amdgpu_vamgr_init(&vamgr, dev); + amdgpu_vamgr_init(&vamgr, dev->dev_info.virtual_address_offset, + dev->dev_info.virtual_address_max, + dev->dev_info.virtual_address_alignment); return &vamgr; } |
From: <rob...@ke...> - 2015-08-23 16:35:00
|
freedreno/freedreno_bo.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) New commits: commit 1eba47a76365576447d6346868a074dca24de1bf Author: Varad Gautam <var...@gm...> Date: Fri Aug 21 22:14:35 2015 +0530 freedreno: get bo size for imported dma-buf Signed-off-by: Varad Gautam <var...@gm...> Signed-off-by: Rob Clark <rob...@fr...> diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c index eabffe9..596bfbc 100644 --- a/freedreno/freedreno_bo.c +++ b/freedreno/freedreno_bo.c @@ -237,8 +237,9 @@ fd_bo_from_dmabuf(struct fd_device *dev, int fd) return NULL; } - /* hmm, would be nice if we had a way to figure out the size.. */ - size = 0; + /* lseek() to get bo size */ + size = lseek(fd, 0, SEEK_END); + lseek(fd, 0, SEEK_CUR); bo = fd_bo_from_handle(dev, req.handle, size); bo->fd = fd; commit 425c8e5af7e57d473cb94f1931baa427e58ef2f7 Author: Varad Gautam <var...@gm...> Date: Fri Aug 21 22:14:34 2015 +0530 freedreno: fill bo->fd when importing Signed-off-by: Varad Gautam <var...@gm...> Signed-off-by: Rob Clark <rob...@fr...> diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c index 972ee17..eabffe9 100644 --- a/freedreno/freedreno_bo.c +++ b/freedreno/freedreno_bo.c @@ -230,6 +230,7 @@ fd_bo_from_dmabuf(struct fd_device *dev, int fd) .fd = fd, }; int ret, size; + struct fd_bo *bo; ret = drmIoctl(dev->fd, DRM_IOCTL_PRIME_FD_TO_HANDLE, &req); if (ret) { @@ -239,7 +240,10 @@ fd_bo_from_dmabuf(struct fd_device *dev, int fd) /* hmm, would be nice if we had a way to figure out the size.. */ size = 0; - return fd_bo_from_handle(dev, req.handle, size); + bo = fd_bo_from_handle(dev, req.handle, size); + bo->fd = fd; + + return bo; } struct fd_bo * fd_bo_from_name(struct fd_device *dev, uint32_t name) commit 857c22e5ecf016bcd15508fec6e6d435bf69b58d Author: Varad Gautam <var...@gm...> Date: Fri Aug 21 22:14:33 2015 +0530 freedreno: fix a bo cache segfault with imported bo's Importing a bo whose handle is still in the bo cache crashes during cleanup. Remove bo from cache when importing. Signed-off-by: Varad Gautam <var...@gm...> Signed-off-by: Rob Clark <rob...@fr...> diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c index eec218c..972ee17 100644 --- a/freedreno/freedreno_bo.c +++ b/freedreno/freedreno_bo.c @@ -52,6 +52,9 @@ static struct fd_bo * lookup_bo(void *tbl, uint32_t key) if (!drmHashLookup(tbl, key, (void **)&bo)) { /* found, incr refcnt and return: */ bo = fd_bo_ref(bo); + + /* don't break the bucket if this bo was found in one */ + list_delinit(&bo->list); } return bo; } |
From: <rob...@ke...> - 2015-09-19 16:13:08
|
freedreno/freedreno_bo.c | 26 +++++++++++--------------- freedreno/freedreno_priv.h | 1 - freedreno/kgsl/kgsl_bo.c | 1 - freedreno/msm/msm_bo.c | 1 - freedreno/msm/msm_ringbuffer.c | 4 ++-- 5 files changed, 13 insertions(+), 20 deletions(-) New commits: commit 14968e4cf63d16f5beaea5eb8edba7578bb90501 Author: Rob Clark <rob...@gm...> Date: Fri Sep 4 11:44:33 2015 -0400 freedreno: debug msg cleanup Signed-off-by: Rob Clark <rob...@fr...> diff --git a/freedreno/msm/msm_ringbuffer.c b/freedreno/msm/msm_ringbuffer.c index ee6af0b..becf245 100644 --- a/freedreno/msm/msm_ringbuffer.c +++ b/freedreno/msm/msm_ringbuffer.c @@ -253,7 +253,7 @@ static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start cmd->nr_relocs = (b > a) ? b - a : 0; } - DEBUG_MSG("nr_cmds=%u, nr_bos=%u\n", req.nr_cmds, req.nr_bos); + DEBUG_MSG("nr_cmds=%u, nr_bos=%u", req.nr_cmds, req.nr_bos); ret = drmCommandWriteRead(ring->pipe->dev->fd, DRM_MSM_GEM_SUBMIT, &req, sizeof(req)); @@ -267,7 +267,7 @@ static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start for (i = 0; i < msm_ring->submit.nr_cmds; i++) { struct drm_msm_gem_submit_cmd *cmd = &msm_ring->submit.cmds[i]; struct drm_msm_gem_submit_reloc *relocs = U642VOID(cmd->relocs); - ERROR_MSG(" cmd[%d]: type=%u, submit_idx=%u, submit_offset=%u, size=%u\n", + ERROR_MSG(" cmd[%d]: type=%u, submit_idx=%u, submit_offset=%u, size=%u", i, cmd->type, cmd->submit_idx, cmd->submit_offset, cmd->size); for (j = 0; j < cmd->nr_relocs; j++) { struct drm_msm_gem_submit_reloc *r = &relocs[j]; commit 76a1e97eae3948827ccc100c593d1e96d7a8ce74 Author: Rob Clark <rob...@gm...> Date: Fri Sep 4 11:41:47 2015 -0400 freedreno: drop exported dmabuf fd tracking There is really no reason to keep around the fd, it just consumes an extra file handle. Signed-off-by: Rob Clark <rob...@fr...> diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c index fee32fc..a23c65d 100644 --- a/freedreno/freedreno_bo.c +++ b/freedreno/freedreno_bo.c @@ -298,11 +298,6 @@ void fd_bo_del(struct fd_bo *bo) if (!atomic_dec_and_test(&bo->refcnt)) return; - if (bo->fd >= 0) { - close(bo->fd); - bo->fd = -1; - } - pthread_mutex_lock(&table_lock); if (bo->bo_reuse) { @@ -386,19 +381,18 @@ uint32_t fd_bo_handle(struct fd_bo *bo) int fd_bo_dmabuf(struct fd_bo *bo) { - if (bo->fd < 0) { - int ret, prime_fd; - - ret = drmPrimeHandleToFD(bo->dev->fd, bo->handle, DRM_CLOEXEC, - &prime_fd); - if (ret) { - return ret; - } + int ret, prime_fd; - bo->fd = prime_fd; - bo->bo_reuse = 0; + ret = drmPrimeHandleToFD(bo->dev->fd, bo->handle, DRM_CLOEXEC, + &prime_fd); + if (ret) { + ERROR_MSG("failed to get dmabuf fd: %d", ret); + return ret; } - return dup(bo->fd); + + bo->bo_reuse = 0; + + return prime_fd; } uint32_t fd_bo_size(struct fd_bo *bo) diff --git a/freedreno/freedreno_priv.h b/freedreno/freedreno_priv.h index 4e442e4..53817b1 100644 --- a/freedreno/freedreno_priv.h +++ b/freedreno/freedreno_priv.h @@ -138,7 +138,6 @@ struct fd_bo { uint32_t size; uint32_t handle; uint32_t name; - int fd; /* dmabuf handle */ void *map; atomic_t refcnt; const struct fd_bo_funcs *funcs; diff --git a/freedreno/kgsl/kgsl_bo.c b/freedreno/kgsl/kgsl_bo.c index b8ac102..2b45b5e 100644 --- a/freedreno/kgsl/kgsl_bo.c +++ b/freedreno/kgsl/kgsl_bo.c @@ -168,7 +168,6 @@ drm_private struct fd_bo * kgsl_bo_from_handle(struct fd_device *dev, bo = &kgsl_bo->base; bo->funcs = &funcs; - bo->fd = -1; for (i = 0; i < ARRAY_SIZE(kgsl_bo->list); i++) list_inithead(&kgsl_bo->list[i]); diff --git a/freedreno/msm/msm_bo.c b/freedreno/msm/msm_bo.c index ee668ab..cd05a6c 100644 --- a/freedreno/msm/msm_bo.c +++ b/freedreno/msm/msm_bo.c @@ -136,7 +136,6 @@ drm_private struct fd_bo * msm_bo_from_handle(struct fd_device *dev, bo = &msm_bo->base; bo->funcs = &funcs; - bo->fd = -1; return bo; } commit 691d14c9a85acd806f83664fd58bd87bd32683eb Author: Rob Clark <rob...@gm...> Date: Sat Aug 29 12:49:28 2015 -0400 freedreno: don't reuse exported buffers Signed-off-by: Rob Clark <rob...@fr...> diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c index 1cb6759..fee32fc 100644 --- a/freedreno/freedreno_bo.c +++ b/freedreno/freedreno_bo.c @@ -371,6 +371,7 @@ int fd_bo_get_name(struct fd_bo *bo, uint32_t *name) pthread_mutex_lock(&table_lock); set_name(bo, req.name); pthread_mutex_unlock(&table_lock); + bo->bo_reuse = 0; } *name = bo->name; @@ -395,6 +396,7 @@ int fd_bo_dmabuf(struct fd_bo *bo) } bo->fd = prime_fd; + bo->bo_reuse = 0; } return dup(bo->fd); } |
From: <ag...@ke...> - 2015-11-03 18:56:46
|
amdgpu/amdgpu_bo.c | 11 +++++++++-- amdgpu/amdgpu_vamgr.c | 8 +++++--- 2 files changed, 14 insertions(+), 5 deletions(-) New commits: commit b176372af4c773de188fae67e334e2a83c5706e3 Author: Tom St Denis <tom...@am...> Date: Fri Oct 9 12:46:40 2015 -0400 amdgpu: Cleanly handle ENOMEM on result in amdgpu_bo_list_create() Move the allocation of result prior to the IOCTL so we can cleanly backtrack if the allocation fails. Signed-off-by: Tom St Denis <tom...@am...> Reviewed-by: Alex Deucher <ale...@am...> diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index 348da00..1a5a401 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -591,6 +591,12 @@ int amdgpu_bo_list_create(amdgpu_device_handle dev, if (!list) return -ENOMEM; + *result = malloc(sizeof(struct amdgpu_bo_list)); + if (!*result) { + free(list); + return -ENOMEM; + } + memset(&args, 0, sizeof(args)); args.in.operation = AMDGPU_BO_LIST_OP_CREATE; args.in.bo_number = number_of_resources; @@ -608,10 +614,11 @@ int amdgpu_bo_list_create(amdgpu_device_handle dev, r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST, &args, sizeof(args)); free(list); - if (r) + if (r) { + free(*result); return r; + } - *result = malloc(sizeof(struct amdgpu_bo_list)); (*result)->dev = dev; (*result)->handle = args.out.list_handle; return 0; commit 1a6a8f34a0b17ac03f42bac416e5d289f9c3248f Author: Tom St Denis <tom...@am...> Date: Fri Oct 9 12:07:26 2015 -0400 amdgpu: Fix use-after-free bug in vamgr_deinit This patch fixes a use-after-free bug in the vamgr_deinit function. Signed-off-by: Tom St Denis <tom...@am...> Reviewed-by: Alex Deucher <ale...@am...> diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index 2221da0..8a707cb 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -57,8 +57,8 @@ drm_private void amdgpu_vamgr_init(struct amdgpu_bo_va_mgr *mgr, uint64_t start, drm_private void amdgpu_vamgr_deinit(struct amdgpu_bo_va_mgr *mgr) { - struct amdgpu_bo_va_hole *hole; - LIST_FOR_EACH_ENTRY(hole, &mgr->va_holes, list) { + struct amdgpu_bo_va_hole *hole, *tmp; + LIST_FOR_EACH_ENTRY_SAFE(hole, tmp, &mgr->va_holes, list) { list_del(&hole->list); free(hole); } commit 988f31ecc29770a2648bf5c7d7779f1e500c196c Author: Tom St Denis <tom...@am...> Date: Fri Oct 9 10:36:04 2015 -0400 amdgpu: Unlock mutex if base_required is invalid In the function amdgpu_vamgr_find_va() the function would return without unlocking the mutex if the base_required offset was below the va managers base offset. Signed-off-by: Tom St Denis <tom...@am...> Reviewed-by: Christian König <chr...@am...> diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index 04d2881..2221da0 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -124,8 +124,10 @@ amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr, uint64_t size, } if (base_required) { - if (base_required < mgr->va_offset) + if (base_required < mgr->va_offset) { + pthread_mutex_unlock(&mgr->bo_va_mutex); return AMDGPU_INVALID_VA_ADDRESS; + } offset = mgr->va_offset; waste = base_required - mgr->va_offset; } else { |
From: <an...@ke...> - 2016-02-03 19:32:33
|
Makefile.am | 6 Makefile.sources | 1 configure.ac | 19 ++ include/drm/vc4_drm.h | 279 +++++++++++++++++++++++++++++++++++ tests/util/kms.c | 1 vc4/Makefile.am | 34 ++++ vc4/Makefile.sources | 3 vc4/libdrm_vc4.pc.in | 9 + vc4/vc4_packet.h | 397 ++++++++++++++++++++++++++++++++++++++++++++++++++ vc4/vc4_qpu_defines.h | 274 ++++++++++++++++++++++++++++++++++ 10 files changed, 1023 insertions(+) New commits: commit 3c717f61f885240980bfc4273dbd1fc837edc391 Author: Eric Anholt <er...@an...> Date: Mon Jan 25 10:16:56 2016 -0800 vc4: Add headers and .pc files for VC4 userspace development. The headers were originally written in Mesa, imported to the kernel, and improved upon in vc4-gpu-tools. These come from the v-g-t copies and will replace the Mesa and v-g-t copies, and hopefully be used from new tests in igt, as well. v2: Fix linking against libdrm_intel instead of libdrm. v3: Drop Libs and Cflags since they'll be inherited from libdrm. v4: Switch to Requires.private. I was wrong about standard practice, apparently only Intel was doing plain Requires (sorry to all involved). Signed-off-by: Eric Anholt <er...@an...> diff --git a/Makefile.am b/Makefile.am index ca41508..feecba7 100644 --- a/Makefile.am +++ b/Makefile.am @@ -29,6 +29,7 @@ AM_DISTCHECK_CONFIGURE_FLAGS = \ --enable-radeon \ --enable-amdgpu \ --enable-nouveau \ + --enable-vc4 \ --enable-vmwgfx \ --enable-omap-experimental-api \ --enable-exynos-experimental-api \ @@ -79,6 +80,10 @@ if HAVE_TEGRA TEGRA_SUBDIR = tegra endif +if HAVE_VC4 +VC4_SUBDIR = vc4 +endif + if BUILD_MANPAGES if HAVE_MANPAGES_STYLESHEET MAN_SUBDIR = man @@ -96,6 +101,7 @@ SUBDIRS = \ $(EXYNOS_SUBDIR) \ $(FREEDRENO_SUBDIR) \ $(TEGRA_SUBDIR) \ + $(VC4_SUBDIR) \ tests \ $(MAN_SUBDIR) diff --git a/configure.ac b/configure.ac index 4635d18..4eeebfb 100644 --- a/configure.ac +++ b/configure.ac @@ -126,6 +126,11 @@ AC_ARG_ENABLE(tegra-experimental-api, [Enable support for Tegra's experimental API (default: disabled)]), [TEGRA=$enableval], [TEGRA=no]) +AC_ARG_ENABLE(vc4, + AS_HELP_STRING([--disable-vc4], + [Enable support for vc4's API (default: auto, enabled on arm)]), + [VC4=$enableval], [VC4=auto]) + AC_ARG_ENABLE(install-test-programs, AS_HELP_STRING([--enable-install-test-programs], [Install test programs (default: no)]), @@ -290,6 +295,12 @@ else *) FREEDRENO=no ;; esac fi + if test "x$VC4" = xauto; then + case $host_cpu in + arm*|aarch64) VC4=yes ;; + *) VC4=no ;; + esac + fi fi if test "x$INTEL" != "xno"; then @@ -396,6 +407,11 @@ if test "x$TEGRA" = xyes; then AC_DEFINE(HAVE_TEGRA, 1, [Have Tegra support]) fi +AM_CONDITIONAL(HAVE_VC4, [test "x$VC4" = xyes]) +if test "x$VC4" = xyes; then + AC_DEFINE(HAVE_VC4, 1, [Have VC4 support]) +fi + AM_CONDITIONAL(HAVE_INSTALL_TESTS, [test "x$INSTALL_TESTS" = xyes]) if test "x$INSTALL_TESTS" = xyes; then AC_DEFINE(HAVE_INSTALL_TESTS, 1, [Install test programs]) @@ -505,6 +521,8 @@ AC_CONFIG_FILES([ freedreno/libdrm_freedreno.pc tegra/Makefile tegra/libdrm_tegra.pc + vc4/Makefile + vc4/libdrm_vc4.pc tests/Makefile tests/modeprint/Makefile tests/modetest/Makefile @@ -535,4 +553,5 @@ echo " OMAP API $OMAP" echo " EXYNOS API $EXYNOS" echo " Freedreno API $FREEDRENO (kgsl: $FREEDRENO_KGSL)" echo " Tegra API $TEGRA" +echo " VC4 API $VC4" echo "" diff --git a/vc4/Makefile.am b/vc4/Makefile.am new file mode 100644 index 0000000..7e486b4 --- /dev/null +++ b/vc4/Makefile.am @@ -0,0 +1,34 @@ +# Copyright © 2016 Broadcom +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the "Software"), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. + +include Makefile.sources + +AM_CFLAGS = \ + $(WARN_CFLAGS) \ + -I$(top_srcdir) \ + $(PTHREADSTUBS_CFLAGS) \ + $(VALGRIND_CFLAGS) \ + -I$(top_srcdir)/include/drm + +libdrm_vc4includedir = ${includedir}/libdrm +libdrm_vc4include_HEADERS = $(LIBDRM_VC4_H_FILES) + +pkgconfig_DATA = libdrm_vc4.pc diff --git a/vc4/Makefile.sources b/vc4/Makefile.sources new file mode 100644 index 0000000..8bf97ff --- /dev/null +++ b/vc4/Makefile.sources @@ -0,0 +1,3 @@ +LIBDRM_VC4_H_FILES := \ + vc4_packet.h \ + vc4_qpu_defines.h diff --git a/vc4/libdrm_vc4.pc.in b/vc4/libdrm_vc4.pc.in new file mode 100644 index 0000000..a92678e --- /dev/null +++ b/vc4/libdrm_vc4.pc.in @@ -0,0 +1,9 @@ +prefix=@prefix@ +exec_prefix=@exec_prefix@ +libdir=@libdir@ +includedir=@includedir@ + +Name: libdrm_vc4 +Description: Userspace interface to vc4 kernel DRM services +Version: @PACKAGE_VERSION@ +Requires.private: libdrm diff --git a/vc4/vc4_packet.h b/vc4/vc4_packet.h new file mode 100644 index 0000000..e18e0bd --- /dev/null +++ b/vc4/vc4_packet.h @@ -0,0 +1,397 @@ +/* + * Copyright © 2014 Broadcom + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef VC4_PACKET_H +#define VC4_PACKET_H + +enum vc4_packet { + VC4_PACKET_HALT = 0, + VC4_PACKET_NOP = 1, + + VC4_PACKET_FLUSH = 4, + VC4_PACKET_FLUSH_ALL = 5, + VC4_PACKET_START_TILE_BINNING = 6, + VC4_PACKET_INCREMENT_SEMAPHORE = 7, + VC4_PACKET_WAIT_ON_SEMAPHORE = 8, + + VC4_PACKET_BRANCH = 16, + VC4_PACKET_BRANCH_TO_SUB_LIST = 17, + VC4_PACKET_RETURN_FROM_SUB_LIST = 18, + + VC4_PACKET_STORE_MS_TILE_BUFFER = 24, + VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF = 25, + VC4_PACKET_STORE_FULL_RES_TILE_BUFFER = 26, + VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER = 27, + VC4_PACKET_STORE_TILE_BUFFER_GENERAL = 28, + VC4_PACKET_LOAD_TILE_BUFFER_GENERAL = 29, + + VC4_PACKET_GL_INDEXED_PRIMITIVE = 32, + VC4_PACKET_GL_ARRAY_PRIMITIVE = 33, + + VC4_PACKET_COMPRESSED_PRIMITIVE = 48, + VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE = 49, + + VC4_PACKET_PRIMITIVE_LIST_FORMAT = 56, + + VC4_PACKET_GL_SHADER_STATE = 64, + VC4_PACKET_NV_SHADER_STATE = 65, + VC4_PACKET_VG_SHADER_STATE = 66, + + VC4_PACKET_CONFIGURATION_BITS = 96, + VC4_PACKET_FLAT_SHADE_FLAGS = 97, + VC4_PACKET_POINT_SIZE = 98, + VC4_PACKET_LINE_WIDTH = 99, + VC4_PACKET_RHT_X_BOUNDARY = 100, + VC4_PACKET_DEPTH_OFFSET = 101, + VC4_PACKET_CLIP_WINDOW = 102, + VC4_PACKET_VIEWPORT_OFFSET = 103, + VC4_PACKET_Z_CLIPPING = 104, + VC4_PACKET_CLIPPER_XY_SCALING = 105, + VC4_PACKET_CLIPPER_Z_SCALING = 106, + + VC4_PACKET_TILE_BINNING_MODE_CONFIG = 112, + VC4_PACKET_TILE_RENDERING_MODE_CONFIG = 113, + VC4_PACKET_CLEAR_COLORS = 114, + VC4_PACKET_TILE_COORDINATES = 115, + + /* Not an actual hardware packet -- this is what we use to put + * references to GEM bos in the command stream, since we need the u32 + * int the actual address packet in order to store the offset from the + * start of the BO. + */ + VC4_PACKET_GEM_HANDLES = 254, +} __attribute__ ((__packed__)); + +#define VC4_PACKET_HALT_SIZE 1 +#define VC4_PACKET_NOP_SIZE 1 +#define VC4_PACKET_FLUSH_SIZE 1 +#define VC4_PACKET_FLUSH_ALL_SIZE 1 +#define VC4_PACKET_START_TILE_BINNING_SIZE 1 +#define VC4_PACKET_INCREMENT_SEMAPHORE_SIZE 1 +#define VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE 1 +#define VC4_PACKET_BRANCH_SIZE 5 +#define VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE 5 +#define VC4_PACKET_RETURN_FROM_SUB_LIST_SIZE 1 +#define VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE 1 +#define VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF_SIZE 1 +#define VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE 5 +#define VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE 5 +#define VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE 7 +#define VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE 7 +#define VC4_PACKET_GL_INDEXED_PRIMITIVE_SIZE 14 +#define VC4_PACKET_GL_ARRAY_PRIMITIVE_SIZE 10 +#define VC4_PACKET_COMPRESSED_PRIMITIVE_SIZE 1 +#define VC4_PACKET_CLIPPED_COMPRESSED_PRIMITIVE_SIZE 1 +#define VC4_PACKET_PRIMITIVE_LIST_FORMAT_SIZE 2 +#define VC4_PACKET_GL_SHADER_STATE_SIZE 5 +#define VC4_PACKET_NV_SHADER_STATE_SIZE 5 +#define VC4_PACKET_VG_SHADER_STATE_SIZE 5 +#define VC4_PACKET_CONFIGURATION_BITS_SIZE 4 +#define VC4_PACKET_FLAT_SHADE_FLAGS_SIZE 5 +#define VC4_PACKET_POINT_SIZE_SIZE 5 +#define VC4_PACKET_LINE_WIDTH_SIZE 5 +#define VC4_PACKET_RHT_X_BOUNDARY_SIZE 3 +#define VC4_PACKET_DEPTH_OFFSET_SIZE 5 +#define VC4_PACKET_CLIP_WINDOW_SIZE 9 +#define VC4_PACKET_VIEWPORT_OFFSET_SIZE 5 +#define VC4_PACKET_Z_CLIPPING_SIZE 9 +#define VC4_PACKET_CLIPPER_XY_SCALING_SIZE 9 +#define VC4_PACKET_CLIPPER_Z_SCALING_SIZE 9 +#define VC4_PACKET_TILE_BINNING_MODE_CONFIG_SIZE 16 +#define VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE 11 +#define VC4_PACKET_CLEAR_COLORS_SIZE 14 +#define VC4_PACKET_TILE_COORDINATES_SIZE 3 +#define VC4_PACKET_GEM_HANDLES_SIZE 9 + +#define VC4_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low)) +/* Using the GNU statement expression extension */ +#define VC4_SET_FIELD(value, field) \ + ({ \ + uint32_t fieldval = (value) << field ## _SHIFT; \ + assert((fieldval & ~ field ## _MASK) == 0); \ + fieldval & field ## _MASK; \ + }) + +#define VC4_GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) + +/** @{ + * Bits used by packets like VC4_PACKET_STORE_TILE_BUFFER_GENERAL and + * VC4_PACKET_TILE_RENDERING_MODE_CONFIG. +*/ +#define VC4_TILING_FORMAT_LINEAR 0 +#define VC4_TILING_FORMAT_T 1 +#define VC4_TILING_FORMAT_LT 2 +/** @} */ + +/** @{ + * + * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and + * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER. + */ +#define VC4_LOADSTORE_FULL_RES_EOF (1 << 3) +#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL (1 << 2) +#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS (1 << 1) +#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR (1 << 0) + +/** @{ + * + * byte 2 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and + * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL (low bits of the address) + */ + +#define VC4_LOADSTORE_TILE_BUFFER_EOF (1 << 3) +#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_VG_MASK (1 << 2) +#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_ZS (1 << 1) +#define VC4_LOADSTORE_TILE_BUFFER_DISABLE_FULL_COLOR (1 << 0) + +/** @} */ + +/** @{ + * + * byte 0-1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and + * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL + */ +#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 15) +#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR (1 << 14) +#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR (1 << 13) +#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP (1 << 12) + +#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK VC4_MASK(9, 8) +#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT 8 +#define VC4_LOADSTORE_TILE_BUFFER_RGBA8888 0 +#define VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER 1 +#define VC4_LOADSTORE_TILE_BUFFER_BGR565 2 +/** @} */ + +/** @{ + * + * byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and + * VC4_PACKET_LOAD_TILE_BUFFER_GENERAL + */ +#define VC4_STORE_TILE_BUFFER_MODE_MASK VC4_MASK(7, 6) +#define VC4_STORE_TILE_BUFFER_MODE_SHIFT 6 +#define VC4_STORE_TILE_BUFFER_MODE_SAMPLE0 (0 << 6) +#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X4 (1 << 6) +#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X16 (2 << 6) + +/** The values of the field are VC4_TILING_FORMAT_* */ +#define VC4_LOADSTORE_TILE_BUFFER_TILING_MASK VC4_MASK(5, 4) +#define VC4_LOADSTORE_TILE_BUFFER_TILING_SHIFT 4 + +#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK VC4_MASK(2, 0) +#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_SHIFT 0 +#define VC4_LOADSTORE_TILE_BUFFER_NONE 0 +#define VC4_LOADSTORE_TILE_BUFFER_COLOR 1 +#define VC4_LOADSTORE_TILE_BUFFER_ZS 2 +#define VC4_LOADSTORE_TILE_BUFFER_Z 3 +#define VC4_LOADSTORE_TILE_BUFFER_VG_MASK 4 +#define VC4_LOADSTORE_TILE_BUFFER_FULL 5 +/** @} */ + +#define VC4_INDEX_BUFFER_U8 (0 << 4) +#define VC4_INDEX_BUFFER_U16 (1 << 4) + +/* This flag is only present in NV shader state. */ +#define VC4_SHADER_FLAG_SHADED_CLIP_COORDS (1 << 3) +#define VC4_SHADER_FLAG_ENABLE_CLIPPING (1 << 2) +#define VC4_SHADER_FLAG_VS_POINT_SIZE (1 << 1) +#define VC4_SHADER_FLAG_FS_SINGLE_THREAD (1 << 0) + +/** @{ byte 2 of config bits. */ +#define VC4_CONFIG_BITS_EARLY_Z_UPDATE (1 << 1) +#define VC4_CONFIG_BITS_EARLY_Z (1 << 0) +/** @} */ + +/** @{ byte 1 of config bits. */ +#define VC4_CONFIG_BITS_Z_UPDATE (1 << 7) +/** same values in this 3-bit field as PIPE_FUNC_* */ +#define VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT 4 +#define VC4_CONFIG_BITS_COVERAGE_READ_LEAVE (1 << 3) + +#define VC4_CONFIG_BITS_COVERAGE_UPDATE_NONZERO (0 << 1) +#define VC4_CONFIG_BITS_COVERAGE_UPDATE_ODD (1 << 1) +#define VC4_CONFIG_BITS_COVERAGE_UPDATE_OR (2 << 1) +#define VC4_CONFIG_BITS_COVERAGE_UPDATE_ZERO (3 << 1) + +#define VC4_CONFIG_BITS_COVERAGE_PIPE_SELECT (1 << 0) +/** @} */ + +/** @{ byte 0 of config bits. */ +#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_NONE (0 << 6) +#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X (1 << 6) +#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_16X (2 << 6) +#define VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_MASK (3 << 6) + +#define VC4_CONFIG_BITS_AA_POINTS_AND_LINES (1 << 4) +#define VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET (1 << 3) +#define VC4_CONFIG_BITS_CW_PRIMITIVES (1 << 2) +#define VC4_CONFIG_BITS_ENABLE_PRIM_BACK (1 << 1) +#define VC4_CONFIG_BITS_ENABLE_PRIM_FRONT (1 << 0) +/** @} */ + +/** @{ bits in the last u8 of VC4_PACKET_TILE_BINNING_MODE_CONFIG */ +#define VC4_BIN_CONFIG_DB_NON_MS (1 << 7) + +#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_MASK VC4_MASK(6, 5) +#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_SHIFT 5 +#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_32 0 +#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_64 1 +#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_128 2 +#define VC4_BIN_CONFIG_ALLOC_BLOCK_SIZE_256 3 + +#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_MASK VC4_MASK(4, 3) +#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_SHIFT 3 +#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_32 0 +#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_64 1 +#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_128 2 +#define VC4_BIN_CONFIG_ALLOC_INIT_BLOCK_SIZE_256 3 + +#define VC4_BIN_CONFIG_AUTO_INIT_TSDA (1 << 2) +#define VC4_BIN_CONFIG_TILE_BUFFER_64BIT (1 << 1) +#define VC4_BIN_CONFIG_MS_MODE_4X (1 << 0) +/** @} */ + +/** @{ bits in the last u16 of VC4_PACKET_TILE_RENDERING_MODE_CONFIG */ +#define VC4_RENDER_CONFIG_DB_NON_MS (1 << 12) +#define VC4_RENDER_CONFIG_EARLY_Z_COVERAGE_DISABLE (1 << 11) +#define VC4_RENDER_CONFIG_EARLY_Z_DIRECTION_G (1 << 10) +#define VC4_RENDER_CONFIG_COVERAGE_MODE (1 << 9) +#define VC4_RENDER_CONFIG_ENABLE_VG_MASK (1 << 8) + +/** The values of the field are VC4_TILING_FORMAT_* */ +#define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK VC4_MASK(7, 6) +#define VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT 6 + +#define VC4_RENDER_CONFIG_DECIMATE_MODE_1X (0 << 4) +#define VC4_RENDER_CONFIG_DECIMATE_MODE_4X (1 << 4) +#define VC4_RENDER_CONFIG_DECIMATE_MODE_16X (2 << 4) +#define VC4_RENDER_CONFIG_DECIMATE_MODE_MASK (3 << 4) + +#define VC4_RENDER_CONFIG_FORMAT_MASK VC4_MASK(3, 2) +#define VC4_RENDER_CONFIG_FORMAT_SHIFT 2 +#define VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED 0 +#define VC4_RENDER_CONFIG_FORMAT_RGBA8888 1 +#define VC4_RENDER_CONFIG_FORMAT_BGR565 2 + +#define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT (1 << 1) +#define VC4_RENDER_CONFIG_MS_MODE_4X (1 << 0) + +#define VC4_PRIMITIVE_LIST_FORMAT_16_INDEX (1 << 4) +#define VC4_PRIMITIVE_LIST_FORMAT_32_XY (3 << 4) +#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_POINTS (0 << 0) +#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_LINES (1 << 0) +#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_TRIANGLES (2 << 0) +#define VC4_PRIMITIVE_LIST_FORMAT_TYPE_RHT (3 << 0) + +enum vc4_texture_data_type { + VC4_TEXTURE_TYPE_RGBA8888 = 0, + VC4_TEXTURE_TYPE_RGBX8888 = 1, + VC4_TEXTURE_TYPE_RGBA4444 = 2, + VC4_TEXTURE_TYPE_RGBA5551 = 3, + VC4_TEXTURE_TYPE_RGB565 = 4, + VC4_TEXTURE_TYPE_LUMINANCE = 5, + VC4_TEXTURE_TYPE_ALPHA = 6, + VC4_TEXTURE_TYPE_LUMALPHA = 7, + VC4_TEXTURE_TYPE_ETC1 = 8, + VC4_TEXTURE_TYPE_S16F = 9, + VC4_TEXTURE_TYPE_S8 = 10, + VC4_TEXTURE_TYPE_S16 = 11, + VC4_TEXTURE_TYPE_BW1 = 12, + VC4_TEXTURE_TYPE_A4 = 13, + VC4_TEXTURE_TYPE_A1 = 14, + VC4_TEXTURE_TYPE_RGBA64 = 15, + VC4_TEXTURE_TYPE_RGBA32R = 16, + VC4_TEXTURE_TYPE_YUV422R = 17, +}; + +#define VC4_TEX_P0_OFFSET_MASK VC4_MASK(31, 12) +#define VC4_TEX_P0_OFFSET_SHIFT 12 +#define VC4_TEX_P0_CSWIZ_MASK VC4_MASK(11, 10) +#define VC4_TEX_P0_CSWIZ_SHIFT 10 +#define VC4_TEX_P0_CMMODE_MASK VC4_MASK(9, 9) +#define VC4_TEX_P0_CMMODE_SHIFT 9 +#define VC4_TEX_P0_FLIPY_MASK VC4_MASK(8, 8) +#define VC4_TEX_P0_FLIPY_SHIFT 8 +#define VC4_TEX_P0_TYPE_MASK VC4_MASK(7, 4) +#define VC4_TEX_P0_TYPE_SHIFT 4 +#define VC4_TEX_P0_MIPLVLS_MASK VC4_MASK(3, 0) +#define VC4_TEX_P0_MIPLVLS_SHIFT 0 + +#define VC4_TEX_P1_TYPE4_MASK VC4_MASK(31, 31) +#define VC4_TEX_P1_TYPE4_SHIFT 31 +#define VC4_TEX_P1_HEIGHT_MASK VC4_MASK(30, 20) +#define VC4_TEX_P1_HEIGHT_SHIFT 20 +#define VC4_TEX_P1_ETCFLIP_MASK VC4_MASK(19, 19) +#define VC4_TEX_P1_ETCFLIP_SHIFT 19 +#define VC4_TEX_P1_WIDTH_MASK VC4_MASK(18, 8) +#define VC4_TEX_P1_WIDTH_SHIFT 8 + +#define VC4_TEX_P1_MAGFILT_MASK VC4_MASK(7, 7) +#define VC4_TEX_P1_MAGFILT_SHIFT 7 +# define VC4_TEX_P1_MAGFILT_LINEAR 0 +# define VC4_TEX_P1_MAGFILT_NEAREST 1 + +#define VC4_TEX_P1_MINFILT_MASK VC4_MASK(6, 4) +#define VC4_TEX_P1_MINFILT_SHIFT 4 +# define VC4_TEX_P1_MINFILT_LINEAR 0 +# define VC4_TEX_P1_MINFILT_NEAREST 1 +# define VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR 2 +# define VC4_TEX_P1_MINFILT_NEAR_MIP_LIN 3 +# define VC4_TEX_P1_MINFILT_LIN_MIP_NEAR 4 +# define VC4_TEX_P1_MINFILT_LIN_MIP_LIN 5 + +#define VC4_TEX_P1_WRAP_T_MASK VC4_MASK(3, 2) +#define VC4_TEX_P1_WRAP_T_SHIFT 2 +#define VC4_TEX_P1_WRAP_S_MASK VC4_MASK(1, 0) +#define VC4_TEX_P1_WRAP_S_SHIFT 0 +# define VC4_TEX_P1_WRAP_REPEAT 0 +# define VC4_TEX_P1_WRAP_CLAMP 1 +# define VC4_TEX_P1_WRAP_MIRROR 2 +# define VC4_TEX_P1_WRAP_BORDER 3 + +#define VC4_TEX_P2_PTYPE_MASK VC4_MASK(31, 30) +#define VC4_TEX_P2_PTYPE_SHIFT 30 +# define VC4_TEX_P2_PTYPE_IGNORED 0 +# define VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE 1 +# define VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS 2 +# define VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS 3 + +/* VC4_TEX_P2_PTYPE_CUBE_MAP_STRIDE bits */ +#define VC4_TEX_P2_CMST_MASK VC4_MASK(29, 12) +#define VC4_TEX_P2_CMST_SHIFT 12 +#define VC4_TEX_P2_BSLOD_MASK VC4_MASK(0, 0) +#define VC4_TEX_P2_BSLOD_SHIFT 0 + +/* VC4_TEX_P2_PTYPE_CHILD_IMAGE_DIMENSIONS */ +#define VC4_TEX_P2_CHEIGHT_MASK VC4_MASK(22, 12) +#define VC4_TEX_P2_CHEIGHT_SHIFT 12 +#define VC4_TEX_P2_CWIDTH_MASK VC4_MASK(10, 0) +#define VC4_TEX_P2_CWIDTH_SHIFT 0 + +/* VC4_TEX_P2_PTYPE_CHILD_IMAGE_OFFSETS */ +#define VC4_TEX_P2_CYOFF_MASK VC4_MASK(22, 12) +#define VC4_TEX_P2_CYOFF_SHIFT 12 +#define VC4_TEX_P2_CXOFF_MASK VC4_MASK(10, 0) +#define VC4_TEX_P2_CXOFF_SHIFT 0 + +#endif /* VC4_PACKET_H */ diff --git a/vc4/vc4_qpu_defines.h b/vc4/vc4_qpu_defines.h new file mode 100644 index 0000000..26fcf50 --- /dev/null +++ b/vc4/vc4_qpu_defines.h @@ -0,0 +1,274 @@ +/* + * Copyright © 2014 Broadcom + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef VC4_QPU_DEFINES_H +#define VC4_QPU_DEFINES_H + +enum qpu_op_add { + QPU_A_NOP, + QPU_A_FADD, + QPU_A_FSUB, + QPU_A_FMIN, + QPU_A_FMAX, + QPU_A_FMINABS, + QPU_A_FMAXABS, + QPU_A_FTOI, + QPU_A_ITOF, + QPU_A_ADD = 12, + QPU_A_SUB, + QPU_A_SHR, + QPU_A_ASR, + QPU_A_ROR, + QPU_A_SHL, + QPU_A_MIN, + QPU_A_MAX, + QPU_A_AND, + QPU_A_OR, + QPU_A_XOR, + QPU_A_NOT, + QPU_A_CLZ, + QPU_A_V8ADDS = 30, + QPU_A_V8SUBS = 31, +}; + +enum qpu_op_mul { + QPU_M_NOP, + QPU_M_FMUL, + QPU_M_MUL24, + QPU_M_V8MULD, + QPU_M_V8MIN, + QPU_M_V8MAX, + QPU_M_V8ADDS, + QPU_M_V8SUBS, +}; + +enum qpu_raddr { + QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */ + /* 0-31 are the plain regfile a or b fields */ + QPU_R_UNIF = 32, + QPU_R_VARY = 35, + QPU_R_ELEM_QPU = 38, + QPU_R_NOP, + QPU_R_XY_PIXEL_COORD = 41, + QPU_R_MS_REV_FLAGS = 42, + QPU_R_VPM = 48, + QPU_R_VPM_LD_BUSY, + QPU_R_VPM_LD_WAIT, + QPU_R_MUTEX_ACQUIRE, +}; + +enum qpu_waddr { + /* 0-31 are the plain regfile a or b fields */ + QPU_W_ACC0 = 32, /* aka r0 */ + QPU_W_ACC1, + QPU_W_ACC2, + QPU_W_ACC3, + QPU_W_TMU_NOSWAP, + QPU_W_ACC5, + QPU_W_HOST_INT, + QPU_W_NOP, + QPU_W_UNIFORMS_ADDRESS, + QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */ + QPU_W_MS_FLAGS = 42, + QPU_W_REV_FLAG = 42, + QPU_W_TLB_STENCIL_SETUP = 43, + QPU_W_TLB_Z, + QPU_W_TLB_COLOR_MS, + QPU_W_TLB_COLOR_ALL, + QPU_W_TLB_ALPHA_MASK, + QPU_W_VPM, + QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */ + QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */ + QPU_W_MUTEX_RELEASE, + QPU_W_SFU_RECIP, + QPU_W_SFU_RECIPSQRT, + QPU_W_SFU_EXP, + QPU_W_SFU_LOG, + QPU_W_TMU0_S, + QPU_W_TMU0_T, + QPU_W_TMU0_R, + QPU_W_TMU0_B, + QPU_W_TMU1_S, + QPU_W_TMU1_T, + QPU_W_TMU1_R, + QPU_W_TMU1_B, +}; + +enum qpu_sig_bits { + QPU_SIG_SW_BREAKPOINT, + QPU_SIG_NONE, + QPU_SIG_THREAD_SWITCH, + QPU_SIG_PROG_END, + QPU_SIG_WAIT_FOR_SCOREBOARD, + QPU_SIG_SCOREBOARD_UNLOCK, + QPU_SIG_LAST_THREAD_SWITCH, + QPU_SIG_COVERAGE_LOAD, + QPU_SIG_COLOR_LOAD, + QPU_SIG_COLOR_LOAD_END, + QPU_SIG_LOAD_TMU0, + QPU_SIG_LOAD_TMU1, + QPU_SIG_ALPHA_MASK_LOAD, + QPU_SIG_SMALL_IMM, + QPU_SIG_LOAD_IMM, + QPU_SIG_BRANCH +}; + +enum qpu_mux { + /* hardware mux values */ + QPU_MUX_R0, + QPU_MUX_R1, + QPU_MUX_R2, + QPU_MUX_R3, + QPU_MUX_R4, + QPU_MUX_R5, + QPU_MUX_A, + QPU_MUX_B, + + /** + * Non-hardware mux value, stores a small immediate field to be + * programmed into raddr_b in the qpu_reg.index. + */ + QPU_MUX_SMALL_IMM, +}; + +enum qpu_cond { + QPU_COND_NEVER, + QPU_COND_ALWAYS, + QPU_COND_ZS, + QPU_COND_ZC, + QPU_COND_NS, + QPU_COND_NC, + QPU_COND_CS, + QPU_COND_CC, +}; + +enum qpu_pack_mul { + QPU_PACK_MUL_NOP, + QPU_PACK_MUL_8888 = 3, /* replicated to each 8 bits of the 32-bit dst. */ + QPU_PACK_MUL_8A, + QPU_PACK_MUL_8B, + QPU_PACK_MUL_8C, + QPU_PACK_MUL_8D, +}; + +enum qpu_pack_a { + QPU_PACK_A_NOP, + /* convert to 16 bit float if float input, or to int16. */ + QPU_PACK_A_16A, + QPU_PACK_A_16B, + /* replicated to each 8 bits of the 32-bit dst. */ + QPU_PACK_A_8888, + /* Convert to 8-bit unsigned int. */ + QPU_PACK_A_8A, + QPU_PACK_A_8B, + QPU_PACK_A_8C, + QPU_PACK_A_8D, + + /* Saturating variants of the previous instructions. */ + QPU_PACK_A_32_SAT, /* int-only */ + QPU_PACK_A_16A_SAT, /* int or float */ + QPU_PACK_A_16B_SAT, + QPU_PACK_A_8888_SAT, + QPU_PACK_A_8A_SAT, + QPU_PACK_A_8B_SAT, + QPU_PACK_A_8C_SAT, + QPU_PACK_A_8D_SAT, +}; + +enum qpu_unpack { + QPU_UNPACK_NOP, + QPU_UNPACK_16A, + QPU_UNPACK_16B, + QPU_UNPACK_8D_REP, + QPU_UNPACK_8A, + QPU_UNPACK_8B, + QPU_UNPACK_8C, + QPU_UNPACK_8D, +}; + +#define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low)) +/* Using the GNU statement expression extension */ +#define QPU_SET_FIELD(value, field) \ + ({ \ + uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \ + assert((fieldval & ~ field ## _MASK) == 0); \ + fieldval & field ## _MASK; \ + }) + +#define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) + +#define QPU_UPDATE_FIELD(inst, value, field) \ + (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field)) + +#define QPU_SIG_SHIFT 60 +#define QPU_SIG_MASK QPU_MASK(63, 60) + +#define QPU_UNPACK_SHIFT 57 +#define QPU_UNPACK_MASK QPU_MASK(59, 57) + +/** + * If set, the pack field means PACK_MUL or R4 packing, instead of normal + * regfile a packing. + */ +#define QPU_PM ((uint64_t)1 << 56) + +#define QPU_PACK_SHIFT 52 +#define QPU_PACK_MASK QPU_MASK(55, 52) + +#define QPU_COND_ADD_SHIFT 49 +#define QPU_COND_ADD_MASK QPU_MASK(51, 49) +#define QPU_COND_MUL_SHIFT 46 +#define QPU_COND_MUL_MASK QPU_MASK(48, 46) + +#define QPU_SF ((uint64_t)1 << 45) + +#define QPU_WADDR_ADD_SHIFT 38 +#define QPU_WADDR_ADD_MASK QPU_MASK(43, 38) +#define QPU_WADDR_MUL_SHIFT 32 +#define QPU_WADDR_MUL_MASK QPU_MASK(37, 32) + +#define QPU_OP_MUL_SHIFT 29 +#define QPU_OP_MUL_MASK QPU_MASK(31, 29) + +#define QPU_RADDR_A_SHIFT 18 +#define QPU_RADDR_A_MASK QPU_MASK(23, 18) +#define QPU_RADDR_B_SHIFT 12 +#define QPU_RADDR_B_MASK QPU_MASK(17, 12) +#define QPU_SMALL_IMM_SHIFT 12 +#define QPU_SMALL_IMM_MASK QPU_MASK(17, 12) + +#define QPU_ADD_A_SHIFT 9 +#define QPU_ADD_A_MASK QPU_MASK(11, 9) +#define QPU_ADD_B_SHIFT 6 +#define QPU_ADD_B_MASK QPU_MASK(8, 6) +#define QPU_MUL_A_SHIFT 3 +#define QPU_MUL_A_MASK QPU_MASK(5, 3) +#define QPU_MUL_B_SHIFT 0 +#define QPU_MUL_B_MASK QPU_MASK(2, 0) + +#define QPU_WS ((uint64_t)1 << 44) + +#define QPU_OP_ADD_SHIFT 24 +#define QPU_OP_ADD_MASK QPU_MASK(28, 24) + +#endif /* VC4_QPU_DEFINES_H */ commit 0ad32e7ff48e106d654acca79445389651ed6909 Author: Eric Anholt <er...@an...> Date: Fri Jan 22 16:37:25 2016 -0800 util: Add support for vc4. This lets allows using modetest for overlay plane testing. Signed-off-by: Eric Anholt <er...@an...> diff --git a/tests/util/kms.c b/tests/util/kms.c index dcd5a8e..ce8aaab 100644 --- a/tests/util/kms.c +++ b/tests/util/kms.c @@ -140,6 +140,7 @@ static const char * const modules[] = { "rockchip", "atmel-hlcdc", "fsl-dcu-drm", + "vc4", }; int util_open(const char *device, const char *module) commit eeb23de23bf2c0aeff4e36b0513ea13ac09c0438 Author: Eric Anholt <er...@an...> Date: Fri Jan 22 16:34:14 2016 -0800 vc4: Add the DRM header file. I'll build some libdrm C code soon, but for now this lets libdrm users use vc4 ioctls. Produced from headers_install of 1df59b8497f47495e873c23abd6d3d290c730505 (drm-next) in the kernel. Signed-off-by: Eric Anholt <er...@an...> diff --git a/Makefile.sources b/Makefile.sources index a77f48d..1a1f0fe 100644 --- a/Makefile.sources +++ b/Makefile.sources @@ -32,6 +32,7 @@ LIBDRM_INCLUDE_H_FILES := \ include/drm/savage_drm.h \ include/drm/sis_drm.h \ include/drm/tegra_drm.h \ + include/drm/vc4_drm.h \ include/drm/via_drm.h LIBDRM_INCLUDE_VMWGFX_H_FILES := \ diff --git a/include/drm/vc4_drm.h b/include/drm/vc4_drm.h new file mode 100644 index 0000000..da3caa0 --- /dev/null +++ b/include/drm/vc4_drm.h @@ -0,0 +1,279 @@ +/* + * Copyright © 2014-2015 Broadcom + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef _VC4_DRM_H_ +#define _VC4_DRM_H_ + +#include "drm.h" + +#define DRM_VC4_SUBMIT_CL 0x00 +#define DRM_VC4_WAIT_SEQNO 0x01 +#define DRM_VC4_WAIT_BO 0x02 +#define DRM_VC4_CREATE_BO 0x03 +#define DRM_VC4_MMAP_BO 0x04 +#define DRM_VC4_CREATE_SHADER_BO 0x05 +#define DRM_VC4_GET_HANG_STATE 0x06 + +#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) +#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) +#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) +#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) +#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) +#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) +#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) + +struct drm_vc4_submit_rcl_surface { + __u32 hindex; /* Handle index, or ~0 if not present. */ + __u32 offset; /* Offset to start of buffer. */ + /* + * Bits for either render config (color_write) or load/store packet. + * Bits should all be 0 for MSAA load/stores. + */ + __u16 bits; + +#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) + __u16 flags; +}; + +/** + * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D + * engine. + * + * Drivers typically use GPU BOs to store batchbuffers / command lists and + * their associated state. However, because the VC4 lacks an MMU, we have to + * do validation of memory accesses by the GPU commands. If we were to store + * our commands in BOs, we'd need to do uncached readback from them to do the + * validation process, which is too expensive. Instead, userspace accumulates + * commands and associated state in plain memory, then the kernel copies the + * data to its own address space, and then validates and stores it in a GPU + * BO. + */ +struct drm_vc4_submit_cl { + /* Pointer to the binner command list. + * + * This is the first set of commands executed, which runs the + * coordinate shader to determine where primitives land on the screen, + * then writes out the state updates and draw calls necessary per tile + * to the tile allocation BO. + */ + __u64 bin_cl; + + /* Pointer to the shader records. + * + * Shader records are the structures read by the hardware that contain + * pointers to uniforms, shaders, and vertex attributes. The + * reference to the shader record has enough information to determine + * how many pointers are necessary (fixed number for shaders/uniforms, + * and an attribute count), so those BO indices into bo_handles are + * just stored as __u32s before each shader record passed in. + */ + __u64 shader_rec; + + /* Pointer to uniform data and texture handles for the textures + * referenced by the shader. + * + * For each shader state record, there is a set of uniform data in the + * order referenced by the record (FS, VS, then CS). Each set of + * uniform data has a __u32 index into bo_handles per texture + * sample operation, in the order the QPU_W_TMUn_S writes appear in + * the program. Following the texture BO handle indices is the actual + * uniform data. + * + * The individual uniform state blocks don't have sizes passed in, + * because the kernel has to determine the sizes anyway during shader + * code validation. + */ + __u64 uniforms; + __u64 bo_handles; + + /* Size in bytes of the binner command list. */ + __u32 bin_cl_size; + /* Size in bytes of the set of shader records. */ + __u32 shader_rec_size; + /* Number of shader records. + * + * This could just be computed from the contents of shader_records and + * the address bits of references to them from the bin CL, but it + * keeps the kernel from having to resize some allocations it makes. + */ + __u32 shader_rec_count; + /* Size in bytes of the uniform state. */ + __u32 uniforms_size; + + /* Number of BO handles passed in (size is that times 4). */ + __u32 bo_handle_count; + + /* RCL setup: */ + __u16 width; + __u16 height; + __u8 min_x_tile; + __u8 min_y_tile; + __u8 max_x_tile; + __u8 max_y_tile; + struct drm_vc4_submit_rcl_surface color_read; + struct drm_vc4_submit_rcl_surface color_write; + struct drm_vc4_submit_rcl_surface zs_read; + struct drm_vc4_submit_rcl_surface zs_write; + struct drm_vc4_submit_rcl_surface msaa_color_write; + struct drm_vc4_submit_rcl_surface msaa_zs_write; + __u32 clear_color[2]; + __u32 clear_z; + __u8 clear_s; + + __u32 pad:24; + +#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) + __u32 flags; + + /* Returned value of the seqno of this render job (for the + * wait ioctl). + */ + __u64 seqno; +}; + +/** + * struct drm_vc4_wait_seqno - ioctl argument for waiting for + * DRM_VC4_SUBMIT_CL completion using its returned seqno. + * + * timeout_ns is the timeout in nanoseconds, where "0" means "don't + * block, just return the status." + */ +struct drm_vc4_wait_seqno { + __u64 seqno; + __u64 timeout_ns; +}; + +/** + * struct drm_vc4_wait_bo - ioctl argument for waiting for + * completion of the last DRM_VC4_SUBMIT_CL on a BO. + * + * This is useful for cases where multiple processes might be + * rendering to a BO and you want to wait for all rendering to be + * completed. + */ +struct drm_vc4_wait_bo { + __u32 handle; + __u32 pad; + __u64 timeout_ns; +}; + +/** + * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs. + * + * There are currently no values for the flags argument, but it may be + * used in a future extension. + */ +struct drm_vc4_create_bo { + __u32 size; + __u32 flags; + /** Returned GEM handle for the BO. */ + __u32 handle; + __u32 pad; +}; + +/** + * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs. + * + * This doesn't actually perform an mmap. Instead, it returns the + * offset you need to use in an mmap on the DRM device node. This + * means that tools like valgrind end up knowing about the mapped + * memory. + * + * There are currently no values for the flags argument, but it may be + * used in a future extension. + */ +struct drm_vc4_mmap_bo { + /** Handle for the object being mapped. */ + __u32 handle; + __u32 flags; + /** offset into the drm node to use for subsequent mmap call. */ + __u64 offset; +}; + +/** + * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4 + * shader BOs. + * + * Since allowing a shader to be overwritten while it's also being + * executed from would allow privlege escalation, shaders must be + * created using this ioctl, and they can't be mmapped later. + */ +struct drm_vc4_create_shader_bo { + /* Size of the data argument. */ + __u32 size; + /* Flags, currently must be 0. */ + __u32 flags; + + /* Pointer to the data. */ + __u64 data; + + /** Returned GEM handle for the BO. */ + __u32 handle; + /* Pad, must be 0. */ + __u32 pad; +}; + +struct drm_vc4_get_hang_state_bo { + __u32 handle; + __u32 paddr; + __u32 size; + __u32 pad; +}; + +/** + * struct drm_vc4_hang_state - ioctl argument for collecting state + * from a GPU hang for analysis. +*/ +struct drm_vc4_get_hang_state { + /** Pointer to array of struct drm_vc4_get_hang_state_bo. */ + __u64 bo; + /** + * On input, the size of the bo array. Output is the number + * of bos to be returned. + */ + __u32 bo_count; + + __u32 start_bin, start_render; + + __u32 ct0ca, ct0ea; + __u32 ct1ca, ct1ea; + __u32 ct0cs, ct1cs; + __u32 ct0ra0, ct1ra0; + + __u32 bpca, bpcs; + __u32 bpoa, bpos; + + __u32 vpmbase; + + __u32 dbge; + __u32 fdbgo; + __u32 fdbgb; + __u32 fdbgr; + __u32 fdbgs; + __u32 errstat; + + /* Pad that we may save more registers into in the future. */ + __u32 pad[16]; +}; + +#endif /* _VC4_DRM_H_ */ |
From: <rob...@ke...> - 2016-02-12 23:32:51
|
freedreno/freedreno_drmif.h | 1 freedreno/kgsl/kgsl_pipe.c | 3 ++ freedreno/msm/msm_drm.h | 1 freedreno/msm/msm_pipe.c | 45 +++++++++++++++++++++++++++++++------------- 4 files changed, 37 insertions(+), 13 deletions(-) New commits: commit 9b77443f6344791851a6c2067e4081b7f43618ea Author: Rob Clark <rob...@fr...> Date: Wed Feb 10 12:27:33 2016 -0500 freedreno: add support for FD_MAX_FREQ Only msm backend supports this. Sorry, if you are using kgsl, no time-elapsed query for you. Signed-off-by: Rob Clark <rob...@fr...> diff --git a/freedreno/freedreno_drmif.h b/freedreno/freedreno_drmif.h index 5547e94..950fd63 100644 --- a/freedreno/freedreno_drmif.h +++ b/freedreno/freedreno_drmif.h @@ -50,6 +50,7 @@ enum fd_param_id { FD_GMEM_SIZE, FD_GPU_ID, FD_CHIP_ID, + FD_MAX_FREQ, }; /* bo flags: */ diff --git a/freedreno/kgsl/kgsl_pipe.c b/freedreno/kgsl/kgsl_pipe.c index 58b3b4d..5569da0 100644 --- a/freedreno/kgsl/kgsl_pipe.c +++ b/freedreno/kgsl/kgsl_pipe.c @@ -50,6 +50,9 @@ static int kgsl_pipe_get_param(struct fd_pipe *pipe, case FD_CHIP_ID: *value = kgsl_pipe->devinfo.chip_id; return 0; + case FD_MAX_FREQ: + /* unsupported on kgsl */ + return -1; default: ERROR_MSG("invalid param id: %d", param); return -1; diff --git a/freedreno/msm/msm_pipe.c b/freedreno/msm/msm_pipe.c index 38db21d..f539b9a 100644 --- a/freedreno/msm/msm_pipe.c +++ b/freedreno/msm/msm_pipe.c @@ -67,6 +67,8 @@ static int msm_pipe_get_param(struct fd_pipe *pipe, case FD_CHIP_ID: *value = msm_pipe->chip_id; return 0; + case FD_MAX_FREQ: + return query_param(pipe, MSM_PARAM_MAX_FREQ, value); default: ERROR_MSG("invalid param id: %d", param); return -1; commit bc5497d061aaaf31e6b38109443c20e1ebfd21a3 Author: Rob Clark <rob...@fr...> Date: Wed Feb 10 12:26:55 2016 -0500 freedreno: small refactor for get_param Will simplify next commit. Signed-off-by: Rob Clark <rob...@fr...> diff --git a/freedreno/msm/msm_pipe.c b/freedreno/msm/msm_pipe.c index aa0866b..38db21d 100644 --- a/freedreno/msm/msm_pipe.c +++ b/freedreno/msm/msm_pipe.c @@ -32,6 +32,25 @@ #include "msm_priv.h" +static int query_param(struct fd_pipe *pipe, uint32_t param, + uint64_t *value) +{ + struct msm_pipe *msm_pipe = to_msm_pipe(pipe); + struct drm_msm_param req = { + .pipe = msm_pipe->pipe, + .param = param, + }; + int ret; + + ret = drmCommandWriteRead(pipe->dev->fd, DRM_MSM_GET_PARAM, + &req, sizeof(req)); + if (ret) + return ret; + + *value = req.value; + + return 0; +} static int msm_pipe_get_param(struct fd_pipe *pipe, enum fd_param_id param, uint64_t *value) @@ -87,21 +106,15 @@ static const struct fd_pipe_funcs funcs = { .destroy = msm_pipe_destroy, }; -static uint64_t get_param(struct fd_device *dev, uint32_t pipe, uint32_t param) +static uint64_t get_param(struct fd_pipe *pipe, uint32_t param) { - struct drm_msm_param req = { - .pipe = pipe, - .param = param, - }; - int ret; - - ret = drmCommandWriteRead(dev->fd, DRM_MSM_GET_PARAM, &req, sizeof(req)); + uint64_t value; + int ret = query_param(pipe, param, &value); if (ret) { ERROR_MSG("get-param failed! %d (%s)", ret, strerror(errno)); return 0; } - - return req.value; + return value; } drm_private struct fd_pipe * msm_pipe_new(struct fd_device *dev, @@ -123,10 +136,14 @@ drm_private struct fd_pipe * msm_pipe_new(struct fd_device *dev, pipe = &msm_pipe->base; pipe->funcs = &funcs; + /* initialize before get_param(): */ + pipe->dev = dev; msm_pipe->pipe = pipe_id[id]; - msm_pipe->gpu_id = get_param(dev, pipe_id[id], MSM_PARAM_GPU_ID); - msm_pipe->gmem = get_param(dev, pipe_id[id], MSM_PARAM_GMEM_SIZE); - msm_pipe->chip_id = get_param(dev, pipe_id[id], MSM_PARAM_CHIP_ID); + + /* these params should be supported since the first version of drm/msm: */ + msm_pipe->gpu_id = get_param(pipe, MSM_PARAM_GPU_ID); + msm_pipe->gmem = get_param(pipe, MSM_PARAM_GMEM_SIZE); + msm_pipe->chip_id = get_param(pipe, MSM_PARAM_CHIP_ID); if (! msm_pipe->gpu_id) goto fail; commit c47385ccdae1d3a461e35c558af34431f10c83e2 Author: Rob Clark <rob...@fr...> Date: Wed Feb 10 12:26:20 2016 -0500 freedreno: update uapi In drm-next.. needed for time-elapsed (and future perf ctrs) in mesa. Signed-off-by: Rob Clark <rob...@fr...> diff --git a/freedreno/msm/msm_drm.h b/freedreno/msm/msm_drm.h index f7474c5..baf505c 100644 --- a/freedreno/msm/msm_drm.h +++ b/freedreno/msm/msm_drm.h @@ -58,6 +58,7 @@ struct drm_msm_timespec { #define MSM_PARAM_GPU_ID 0x01 #define MSM_PARAM_GMEM_SIZE 0x02 #define MSM_PARAM_CHIP_ID 0x03 +#define MSM_PARAM_MAX_FREQ 0x04 struct drm_msm_param { uint32_t pipe; /* in, MSM_PIPE_x */ |
From: <rob...@ke...> - 2016-11-05 14:26:53
|
Makefile.sources | 1 freedreno/freedreno_drmif.h | 1 freedreno/freedreno_priv.h | 3 freedreno/freedreno_ringbuffer.c | 11 ++ freedreno/freedreno_ringbuffer.h | 5 + freedreno/kgsl/kgsl_ringbuffer.c | 6 + freedreno/msm/msm_drm.h | 22 +++++ freedreno/msm/msm_ringbuffer.c | 18 ++++ libsync.h | 148 +++++++++++++++++++++++++++++++++++++++ 9 files changed, 207 insertions(+), 8 deletions(-) New commits: commit e9eb44b45b8d4a2f06ef83365b28eca55c0f3fb4 Author: Rob Clark <rob...@fr...> Date: Mon Aug 15 13:26:18 2016 -0400 freedreno: add fence fd support Signed-off-by: Rob Clark <rob...@fr...> diff --git a/freedreno/freedreno_drmif.h b/freedreno/freedreno_drmif.h index 2d913e6..7a8073f 100644 --- a/freedreno/freedreno_drmif.h +++ b/freedreno/freedreno_drmif.h @@ -92,6 +92,7 @@ int fd_device_fd(struct fd_device *dev); enum fd_version { FD_VERSION_MADVISE = 1, /* kernel supports madvise */ FD_VERSION_UNLIMITED_CMDS = 1, /* submits w/ >4 cmd buffers (growable ringbuffer) */ + FD_VERSION_FENCE_FD = 2, /* submit command supports in/out fences */ }; enum fd_version fd_device_version(struct fd_device *dev); diff --git a/freedreno/freedreno_priv.h b/freedreno/freedreno_priv.h index cdfdbe8..86da83b 100644 --- a/freedreno/freedreno_priv.h +++ b/freedreno/freedreno_priv.h @@ -133,7 +133,8 @@ struct fd_ringmarker { struct fd_ringbuffer_funcs { void * (*hostptr)(struct fd_ringbuffer *ring); - int (*flush)(struct fd_ringbuffer *ring, uint32_t *last_start); + int (*flush)(struct fd_ringbuffer *ring, uint32_t *last_start, + int in_fence_fd, int *out_fence_fd); void (*grow)(struct fd_ringbuffer *ring, uint32_t size); void (*reset)(struct fd_ringbuffer *ring); void (*emit_reloc)(struct fd_ringbuffer *ring, diff --git a/freedreno/freedreno_ringbuffer.c b/freedreno/freedreno_ringbuffer.c index 22dafb3..c132145 100644 --- a/freedreno/freedreno_ringbuffer.c +++ b/freedreno/freedreno_ringbuffer.c @@ -80,10 +80,15 @@ void fd_ringbuffer_reset(struct fd_ringbuffer *ring) ring->funcs->reset(ring); } -/* maybe get rid of this and use fd_ringmarker_flush() from DDX too? */ int fd_ringbuffer_flush(struct fd_ringbuffer *ring) { - return ring->funcs->flush(ring, ring->last_start); + return ring->funcs->flush(ring, ring->last_start, -1, NULL); +} + +int fd_ringbuffer_flush2(struct fd_ringbuffer *ring, int in_fence_fd, + int *out_fence_fd) +{ + return ring->funcs->flush(ring, ring->last_start, in_fence_fd, out_fence_fd); } void fd_ringbuffer_grow(struct fd_ringbuffer *ring, uint32_t ndwords) @@ -177,5 +182,5 @@ uint32_t fd_ringmarker_dwords(struct fd_ringmarker *start, int fd_ringmarker_flush(struct fd_ringmarker *marker) { struct fd_ringbuffer *ring = marker->ring; - return ring->funcs->flush(ring, marker->cur); + return ring->funcs->flush(ring, marker->cur, -1, NULL); } diff --git a/freedreno/freedreno_ringbuffer.h b/freedreno/freedreno_ringbuffer.h index 8899b5d..108d5a6 100644 --- a/freedreno/freedreno_ringbuffer.h +++ b/freedreno/freedreno_ringbuffer.h @@ -56,6 +56,11 @@ void fd_ringbuffer_set_parent(struct fd_ringbuffer *ring, struct fd_ringbuffer *parent); void fd_ringbuffer_reset(struct fd_ringbuffer *ring); int fd_ringbuffer_flush(struct fd_ringbuffer *ring); +/* in_fence_fd: -1 for no in-fence, else fence fd + * out_fence_fd: NULL for no output-fence requested, else ptr to return out-fence + */ +int fd_ringbuffer_flush2(struct fd_ringbuffer *ring, int in_fence_fd, + int *out_fence_fd); void fd_ringbuffer_grow(struct fd_ringbuffer *ring, uint32_t ndwords); uint32_t fd_ringbuffer_timestamp(struct fd_ringbuffer *ring); diff --git a/freedreno/kgsl/kgsl_ringbuffer.c b/freedreno/kgsl/kgsl_ringbuffer.c index 7b3298a..e4696b1 100644 --- a/freedreno/kgsl/kgsl_ringbuffer.c +++ b/freedreno/kgsl/kgsl_ringbuffer.c @@ -113,7 +113,8 @@ static void * kgsl_ringbuffer_hostptr(struct fd_ringbuffer *ring) return kgsl_ring->bo->hostptr; } -static int kgsl_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start) +static int kgsl_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start, + int in_fence_fd, int *out_fence_fd) { struct kgsl_ringbuffer *kgsl_ring = to_kgsl_ringbuffer(ring); struct kgsl_pipe *kgsl_pipe = to_kgsl_pipe(ring->pipe); @@ -131,6 +132,9 @@ static int kgsl_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_star }; int ret; + assert(in_fence_fd == -1); + assert(out_fence_fd == NULL); + kgsl_pipe_pre_submit(kgsl_pipe); /* z180_cmdstream_issueibcmds() is made of fail: */ diff --git a/freedreno/msm/msm_ringbuffer.c b/freedreno/msm/msm_ringbuffer.c index 60f0315..5117df1 100644 --- a/freedreno/msm/msm_ringbuffer.c +++ b/freedreno/msm/msm_ringbuffer.c @@ -395,7 +395,8 @@ static void dump_submit(struct msm_ringbuffer *msm_ring) } } -static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start) +static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start, + int in_fence_fd, int *out_fence_fd) { struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring); struct drm_msm_gem_submit req = { @@ -404,6 +405,15 @@ static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start uint32_t i; int ret; + if (in_fence_fd != -1) { + req.flags |= MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_NO_IMPLICIT; + req.fence_fd = in_fence_fd; + } + + if (out_fence_fd) { + req.flags |= MSM_SUBMIT_FENCE_FD_OUT; + } + finalize_current_cmd(ring, last_start); /* needs to be after get_cmd() as that could create bos/cmds table: */ @@ -435,6 +445,10 @@ static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start struct msm_cmd *msm_cmd = msm_ring->cmds[i]; msm_cmd->ring->last_timestamp = req.fence; } + + if (out_fence_fd) { + *out_fence_fd = req.fence_fd; + } } flush_reset(ring); commit 9270d984cde31a8abc5f9ec31cbd86a10b883864 Author: Rob Clark <rob...@fr...> Date: Mon Aug 15 12:52:31 2016 -0400 freedreno: sync uapi header Signed-off-by: Rob Clark <rob...@fr...> diff --git a/freedreno/msm/msm_drm.h b/freedreno/msm/msm_drm.h index cbf75c3..ed4c8d4 100644 --- a/freedreno/msm/msm_drm.h +++ b/freedreno/msm/msm_drm.h @@ -50,6 +50,15 @@ extern "C" { #define MSM_PIPE_2D1 0x02 #define MSM_PIPE_3D0 0x10 +/* The pipe-id just uses the lower bits, so can be OR'd with flags in + * the upper 16 bits (which could be extended further, if needed, maybe + * we extend/overload the pipe-id some day to deal with multiple rings, + * but even then I don't think we need the full lower 16 bits). + */ +#define MSM_PIPE_ID_MASK 0xffff +#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK) +#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK) + /* timeouts are specified in clock-monotonic absolute times (to simplify * restarting interrupted ioctls). The following struct is logically the * same as 'struct timespec' but 32/64b ABI safe. @@ -183,17 +192,28 @@ struct drm_msm_gem_submit_bo { __u64 presumed; /* in/out, presumed buffer address */ }; +/* Valid submit ioctl flags: */ +#define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */ +#define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */ +#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */ +#define MSM_SUBMIT_FLAGS ( \ + MSM_SUBMIT_NO_IMPLICIT | \ + MSM_SUBMIT_FENCE_FD_IN | \ + MSM_SUBMIT_FENCE_FD_OUT | \ + 0) + /* Each cmdstream submit consists of a table of buffers involved, and * one or more cmdstream buffers. This allows for conditional execution * (context-restore), and IB buffers needed for per tile/bin draw cmds. */ struct drm_msm_gem_submit { - __u32 pipe; /* in, MSM_PIPE_x */ + __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */ __u32 fence; /* out */ __u32 nr_bos; /* in, number of submit_bo's */ __u32 nr_cmds; /* in, number of submit_cmd's */ __u64 __user bos; /* in, ptr to array of submit_bo's */ __u64 __user cmds; /* in, ptr to array of submit_cmd's */ + __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */ }; /* The normal way to synchronize with the GPU is just to CPU_PREP on diff --git a/freedreno/msm/msm_ringbuffer.c b/freedreno/msm/msm_ringbuffer.c index a78806c..60f0315 100644 --- a/freedreno/msm/msm_ringbuffer.c +++ b/freedreno/msm/msm_ringbuffer.c @@ -399,7 +399,7 @@ static int msm_ringbuffer_flush(struct fd_ringbuffer *ring, uint32_t *last_start { struct msm_ringbuffer *msm_ring = to_msm_ringbuffer(ring); struct drm_msm_gem_submit req = { - .pipe = to_msm_pipe(ring->pipe)->pipe, + .flags = to_msm_pipe(ring->pipe)->pipe, }; uint32_t i; int ret; commit f803a45e744272190aaaab1ad7c702641190d002 Author: Rob Clark <rob...@fr...> Date: Mon Aug 15 14:45:35 2016 -0400 add libsync.h helper Rather than cut/pasting these couple ioctl wrappers everywhere, just stuff them as static-inline into a header. This is probably mostly used from mesa, but some drivers, test apps, etc may also want to use it from libdrm. v2: handle EINTR, add sync_accumulate() based on #dri-devel discussion, etc Signed-off-by: Rob Clark <rob...@fr...> Reviewed-by: Chris Wilson <ch...@ch...> diff --git a/Makefile.sources b/Makefile.sources index a57036a..10aa1d0 100644 --- a/Makefile.sources +++ b/Makefile.sources @@ -13,6 +13,7 @@ LIBDRM_FILES := \ util_math.h LIBDRM_H_FILES := \ + libsync.h \ xf86drm.h \ xf86drmMode.h diff --git a/libsync.h b/libsync.h new file mode 100644 index 0000000..f1a2f96 --- /dev/null +++ b/libsync.h @@ -0,0 +1,148 @@ +/* + * sync abstraction + * Copyright 2015-2016 Collabora Ltd. + * + * Based on the implementation from the Android Open Source Project, + * + * Copyright 2012 Google, Inc + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _LIBSYNC_H +#define _LIBSYNC_H + +#include <assert.h> +#include <errno.h> +#include <stdint.h> +#include <string.h> +#include <sys/ioctl.h> +#include <sys/poll.h> +#include <unistd.h> + +#if defined(__cplusplus) +extern "C" { +#endif + +#ifndef SYNC_IOC_MERGE +/* duplicated from linux/sync_file.h to avoid build-time dependency + * on new (v4.7) kernel headers. Once distro's are mostly using + * something newer than v4.7 drop this and #include <linux/sync_file.h> + * instead. + */ +struct sync_merge_data { + char name[32]; + int32_t fd2; + int32_t fence; + uint32_t flags; + uint32_t pad; +}; +#define SYNC_IOC_MAGIC '>' +#define SYNC_IOC_MERGE _IOWR(SYNC_IOC_MAGIC, 3, struct sync_merge_data) +#endif + + +static inline int sync_wait(int fd, int timeout) +{ + struct pollfd fds = {0}; + int ret; + + fds.fd = fd; + fds.events = POLLIN; + + do { + ret = poll(&fds, 1, timeout); + if (ret > 0) { + if (fds.revents & (POLLERR | POLLNVAL)) { + errno = EINVAL; + return -1; + } + return 0; + } else if (ret == 0) { + errno = ETIME; + return -1; + } + } while (ret == -1 && (errno == EINTR || errno == EAGAIN)); + + return ret; +} + +static inline int sync_merge(const char *name, int fd1, int fd2) +{ + struct sync_merge_data data = {0}; + int ret; + + data.fd2 = fd2; + strncpy(data.name, name, sizeof(data.name)); + + do { + ret = ioctl(fd1, SYNC_IOC_MERGE, &data); + } while (ret == -1 && (errno == EINTR || errno == EAGAIN)); + + if (ret < 0) + return ret; + + return data.fence; +} + +/* accumulate fd2 into fd1. If *fd1 is not a valid fd then dup fd2, + * otherwise sync_merge() and close the old *fd1. This can be used + * to implement the pattern: + * + * init() + * { + * batch.fence_fd = -1; + * } + * + * // does *NOT* take ownership of fd + * server_sync(int fd) + * { + * if (sync_accumulate("foo", &batch.fence_fd, fd)) { + * ... error ... + * } + * } + */ +static inline int sync_accumulate(const char *name, int *fd1, int fd2) +{ + int ret; + + assert(fd2 >= 0); + + if (*fd1 < 0) { + *fd1 = dup(fd2); + return 0; + } + + ret = sync_merge(name, *fd1, fd2); + if (ret < 0) { + /* leave *fd1 as it is */ + return ret; + } + + close(*fd1); + *fd1 = ret; + + return 0; +} + +#if defined(__cplusplus) +} +#endif + +#endif |
From: <eve...@ke...> - 2016-11-14 20:00:18
|
Makefile.am | 1 configure.ac | 2 include/drm/README | 157 +++++++++++++++++++++++++++++++++++++++++++++++++++++ xf86drm.c | 4 - 4 files changed, 161 insertions(+), 3 deletions(-) New commits: commit 317bdff14ac8f1e8735f97d96c7eb963e1e47a4a Author: Emil Velikov <emi...@gm...> Date: Mon Nov 14 19:48:38 2016 +0000 Bump version for release diff --git a/configure.ac b/configure.ac index 1c7a7fb..9f25a4c 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.72], + [2.4.73], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) commit f53d3542c1dfa2a1c1a5a7155d058df9a6bcce7b Author: Emil Velikov <emi...@co...> Date: Fri Nov 11 19:04:11 2016 +0000 xd86drm: read more than 128 bytes of uevent in drmParsePciBusInfo Some platforms (such as Macs using OF) can have more information in the uevent file thus reading only the first 128 might not be sufficient. Bump it to 512, which "should be enough for everybody" ;-) v2: Use sizeof(data)-1 over hardcoded number (Eric). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98629 Signed-off-by: Emil Velikov <emi...@co...> Reported-by: Mingcong Bai <jeffbai@aosc.xyz> Tested-by: Mingcong Bai <jeffbai@aosc.xyz> (v1) Reviewed-by: Eric Engestrom <eri...@im...> diff --git a/xf86drm.c b/xf86drm.c index 52add5e..9b97bbb 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -2864,7 +2864,7 @@ static int drmParsePciBusInfo(int maj, int min, drmPciBusInfoPtr info) { #ifdef __linux__ char path[PATH_MAX + 1]; - char data[128 + 1]; + char data[512 + 1]; char *str; int domain, bus, dev, func; int fd, ret; @@ -2875,7 +2875,7 @@ static int drmParsePciBusInfo(int maj, int min, drmPciBusInfoPtr info) return -errno; ret = read(fd, data, sizeof(data)); - data[128] = '\0'; + data[sizeof(data)-1] = '\0'; close(fd); if (ret < 0) return -errno; commit de13ea387737cdc99ec43813acb4d4f443075db2 Author: Emil Velikov <emi...@gm...> Date: Mon Nov 14 17:59:28 2016 +0000 headers: Add README file Since we're trying to standardise and make things more consistent in the area, add a basic README which covers some of the more popular topics. v2: - Drop drm-misc (Daniel Vetter) v3: - Elaborate on when and which headers to update - Add a list of headers and the respective "issues" - Add file to EXTRA_DIST Cc: Dave Airlie <ai...@re...> Reviewed-by: Daniel Vetter <dan...@ff...> (v1) Signed-off-by: Emil Velikov <emi...@gm...> diff --git a/Makefile.am b/Makefile.am index 630edc4..2e46bde 100644 --- a/Makefile.am +++ b/Makefile.am @@ -133,6 +133,7 @@ if HAVE_VMWGFX klibdrminclude_HEADERS += $(LIBDRM_INCLUDE_VMWGFX_H_FILES) endif +EXTRA_DIST = include/drm/README copy-headers : cp -r $(kernel_source)/include/uapi/drm/*.h $(top_srcdir)/include/drm/ diff --git a/include/drm/README b/include/drm/README new file mode 100644 index 0000000..c3292f3 --- /dev/null +++ b/include/drm/README @@ -0,0 +1,157 @@ +What are these headers ? +------------------------ +This is the canonical source of drm headers that user space should use for +communicating with the kernel DRM subsystem. + +They flow from the kernel, thus any changes must be merged there first. +Do _not_ attempt to "fix" these by deviating from the kernel ones ! + + +Non-linux platforms - changes/patches +------------------------------------- +If your platform has local changes, please send them upstream for inclusion. +Even if your patches don't get accepted in their current form, devs will +give you feedback on how to address things properly. + +git send-email --subject-prefix="PATCH libdrm" your patches to dri-devel +mailing list. + +Before doing so, please consider the following: + - Have the [libdrm vs kernel] headers on your platform deviated ? +Consider unifying them first. + + - Have you introduced additional ABI that's not available in Linux ? +Propose it for [Linux kernel] upstream inclusion. +If that doesn't work out (hopefully it never does), move it to another header +and/or keep the change(s) local ? + + - Are your changes DRI1/UMS specific ? +There is virtually no interest/power in keeping those legacy interfaces. They +are around due to the kernel "thou shalt not break existing user space" rule. + +Consider porting the driver to DRI2/KMS - all (almost?) sensible hardware is +capable of supporting those. + + +Which headers go where ? +------------------------ +A snipped from the, now removed, Makefile.am used to state: + + XXX airlied says, nothing besides *_drm.h and drm*.h should be necessary. + however, r300 and via need their reg headers installed in order to build. + better solutions are welcome. + +Obviously the r300 and via headers are no longer around ;-) + +Reason behind is that the drm headers can be used as a basic communications +channel with the respective kernel modules. If more advanced functionality is +required one can pull the specific libdrm_$driver which is free to pull +additional files from the kernel. + +For example: nouveau has nouveau/nvif/*.h while vc4 has vc4/*.h + +If your driver is still in prototyping/staging state, consider moving the +$driver_drm.h into $driver and _not_ installing it. An header providing opaque +definitions and access [via $driver_drmif.h or similar] would be better fit. + + +When and which headers to update +-------------------------------- +Ideally all files will be synced (updated) with the latest released kernel on +each libdrm release. Sadly that's not yet possible since quite a few headers +differ significantly - see Outdated or Broken Headers section below. + +That said, it's up-to the individual developers to sync with newer version +(from drm-next) as they see fit. + + +When and how to update these files +---------------------------------- +In order to update the files do the following: + - Switch to a Linux kernel tree/branch which is not rebased. +For example: airlied/drm-next + - Install the headers via `make headers_install' to a separate location. + - Copy the drm header[s] + git add + git commit. + - Note: Your commit message must include: + a) Brief summary on the delta. If there's any change that looks like an +API/ABI break one _must_ explicitly state why it's safe to do so. + b) "Generated using make headers_install." + c) "Generated from $tree/branch commit $sha" + + +Outdated or Broken Headers +-------------------------- +This section contains a list of headers and the respective "issues" they might +have relative to their kernel equivalent. + +Nearly all headers: + - Missing extern C notation. +Status: Trivial. + +Most UMS headers: + - Not using fixed size interers - compat ioctls are broken. +Status: ? +Promote to fixed size ints, which match the current (32bit) ones. + + +amdgpu_drm.h + - Using the stdint.h uint*_t over the respective __u* ones +Status: Trivial. + +drm_mode.h + - Missing DPI encode/connector pair. +Status: Trivial. + +i915_drm.h + - Missing PARAMS - HAS_POOLED_EU, MIN_EU_IN_POOL CONTEXT_PARAM_NO_ERROR_CAPTURE +Status: Trivial. + +mga_drm.h + - Typo fix, use struct over typedef. +Status: Trivial. + +nouveau_drm.h + - Missing macros NOUVEAU_GETPARAM*, NOUVEAU_DRM_HEADER_PATCHLEVEL, structs, +enums, using stdint.h over the __u* types. +Status: ? + +qxl_drm.h + - Using the stdint.h uint*_t over the respective __u* ones +Status: Trivial. + +r128_drm.h + - Broken compat ioctls. + +radeon_drm.h + - Missing RADEON_TILING_R600_NO_SCANOUT, CIK_TILE_MODE_*, broken UMS ioctls, +using stdint types. + - Both kernel and libdrm: missing padding - +drm_radeon_gem_{create,{g,s}et_tiling,set_domain} others ? +Status: ? + +savage_drm.h + - Renamed ioctls - DRM_IOCTL_SAVAGE_{,BCI}_EVENT_EMIT, compat ioctls are broken. +Status: ? + +sis_drm.h + - Borken ioctls + libdrm uses int vs kernel long +Status: ? + +via_drm.h + - Borken ioctls - libdrm int vs kernel long +Status: ? + + +omap_drm.h (living in $TOP/omap) + - License mismatch, missing DRM_IOCTL_OMAP_GEM_NEW and related struct +Status: ? + +msm_drm.h (located in $TOP/freedreno/msm/) + - License mismatch, missing MSM_PIPE_*, MSM_SUBMIT_*. Renamed +drm_msm_gem_submit::flags, missing drm_msm_gem_submit::fence_fd. +Status: ? + +exynos_drm.h (living in $TOP/exynos) + - License mismatch, now using fixed size ints (but not everywhere). Lots of +new stuff. +Status: ? |
From: <eve...@ke...> - 2016-12-24 17:09:02
|
xf86drm.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 56 insertions(+), 8 deletions(-) New commits: commit eebefaf72c55fd2116f4c983ec6724a4d66ab413 Author: Jonathan Gray <js...@js...> Date: Sat Dec 17 16:09:53 2016 +1100 xf86drm: don't fatal on per device error in drmGetDevice[s]2 When iterating over all the device nodes if drmProcessPciDevice() returned an error for any node the function would return an error, ignoring any valid nodes. The result of this on OpenBSD where drmProcessPciDevice() results in device nodes being opened to issue ioctls to get pci data was that data obtained from /dev/drm0 would be ignored if /dev/drm1 could not be opened. Reviewed-by: Emil Velikov <emi...@gm...> Signed-off-by: Jonathan Gray <js...@js...> diff --git a/xf86drm.c b/xf86drm.c index f684c01..7d7df18 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -3383,7 +3383,7 @@ int drmGetDevice2(int fd, uint32_t flags, drmDevicePtr *device) case DRM_BUS_PCI: ret = drmProcessPciDevice(&d, node, node_type, maj, min, true, flags); if (ret) - goto free_devices; + continue; break; default: @@ -3514,7 +3514,7 @@ int drmGetDevices2(uint32_t flags, drmDevicePtr devices[], int max_devices) ret = drmProcessPciDevice(&device, node, node_type, maj, min, devices != NULL, flags); if (ret) - goto free_devices; + continue; break; default: commit e2e766d5acdbb826f1cfe5643669db54ee86f456 Author: Jonathan Gray <js...@js...> Date: Sat Dec 17 16:09:52 2016 +1100 xf86drm: add a non-sysfs version of drmGetDeviceNameFromFd2 Implement a generic drmGetDeviceNameFromFd2() to use on non-linux systems without sysfs. v2: remove min < base test as requested by Emil Reviewed-by: Emil Velikov <emi...@gm...> Signed-off-by: Jonathan Gray <js...@js...> diff --git a/xf86drm.c b/xf86drm.c index f6850aa..f684c01 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -3627,7 +3627,47 @@ char *drmGetDeviceNameFromFd2(int fd) fclose(f); return device_name; #else -#warning "Missing implementation of drmGetDeviceNameFromFd2" - return NULL; + struct stat sbuf; + char node[PATH_MAX + 1]; + const char *dev_name; + int node_type; + int maj, min, n, base; + + if (fstat(fd, &sbuf)) + return NULL; + + maj = major(sbuf.st_rdev); + min = minor(sbuf.st_rdev); + + if (maj != DRM_MAJOR || !S_ISCHR(sbuf.st_mode)) + return NULL; + + node_type = drmGetMinorType(min); + if (node_type == -1) + return NULL; + + switch (node_type) { + case DRM_NODE_PRIMARY: + dev_name = DRM_DEV_NAME; + break; + case DRM_NODE_CONTROL: + dev_name = DRM_CONTROL_DEV_NAME; + break; + case DRM_NODE_RENDER: + dev_name = DRM_RENDER_DEV_NAME; + break; + default: + return NULL; + }; + + base = drmGetMinorBase(node_type); + if (base < 0) + return NULL; + + n = snprintf(node, PATH_MAX, dev_name, DRM_DIR_NAME, min - base); + if (n == -1 || n >= PATH_MAX) + return NULL; + + return strdup(node); #endif } commit d5cf3f98314c1b9d87216e00c30c9fef06ff24c3 Author: Jonathan Gray <js...@js...> Date: Sat Dec 17 16:09:51 2016 +1100 xf86drm: adjust device node path for minor base When constructing a path to a device node the minor number retrieved from fstat needs to have the offset of the node type subtracted from it. Control and render node types have the same major as the primary node but each has their own block of minor types at fixed offsets. v2: remove min < base test as requested by Emil Reviewed-by: Emil Velikov <emi...@gm...> Signed-off-by: Jonathan Gray <js...@js...> diff --git a/xf86drm.c b/xf86drm.c index b5eeeb0..f6850aa 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -2838,7 +2838,7 @@ out_close_dir: char buf[PATH_MAX + 1]; const char *dev_name; unsigned int maj, min; - int n; + int n, base; if (fstat(fd, &sbuf)) return NULL; @@ -2863,7 +2863,11 @@ out_close_dir: return NULL; }; - n = snprintf(buf, sizeof(buf), dev_name, DRM_DIR_NAME, min); + base = drmGetMinorBase(type); + if (base < 0) + return NULL; + + n = snprintf(buf, sizeof(buf), dev_name, DRM_DIR_NAME, min - base); if (n == -1 || n >= sizeof(buf)) return NULL; @@ -3262,7 +3266,7 @@ int drmGetDevice2(int fd, uint32_t flags, drmDevicePtr *device) char node[PATH_MAX + 1]; const char *dev_name; int node_type, subsystem_type; - int maj, min, n, ret; + int maj, min, n, ret, base; if (fd == -1 || device == NULL) return -EINVAL; @@ -3294,7 +3298,11 @@ int drmGetDevice2(int fd, uint32_t flags, drmDevicePtr *device) return -EINVAL; }; - n = snprintf(node, PATH_MAX, dev_name, DRM_DIR_NAME, min); + base = drmGetMinorBase(node_type); + if (base < 0) + return -EINVAL; + + n = snprintf(node, PATH_MAX, dev_name, DRM_DIR_NAME, min - base); if (n == -1 || n >= PATH_MAX) return -errno; if (stat(node, &sbuf)) |
From: <ta...@ke...> - 2017-01-18 07:37:04
|
xf86drmMode.c | 2 +- xf86drmMode.h | 19 +++++++++++-------- 2 files changed, 12 insertions(+), 9 deletions(-) New commits: commit ecc2a097294dcc773dbe5e2a989f180bedb89b69 Author: Thierry Reding <tr...@nv...> Date: Mon Apr 13 11:36:59 2015 +0200 xf86drm: Fix type-punned pointer build warning CC libdrm_la-xf86drmMode.lo ../xf86drmMode.c: In function 'drmHandleEvent': ../xf86drmMode.c:854:15: warning: dereferencing type-punned pointer will break strict-aliasing rules [-Wstrict-aliasing] e = (struct drm_event *)(&buffer[i]); ^ Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99350 Reviewed-by: Emil Velikov <emi...@co...> Signed-off-by: Thierry Reding <tr...@nv...> diff --git a/xf86drmMode.c b/xf86drmMode.c index fb22f68..0266bc1 100644 --- a/xf86drmMode.c +++ b/xf86drmMode.c @@ -901,7 +901,7 @@ int drmHandleEvent(int fd, drmEventContextPtr evctx) i = 0; while (i < len) { - e = (struct drm_event *) &buffer[i]; + e = (struct drm_event *)(buffer + i); switch (e->type) { case DRM_EVENT_VBLANK: if (evctx->version < 1 || commit 4bfbe4c69e95ae3aaaa151f3ffcdd1d3e112214b Author: Thierry Reding <tr...@nv...> Date: Wed Dec 17 11:53:31 2014 +0100 xf86drmMode.h: Add DisplayPort MST and DPI encoders/connectors This brings xf86drmMode.h in sync with include/drm/drm_mode.h. Eventually we really should only have a single set of definitions rather than duplicating this in two files. v2: add DPI encoder and connector types introduced in Linux v4.7 Reviewed-by: Emil Velikov <emi...@co...> Signed-off-by: Thierry Reding <tr...@nv...> diff --git a/xf86drmMode.h b/xf86drmMode.h index 00ad81d..5b390d9 100644 --- a/xf86drmMode.h +++ b/xf86drmMode.h @@ -130,6 +130,8 @@ extern "C" { #define DRM_MODE_ENCODER_TVDAC 4 #define DRM_MODE_ENCODER_VIRTUAL 5 #define DRM_MODE_ENCODER_DSI 6 +#define DRM_MODE_ENCODER_DPMST 7 +#define DRM_MODE_ENCODER_DPI 8 #define DRM_MODE_SUBCONNECTOR_Automatic 0 #define DRM_MODE_SUBCONNECTOR_Unknown 0 @@ -157,6 +159,7 @@ extern "C" { #define DRM_MODE_CONNECTOR_eDP 14 #define DRM_MODE_CONNECTOR_VIRTUAL 15 #define DRM_MODE_CONNECTOR_DSI 16 +#define DRM_MODE_CONNECTOR_DPI 17 #define DRM_MODE_PROP_PENDING (1<<0) #define DRM_MODE_PROP_RANGE (1<<1) commit ab50ffbc703573c08e3053555414a6c4d7d778e8 Author: Thierry Reding <tr...@nv...> Date: Wed Dec 17 11:52:40 2014 +0100 xf86drmMode.h: Use consistent padding Reviewed-by: Emil Velikov <emi...@co...> Signed-off-by: Thierry Reding <tr...@nv...> diff --git a/xf86drmMode.h b/xf86drmMode.h index b684967..00ad81d 100644 --- a/xf86drmMode.h +++ b/xf86drmMode.h @@ -123,13 +123,13 @@ extern "C" { #define DRM_MODE_DITHERING_OFF 0 #define DRM_MODE_DITHERING_ON 1 -#define DRM_MODE_ENCODER_NONE 0 -#define DRM_MODE_ENCODER_DAC 1 -#define DRM_MODE_ENCODER_TMDS 2 -#define DRM_MODE_ENCODER_LVDS 3 -#define DRM_MODE_ENCODER_TVDAC 4 +#define DRM_MODE_ENCODER_NONE 0 +#define DRM_MODE_ENCODER_DAC 1 +#define DRM_MODE_ENCODER_TMDS 2 +#define DRM_MODE_ENCODER_LVDS 3 +#define DRM_MODE_ENCODER_TVDAC 4 #define DRM_MODE_ENCODER_VIRTUAL 5 -#define DRM_MODE_ENCODER_DSI 6 +#define DRM_MODE_ENCODER_DSI 6 #define DRM_MODE_SUBCONNECTOR_Automatic 0 #define DRM_MODE_SUBCONNECTOR_Unknown 0 @@ -153,8 +153,8 @@ extern "C" { #define DRM_MODE_CONNECTOR_DisplayPort 10 #define DRM_MODE_CONNECTOR_HDMIA 11 #define DRM_MODE_CONNECTOR_HDMIB 12 -#define DRM_MODE_CONNECTOR_TV 13 -#define DRM_MODE_CONNECTOR_eDP 14 +#define DRM_MODE_CONNECTOR_TV 13 +#define DRM_MODE_CONNECTOR_eDP 14 #define DRM_MODE_CONNECTOR_VIRTUAL 15 #define DRM_MODE_CONNECTOR_DSI 16 |
From: <ag...@ke...> - 2017-01-27 16:57:10
|
tests/amdgpu/amdgpu_test.c | 259 +++++++++++++++++++++++++++++++++++++++------ tests/amdgpu/amdgpu_test.h | 3 tests/amdgpu/bo_tests.c | 5 3 files changed, 233 insertions(+), 34 deletions(-) New commits: commit 8a89d5f620967a9086495d15825415ac27bf061a Author: Alex Xie <Ale...@am...> Date: Tue Jan 24 17:29:52 2017 -0500 amdgpu: A new option to run tests on render node Tested: 1. As root, tests passed on primary. 2. As root, tests passed on render node. BO export/import test was skipped 3. As non-privileged user, tests failed on primary as expected. 4. As non-privileged user, tests passed on render node. BO export/import test was skipped Reviewed-by: Emil Velikov <emi...@gm...> Signed-off-by: Alex Xie <Ale...@am...> Signed-off-by: Alex Deucher <ale...@am...> diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index c01ee54..3fd6820 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -56,6 +56,9 @@ */ int drm_amdgpu[MAX_CARDS_SUPPORTED]; +/** Open render node to test */ +int open_render_node = 0; /* By default run most tests on primary node */ + /** The table of all known test suites to run */ static CU_SuiteInfo suites[] = { { @@ -109,16 +112,17 @@ static void display_test_suites(void) /** Help string for command line parameters */ static const char usage[] = - "Usage: %s [-hlp] [<-s <suite id>> [-t <test id>]] " + "Usage: %s [-hlpr] [<-s <suite id>> [-t <test id>]] " "[-b <pci_bus_id> [-d <pci_device_id>]]\n" "where:\n" " l - Display all suites and their tests\n" + " r - Run the tests on render node\n" " b - Specify device's PCI bus id to run tests\n" " d - Specify device's PCI device id to run tests (optional)\n" " p - Display information of AMDGPU devices in system\n" " h - Display this help\n"; /** Specified options strings for getopt */ -static const char options[] = "hlps:t:b:d:"; +static const char options[] = "hlrps:t:b:d:"; /* Open AMD devices. * Return the number of AMD device openned. @@ -326,6 +330,9 @@ int main(int argc, char **argv) case 'p': display_devices = 1; break; + case 'r': + open_render_node = 1; + break; case '?': case 'h': fprintf(stderr, usage, argv[0]); @@ -336,7 +343,7 @@ int main(int argc, char **argv) } } - if (amdgpu_open_devices(0) <= 0) { + if (amdgpu_open_devices(open_render_node) <= 0) { perror("Cannot open AMDGPU device"); exit(EXIT_FAILURE); } diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h index fca92ad..e30e231 100644 --- a/tests/amdgpu/amdgpu_test.h +++ b/tests/amdgpu/amdgpu_test.h @@ -35,6 +35,9 @@ /* Forward reference for array to keep "drm" handles */ extern int drm_amdgpu[MAX_CARDS_SUPPORTED]; +/* Global variables */ +extern int open_render_node; + /************************* Basic test suite ********************************/ /* diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c index 25df767..74b5e77 100644 --- a/tests/amdgpu/bo_tests.c +++ b/tests/amdgpu/bo_tests.c @@ -152,6 +152,11 @@ static void amdgpu_bo_export_import_do_type(enum amdgpu_bo_handle_type type) static void amdgpu_bo_export_import(void) { + if (open_render_node) { + printf("(DRM render node is used. Skip export/Import test) "); + return; + } + amdgpu_bo_export_import_do_type(amdgpu_bo_handle_type_gem_flink_name); amdgpu_bo_export_import_do_type(amdgpu_bo_handle_type_dma_buf_fd); } commit 12dd7a2e9cfa20a3022cfe091e824b09c0bfb9d1 Author: Alex Xie <Ale...@am...> Date: Tue Jan 24 17:29:51 2017 -0500 amdgpu: A new option to choose which device to run most tests This can be used to test multiple GPUs v2: Use PCI bus ID and optional PCI device ID to choose device Add an option to display information of AMDGPU devices Tested: ./amdgpu_test -p ./amdgpu_test ./amdgpu_test -b 1 #fail as expected ./amdgpu_test -b 6 #pass ./amdgpu_test -b -d 1 #fail as expected ./amdgpu_test -b -d 0 #pass Reviewed-by: Emil Velikov <emi...@gm...> Signed-off-by: Alex Xie <Ale...@am...> Signed-off-by: Alex Deucher <ale...@am...> diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index d2b00d4..c01ee54 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -108,12 +108,17 @@ static void display_test_suites(void) /** Help string for command line parameters */ -static const char usage[] = "Usage: %s [-hl] [<-s <suite id>> [-t <test id>]]\n" - "where:\n" - " l - Display all suites and their tests\n" - " h - Display this help\n"; +static const char usage[] = + "Usage: %s [-hlp] [<-s <suite id>> [-t <test id>]] " + "[-b <pci_bus_id> [-d <pci_device_id>]]\n" + "where:\n" + " l - Display all suites and their tests\n" + " b - Specify device's PCI bus id to run tests\n" + " d - Specify device's PCI device id to run tests (optional)\n" + " p - Display information of AMDGPU devices in system\n" + " h - Display this help\n"; /** Specified options strings for getopt */ -static const char options[] = "hls:t:"; +static const char options[] = "hlps:t:b:d:"; /* Open AMD devices. * Return the number of AMD device openned. @@ -203,21 +208,79 @@ static void amdgpu_close_devices() static void amdgpu_print_devices() { int i; - for (i = 0; i < MAX_CARDS_SUPPORTED; i++) - if (drm_amdgpu[i] >=0) { - /** Display version of DRM driver */ - drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]); + drmDevicePtr device; + + /* Open the first AMD devcie to print driver information. */ + if (drm_amdgpu[0] >=0) { + /* Display AMD driver version information.*/ + drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]); + + if (retval == NULL) { + perror("Cannot get version for AMDGPU device"); + return; + } - if (retval == NULL) { - perror("Cannot get version for AMDGPU device"); - exit(EXIT_FAILURE); + printf("Driver name: %s, Date: %s, Description: %s.\n", + retval->name, retval->date, retval->desc); + drmFreeVersion(retval); + } + + /* Display information of AMD devices */ + printf("Devices:\n"); + for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >=0; i++) + if (drmGetDevice2(drm_amdgpu[i], + DRM_DEVICE_GET_PCI_REVISION, + &device) == 0) { + if (device->bustype == DRM_BUS_PCI) { + printf("PCI "); + printf(" domain:%04x", + device->businfo.pci->domain); + printf(" bus:%02x", + device->businfo.pci->bus); + printf(" device:%02x", + device->businfo.pci->dev); + printf(" function:%01x", + device->businfo.pci->func); + printf(" vendor_id:%04x", + device->deviceinfo.pci->vendor_id); + printf(" device_id:%04x", + device->deviceinfo.pci->device_id); + printf(" subvendor_id:%04x", + device->deviceinfo.pci->subvendor_id); + printf(" subdevice_id:%04x", + device->deviceinfo.pci->subdevice_id); + printf(" revision_id:%02x", + device->deviceinfo.pci->revision_id); + printf("\n"); } + drmFreeDevice(&device); + } +} + +/* Find a match AMD device in PCI bus + * Return the index of the device or -1 if not found + */ +static int amdgpu_find_device(uint8_t bus, uint8_t dev) +{ + int i; + drmDevicePtr device; + + for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >=0; i++) + if (drmGetDevice2(drm_amdgpu[i], + DRM_DEVICE_GET_PCI_REVISION, + &device) == 0) { + if (device->bustype == DRM_BUS_PCI) + if (device->businfo.pci->bus == bus && + device->businfo.pci->dev == dev) { + + drmFreeDevice(&device); + return i; + } - printf("AMDGPU device #%d: " - "Name: [%s] : Date [%s] : Description [%s]\n", - i, retval->name, retval->date, retval->desc); - drmFreeVersion(retval); + drmFreeDevice(&device); } + + return -1; } /* The main() function for setting up and running the tests. @@ -230,8 +293,12 @@ int main(int argc, char **argv) int i = 0; int suite_id = -1; /* By default run everything */ int test_id = -1; /* By default run all tests in the suite */ + int pci_bus_id = -1; /* By default PC bus ID is not specified */ + int pci_device_id = 0; /* By default PC device ID is zero */ + int display_devices = 0;/* By default not to display devices' info */ CU_pSuite pSuite = NULL; CU_pTest pTest = NULL; + int test_device_index; for (i = 0; i < MAX_CARDS_SUPPORTED; i++) drm_amdgpu[i] = -1; @@ -250,6 +317,15 @@ int main(int argc, char **argv) case 't': test_id = atoi(optarg); break; + case 'b': + pci_bus_id = atoi(optarg); + break; + case 'd': + pci_device_id = atoi(optarg); + break; + case 'p': + display_devices = 1; + break; case '?': case 'h': fprintf(stderr, usage, argv[0]); @@ -270,7 +346,30 @@ int main(int argc, char **argv) exit(EXIT_FAILURE); } - amdgpu_print_devices(); + if (display_devices) { + amdgpu_print_devices(); + amdgpu_close_devices(); + exit(EXIT_SUCCESS); + } + + if (pci_bus_id > 0) { + /* A device was specified to run the test */ + test_device_index = amdgpu_find_device((uint8_t)pci_bus_id, + (uint8_t)pci_device_id); + + if (test_device_index >= 0) { + /* Most tests run on device of drm_amdgpu[0]. + * Swap the chosen device to drm_amdgpu[0]. + */ + i = drm_amdgpu[0]; + drm_amdgpu[0] = drm_amdgpu[test_device_index]; + drm_amdgpu[test_device_index] = i; + } else { + fprintf(stderr, + "The specified GPU device does not exist.\n"); + exit(EXIT_FAILURE); + } + } /* Initialize test suites to run */ commit 5e0f7c5c65ca6714cd7352d72303ec2cbec35cb5 Author: Alex Xie <Ale...@am...> Date: Tue Jan 24 17:29:50 2017 -0500 amdgpu: verify the tested device Verify the vender ID and driver name. Open all AMDGPU devices. Provide an option to open render node. Tested as root: PASS Tested as non-privileged user: All tests failed as expected v2: Return value in the ene of function amdgpu_open_devices. Check the return value of amdgpu_open_devices. amdgpu_test is not for USB device for the time being. Get the name of node from function drmGetDevices2. Drop the legacy drmAvailable() from the test. Reviewed-by: Emil Velikov <emi...@gm...> Signed-off-by: Alex Xie <Ale...@am...> Signed-off-by: Alex Deucher <ale...@am...> diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c index 71f357c..d2b00d4 100644 --- a/tests/amdgpu/amdgpu_test.c +++ b/tests/amdgpu/amdgpu_test.c @@ -115,6 +115,111 @@ static const char usage[] = "Usage: %s [-hl] [<-s <suite id>> [-t <test id>]]\n" /** Specified options strings for getopt */ static const char options[] = "hls:t:"; +/* Open AMD devices. + * Return the number of AMD device openned. + */ +static int amdgpu_open_devices(int open_render_node) +{ + drmDevicePtr devices[MAX_CARDS_SUPPORTED]; + int ret; + int i; + int drm_node; + int amd_index = 0; + int drm_count; + int fd; + drmVersionPtr version; + + drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED); + + if (drm_count < 0) { + fprintf(stderr, + "drmGetDevices2() returned an error %d\n", + drm_count); + return 0; + } + + for (i = 0; i < drm_count; i++) { + /* If this is not PCI device, skip*/ + if (devices[i]->bustype != DRM_BUS_PCI) + continue; + + /* If this is not AMD GPU vender ID, skip*/ + if (devices[i]->deviceinfo.pci->vendor_id != 0x1002) + continue; + + if (open_render_node) + drm_node = DRM_NODE_RENDER; + else + drm_node = DRM_NODE_PRIMARY; + + fd = -1; + if (devices[i]->available_nodes & 1 << drm_node) + fd = open( + devices[i]->nodes[drm_node], + O_RDWR | O_CLOEXEC); + + /* This node is not available. */ + if (fd < 0) continue; + + version = drmGetVersion(fd); + if (!version) { + fprintf(stderr, + "Warning: Cannot get version for %s." + "Error is %s\n", + devices[i]->nodes[drm_node], + strerror(errno)); + close(fd); + continue; + } + + if (strcmp(version->name, "amdgpu")) { + /* This is not AMDGPU driver, skip.*/ + drmFreeVersion(version); + close(fd); + continue; + } + + drmFreeVersion(version); + + drm_amdgpu[amd_index] = fd; + amd_index++; + } + + drmFreeDevices(devices, drm_count); + return amd_index; +} + +/* Close AMD devices. + */ +static void amdgpu_close_devices() +{ + int i; + for (i = 0; i < MAX_CARDS_SUPPORTED; i++) + if (drm_amdgpu[i] >=0) + close(drm_amdgpu[i]); +} + +/* Print AMD devices information */ +static void amdgpu_print_devices() +{ + int i; + for (i = 0; i < MAX_CARDS_SUPPORTED; i++) + if (drm_amdgpu[i] >=0) { + /** Display version of DRM driver */ + drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]); + + if (retval == NULL) { + perror("Cannot get version for AMDGPU device"); + exit(EXIT_FAILURE); + } + + printf("AMDGPU device #%d: " + "Name: [%s] : Date [%s] : Description [%s]\n", + i, retval->name, retval->date, retval->desc); + drmFreeVersion(retval); + } +} + /* The main() function for setting up and running the tests. * Returns a CUE_SUCCESS on successful running, another * CUnit error code on failure. @@ -128,14 +233,6 @@ int main(int argc, char **argv) CU_pSuite pSuite = NULL; CU_pTest pTest = NULL; - int aval = drmAvailable(); - - if (aval == 0) { - fprintf(stderr, "DRM driver is not available\n"); - exit(EXIT_FAILURE); - } - - for (i = 0; i < MAX_CARDS_SUPPORTED; i++) drm_amdgpu[i] = -1; @@ -163,35 +260,23 @@ int main(int argc, char **argv) } } - /* Try to open all possible radeon connections - * Right now: Open only the 0. - */ - printf("Try to open the card 0..\n"); - drm_amdgpu[0] = open("/dev/dri/card0", O_RDWR | O_CLOEXEC); - - if (drm_amdgpu[0] < 0) { - perror("Cannot open /dev/dri/card0\n"); + if (amdgpu_open_devices(0) <= 0) { + perror("Cannot open AMDGPU device"); exit(EXIT_FAILURE); } - /** Display version of DRM driver */ - drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]); - - if (retval == NULL) { - perror("Could not get information about DRM driver"); + if (drm_amdgpu[0] < 0) { + perror("Cannot open AMDGPU device"); exit(EXIT_FAILURE); } - printf("DRM Driver: Name: [%s] : Date [%s] : Description [%s]\n", - retval->name, retval->date, retval->desc); - - drmFreeVersion(retval); + amdgpu_print_devices(); /* Initialize test suites to run */ /* initialize the CUnit test registry */ if (CUE_SUCCESS != CU_initialize_registry()) { - close(drm_amdgpu[0]); + amdgpu_close_devices(); return CU_get_error(); } @@ -200,7 +285,7 @@ int main(int argc, char **argv) fprintf(stderr, "suite registration failed - %s\n", CU_get_error_msg()); CU_cleanup_registry(); - close(drm_amdgpu[0]); + amdgpu_close_devices(); exit(EXIT_FAILURE); } @@ -222,7 +307,7 @@ int main(int argc, char **argv) fprintf(stderr, "Invalid test id: %d\n", test_id); CU_cleanup_registry(); - close(drm_amdgpu[0]); + amdgpu_close_devices(); exit(EXIT_FAILURE); } } else @@ -231,13 +316,13 @@ int main(int argc, char **argv) fprintf(stderr, "Invalid suite id : %d\n", suite_id); CU_cleanup_registry(); - close(drm_amdgpu[0]); + amdgpu_close_devices(); exit(EXIT_FAILURE); } } else CU_basic_run_tests(); CU_cleanup_registry(); - close(drm_amdgpu[0]); + amdgpu_close_devices(); return CU_get_error(); } |
From: <ic...@ke...> - 2017-01-27 20:01:41
|
include/drm/i915_drm.h | 276 +++++++++++++++++++++++++++++++++++++++++++++-- intel/intel_bufmgr.h | 10 + intel/intel_bufmgr_gem.c | 80 ++++++++++++- 3 files changed, 348 insertions(+), 18 deletions(-) New commits: commit c4b00767a7f3b2d00c7b1bc61e2b4d13f90c10ca Author: Chris Wilson <ch...@ch...> Date: Sat Aug 20 12:38:46 2016 +0100 intel: Support passing of explicit fencing from execbuf Allow the caller to pass in an fd to an array of fences to control serialisation of the execbuf in the kernel and on the GPU, and in return allow creation of a fence fd for signaling the completion (and flushing) of the batch. When the returned fence is signaled, all writes to the buffers inside the batch will be complete and coherent from the cpu, or other consumers. The return fence is a sync_file object and can be passed to other users (such as atomic modesetting, or other drivers). Signed-off-by: Chris Wilson <ch...@ch...> diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h index f43ee47..11579fb 100644 --- a/intel/intel_bufmgr.h +++ b/intel/intel_bufmgr.h @@ -221,6 +221,12 @@ int drm_intel_gem_context_get_id(drm_intel_context *ctx, void drm_intel_gem_context_destroy(drm_intel_context *ctx); int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx, int used, unsigned int flags); +int drm_intel_gem_bo_fence_exec(drm_intel_bo *bo, + drm_intel_context *ctx, + int used, + int in_fence, + int *out_fence, + unsigned int flags); int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd); drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr, diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 554d079..9195f3e 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -2376,6 +2376,7 @@ drm_intel_gem_bo_exec(drm_intel_bo *bo, int used, static int do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx, drm_clip_rect_t *cliprects, int num_cliprects, int DR4, + int in_fence, int *out_fence, unsigned int flags) { drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; @@ -2430,12 +2431,20 @@ do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx, else i915_execbuffer2_set_context_id(execbuf, ctx->ctx_id); execbuf.rsvd2 = 0; + if (in_fence != -1) { + execbuf.rsvd2 = in_fence; + execbuf.flags |= I915_EXEC_FENCE_IN; + } + if (out_fence != NULL) { + *out_fence = -1; + execbuf.flags |= I915_EXEC_FENCE_OUT; + } if (bufmgr_gem->no_exec) goto skip_execution; ret = drmIoctl(bufmgr_gem->fd, - DRM_IOCTL_I915_GEM_EXECBUFFER2, + DRM_IOCTL_I915_GEM_EXECBUFFER2_WR, &execbuf); if (ret != 0) { ret = -errno; @@ -2451,6 +2460,9 @@ do_exec2(drm_intel_bo *bo, int used, drm_intel_context *ctx, } drm_intel_update_buffer_offsets2(bufmgr_gem); + if (ret == 0 && out_fence != NULL) + *out_fence = execbuf.rsvd2 >> 32; + skip_execution: if (bufmgr_gem->bufmgr.debug) drm_intel_gem_dump_validation_list(bufmgr_gem); @@ -2476,7 +2488,7 @@ drm_intel_gem_bo_exec2(drm_intel_bo *bo, int used, int DR4) { return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4, - I915_EXEC_RENDER); + -1, NULL, I915_EXEC_RENDER); } static int @@ -2485,14 +2497,25 @@ drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used, unsigned int flags) { return do_exec2(bo, used, NULL, cliprects, num_cliprects, DR4, - flags); + -1, NULL, flags); } int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx, int used, unsigned int flags) { - return do_exec2(bo, used, ctx, NULL, 0, 0, flags); + return do_exec2(bo, used, ctx, NULL, 0, 0, -1, NULL, flags); +} + +int +drm_intel_gem_bo_fence_exec(drm_intel_bo *bo, + drm_intel_context *ctx, + int used, + int in_fence, + int *out_fence, + unsigned int flags) +{ + return do_exec2(bo, used, ctx, NULL, 0, 0, in_fence, out_fence, flags); } static int commit 1bd35da961312aeb33fc7af586fa0d1f207a2d5f Author: Chris Wilson <ch...@ch...> Date: Sat Aug 20 18:36:42 2016 +0100 intel: Allow the client to control implicit synchronisation The kernel allows implicit synchronisation to be disabled on individual buffers. Use at your own risk. Signed-off-by: Chris Wilson <ch...@ch...> diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h index 85e4ff7..f43ee47 100644 --- a/intel/intel_bufmgr.h +++ b/intel/intel_bufmgr.h @@ -184,6 +184,10 @@ int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo); int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo); int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo); +#define HAVE_DRM_INTEL_GEM_BO_DISABLE_IMPLICIT_SYNC 1 +int drm_intel_bufmgr_gem_can_disable_implicit_sync(drm_intel_bufmgr *bufmgr); +void drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo); + void *drm_intel_gem_bo_map__cpu(drm_intel_bo *bo); void *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo); void *drm_intel_gem_bo_map__wc(drm_intel_bo *bo); diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index c47cb9b..554d079 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -149,6 +149,7 @@ typedef struct _drm_intel_bufmgr_gem { unsigned int bo_reuse : 1; unsigned int no_exec : 1; unsigned int has_vebox : 1; + unsigned int has_exec_async : 1; bool fenced_relocs; struct { @@ -195,6 +196,8 @@ struct _drm_intel_bo_gem { uint32_t swizzle_mode; unsigned long stride; + unsigned long kflags; + time_t free_time; /** Array passed to the DRM containing relocation information. */ @@ -575,12 +578,11 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence) bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count; bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs; bufmgr_gem->exec2_objects[index].alignment = bo->align; - bufmgr_gem->exec2_objects[index].offset = bo_gem->is_softpin ? - bo->offset64 : 0; - bufmgr_gem->exec_bos[index] = bo; - bufmgr_gem->exec2_objects[index].flags = flags; + bufmgr_gem->exec2_objects[index].offset = bo->offset64; + bufmgr_gem->exec2_objects[index].flags = flags | bo_gem->kflags; bufmgr_gem->exec2_objects[index].rsvd1 = 0; bufmgr_gem->exec2_objects[index].rsvd2 = 0; + bufmgr_gem->exec_bos[index] = bo; bufmgr_gem->exec_count++; } @@ -1368,6 +1370,7 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time) for (i = 0; i < bo_gem->softpin_target_count; i++) drm_intel_gem_bo_unreference_locked_timed(bo_gem->softpin_target[i], time); + bo_gem->kflags = 0; bo_gem->reloc_count = 0; bo_gem->used_as_reloc_target = false; bo_gem->softpin_target_count = 0; @@ -2766,6 +2769,40 @@ drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr) } /** + * Disables implicit synchronisation before executing the bo + * + * This will cause rendering corruption unless you correctly manage explicit + * fences for all rendering involving this buffer - including use by others. + * Disabling the implicit serialisation is only required if that serialisation + * is too coarse (for example, you have split the buffer into many + * non-overlapping regions and are sharing the whole buffer between concurrent + * independent command streams). + * + * Note the kernel must advertise support via I915_PARAM_HAS_EXEC_ASYNC, + * which can be checked using drm_intel_bufmgr_can_disable_implicit_sync, + * or subsequent execbufs involving the bo will generate EINVAL. + */ +void +drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + bo_gem->kflags |= EXEC_OBJECT_ASYNC; +} + +/** + * Query whether the kernel supports disabling of its implicit synchronisation + * before execbuf. See drm_intel_gem_bo_disable_implicit_sync() + */ +int +drm_intel_bufmgr_gem_can_disable_implicit_sync(drm_intel_bufmgr *bufmgr) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; + + return bufmgr_gem->has_exec_async; +} + +/** * Enable use of fenced reloc type. * * New code should enable this to avoid unnecessary fence register @@ -3635,6 +3672,10 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); bufmgr_gem->has_relaxed_fencing = ret == 0; + gp.param = I915_PARAM_HAS_EXEC_ASYNC; + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); + bufmgr_gem->has_exec_async = ret == 0; + bufmgr_gem->bufmgr.bo_alloc_userptr = check_bo_alloc_userptr; gp.param = I915_PARAM_HAS_WAIT_TIMEOUT; commit a3d715ee14b29d2680ceaf44955679205795140c Author: Chris Wilson <ch...@ch...> Date: Fri Jan 27 10:39:10 2017 +0000 Import uapi/i915_drm.h from v4.10-rc5-950-g152d5750dda9 To sync with "drm/i915: Support explicit fencing for execbuf" diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index eb611a7..5ebe046 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -29,6 +29,10 @@ #include "drm.h" +#if defined(__cplusplus) +extern "C" { +#endif + /* Please note that modifications to all structs defined here are * subject to backwards-compatibility constraints. */ @@ -58,6 +62,30 @@ #define I915_ERROR_UEVENT "ERROR" #define I915_RESET_UEVENT "RESET" +/* + * MOCS indexes used for GPU surfaces, defining the cacheability of the + * surface data and the coherency for this data wrt. CPU vs. GPU accesses. + */ +enum i915_mocs_table_index { + /* + * Not cached anywhere, coherency between CPU and GPU accesses is + * guaranteed. + */ + I915_MOCS_UNCACHED, + /* + * Cacheability and coherency controlled by the kernel automatically + * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current + * usage of the surface (used for display scanout or not). + */ + I915_MOCS_PTE, + /* + * Cached in all GPU caches available on the platform. + * Coherency between CPU and GPU accesses to the surface is not + * guaranteed without extra synchronization. + */ + I915_MOCS_CACHED, +}; + /* Each region is a minimum of 16k, and there are at most 255 of them. */ #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use @@ -218,6 +246,7 @@ typedef struct _drm_i915_sarea { #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 #define DRM_I915_OVERLAY_ATTRS 0x28 #define DRM_I915_GEM_EXECBUFFER2 0x29 +#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a #define DRM_I915_SET_SPRITE_COLORKEY 0x2b #define DRM_I915_GEM_WAIT 0x2c @@ -230,6 +259,7 @@ typedef struct _drm_i915_sarea { #define DRM_I915_GEM_USERPTR 0x33 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 +#define DRM_I915_PERF_OPEN 0x36 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) @@ -251,6 +281,7 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) +#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) @@ -283,6 +314,7 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) +#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. @@ -357,8 +389,28 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_HAS_GPU_RESET 35 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 #define I915_PARAM_HAS_EXEC_SOFTPIN 37 -#define I915_PARAM_HAS_POOLED_EU 38 -#define I915_PARAM_MIN_EU_IN_POOL 39 +#define I915_PARAM_HAS_POOLED_EU 38 +#define I915_PARAM_MIN_EU_IN_POOL 39 +#define I915_PARAM_MMAP_GTT_VERSION 40 + +/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution + * priorities and the driver will attempt to execute batches in priority order. + */ +#define I915_PARAM_HAS_SCHEDULER 41 +#define I915_PARAM_HUC_STATUS 42 + +/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of + * synchronisation with implicit fencing on individual objects. + * See EXEC_OBJECT_ASYNC. + */ +#define I915_PARAM_HAS_EXEC_ASYNC 43 + +/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support - + * both being able to pass in a sync_file fd to wait upon before executing, + * and being able to return a new sync_file fd that is signaled when the + * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT. + */ +#define I915_PARAM_HAS_EXEC_FENCE 44 typedef struct drm_i915_getparam { __s32 param; @@ -694,15 +746,41 @@ struct drm_i915_gem_exec_object2 { */ __u64 offset; -#define EXEC_OBJECT_NEEDS_FENCE (1<<0) -#define EXEC_OBJECT_NEEDS_GTT (1<<1) -#define EXEC_OBJECT_WRITE (1<<2) +#define EXEC_OBJECT_NEEDS_FENCE (1<<0) +#define EXEC_OBJECT_NEEDS_GTT (1<<1) +#define EXEC_OBJECT_WRITE (1<<2) #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) -#define EXEC_OBJECT_PINNED (1<<4) -#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1) +#define EXEC_OBJECT_PINNED (1<<4) +#define EXEC_OBJECT_PAD_TO_SIZE (1<<5) +/* The kernel implicitly tracks GPU activity on all GEM objects, and + * synchronises operations with outstanding rendering. This includes + * rendering on other devices if exported via dma-buf. However, sometimes + * this tracking is too coarse and the user knows better. For example, + * if the object is split into non-overlapping ranges shared between different + * clients or engines (i.e. suballocating objects), the implicit tracking + * by kernel assumes that each operation affects the whole object rather + * than an individual range, causing needless synchronisation between clients. + * The kernel will also forgo any CPU cache flushes prior to rendering from + * the object as the client is expected to be also handling such domain + * tracking. + * + * The kernel maintains the implicit tracking in order to manage resources + * used by the GPU - this flag only disables the synchronisation prior to + * rendering with this object in this execbuf. + * + * Opting out of implicit synhronisation requires the user to do its own + * explicit tracking to avoid rendering corruption. See, for example, + * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously. + */ +#define EXEC_OBJECT_ASYNC (1<<6) +/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ +#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_ASYNC<<1) __u64 flags; - __u64 rsvd1; + union { + __u64 rsvd1; + __u64 pad_to_size; + }; __u64 rsvd2; }; @@ -786,7 +864,32 @@ struct drm_i915_gem_execbuffer2 { */ #define I915_EXEC_RESOURCE_STREAMER (1<<15) -#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1) +/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent + * a sync_file fd to wait upon (in a nonblocking manner) prior to executing + * the batch. + * + * Returns -EINVAL if the sync_file fd cannot be found. + */ +#define I915_EXEC_FENCE_IN (1<<16) + +/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd + * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given + * to the caller, and it should be close() after use. (The fd is a regular + * file descriptor and will be cleaned up on process termination. It holds + * a reference to the request, but nothing else.) + * + * The sync_file fd can be combined with other sync_file and passed either + * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip + * will only occur after this request completes), or to other devices. + * + * Using I915_EXEC_FENCE_OUT requires use of + * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written + * back to userspace. Failure to do so will cause the out-fence to always + * be reported as zero, and the real fence fd to be leaked. + */ +#define I915_EXEC_FENCE_OUT (1<<17) + +#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_OUT<<1)) #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) #define i915_execbuffer2_set_context_id(eb2, context) \ @@ -822,7 +925,16 @@ struct drm_i915_gem_busy { * having flushed any pending activity), and a non-zero return that * the object is still in-flight on the GPU. (The GPU has not yet * signaled completion for all pending requests that reference the - * object.) + * object.) An object is guaranteed to become idle eventually (so + * long as no new GPU commands are executed upon it). Due to the + * asynchronous nature of the hardware, an object reported + * as busy may become idle before the ioctl is completed. + * + * Furthermore, if the object is busy, which engine is busy is only + * provided as a guide. There are race conditions which prevent the + * report of which engines are busy from being always accurate. + * However, the converse is not true. If the object is idle, the + * result of the ioctl, that all engines are idle, is accurate. * * The returned dword is split into two fields to indicate both * the engines on which the object is being read, and the @@ -845,6 +957,11 @@ struct drm_i915_gem_busy { * execution engines, e.g. multiple media engines, which are * mapped to the same identifier in the EXECBUFFER2 ioctl and * so are not separately reported for busyness. + * + * Caveat emptor: + * Only the boolean result of this query is reliable; that is whether + * the object is idle or busy. The report of which engines are busy + * should be only used as a heuristic. */ __u32 busy; }; @@ -893,6 +1010,7 @@ struct drm_i915_gem_caching { #define I915_TILING_NONE 0 #define I915_TILING_X 1 #define I915_TILING_Y 2 +#define I915_TILING_LAST I915_TILING_Y #define I915_BIT_6_SWIZZLE_NONE 0 #define I915_BIT_6_SWIZZLE_9 1 @@ -1169,7 +1287,145 @@ struct drm_i915_gem_context_param { #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 +#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 +#define I915_CONTEXT_PARAM_BANNABLE 0x5 __u64 value; }; +enum drm_i915_oa_format { + I915_OA_FORMAT_A13 = 1, + I915_OA_FORMAT_A29, + I915_OA_FORMAT_A13_B8_C8, + I915_OA_FORMAT_B4_C8, + I915_OA_FORMAT_A45_B8_C8, + I915_OA_FORMAT_B4_C8_A16, + I915_OA_FORMAT_C4_B8, + + I915_OA_FORMAT_MAX /* non-ABI */ +}; + +enum drm_i915_perf_property_id { + /** + * Open the stream for a specific context handle (as used with + * execbuffer2). A stream opened for a specific context this way + * won't typically require root privileges. + */ + DRM_I915_PERF_PROP_CTX_HANDLE = 1, + + /** + * A value of 1 requests the inclusion of raw OA unit reports as + * part of stream samples. + */ + DRM_I915_PERF_PROP_SAMPLE_OA, + + /** + * The value specifies which set of OA unit metrics should be + * be configured, defining the contents of any OA unit reports. + */ + DRM_I915_PERF_PROP_OA_METRICS_SET, + + /** + * The value specifies the size and layout of OA unit reports. + */ + DRM_I915_PERF_PROP_OA_FORMAT, + + /** + * Specifying this property implicitly requests periodic OA unit + * sampling and (at least on Haswell) the sampling frequency is derived + * from this exponent as follows: + * + * 80ns * 2^(period_exponent + 1) + */ + DRM_I915_PERF_PROP_OA_EXPONENT, + + DRM_I915_PERF_PROP_MAX /* non-ABI */ +}; + +struct drm_i915_perf_open_param { + __u32 flags; +#define I915_PERF_FLAG_FD_CLOEXEC (1<<0) +#define I915_PERF_FLAG_FD_NONBLOCK (1<<1) +#define I915_PERF_FLAG_DISABLED (1<<2) + + /** The number of u64 (id, value) pairs */ + __u32 num_properties; + + /** + * Pointer to array of u64 (id, value) pairs configuring the stream + * to open. + */ + __u64 properties_ptr; +}; + +/** + * Enable data capture for a stream that was either opened in a disabled state + * via I915_PERF_FLAG_DISABLED or was later disabled via + * I915_PERF_IOCTL_DISABLE. + * + * It is intended to be cheaper to disable and enable a stream than it may be + * to close and re-open a stream with the same configuration. + * + * It's undefined whether any pending data for the stream will be lost. + */ +#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) + +/** + * Disable data capture for a stream. + * + * It is an error to try and read a stream that is disabled. + */ +#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) + +/** + * Common to all i915 perf records + */ +struct drm_i915_perf_record_header { + __u32 type; + __u16 pad; + __u16 size; +}; + +enum drm_i915_perf_record_type { + + /** + * Samples are the work horse record type whose contents are extensible + * and defined when opening an i915 perf stream based on the given + * properties. + * + * Boolean properties following the naming convention + * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in + * every sample. + * + * The order of these sample properties given by userspace has no + * affect on the ordering of data within a sample. The order is + * documented here. + * + * struct { + * struct drm_i915_perf_record_header header; + * + * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA + * }; + */ + DRM_I915_PERF_RECORD_SAMPLE = 1, + + /* + * Indicates that one or more OA reports were not written by the + * hardware. This can happen for example if an MI_REPORT_PERF_COUNT + * command collides with periodic sampling - which would be more likely + * at higher sampling frequencies. + */ + DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, + + /** + * An error occurred that resulted in all pending OA reports being lost. + */ + DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, + + DRM_I915_PERF_RECORD_MAX /* non-ABI */ +}; + +#if defined(__cplusplus) +} +#endif + #endif /* _I915_DRM_H_ */ |
From: <ai...@ke...> - 2017-01-28 01:14:56
|
intel/intel-symbol-check | 4 ++++ 1 file changed, 4 insertions(+) New commits: commit d4b8344363b4e0f0e831e5722b6df5cc0bb08df8 Author: Chad Versace <cha...@ch...> Date: Fri Jan 27 12:18:00 2017 -0800 Bump version for 2.4.75 release For Intel explicit fencing. Signed-off-by: Chad Versace <cha...@ch...> diff --git a/configure.ac b/configure.ac index 39973b6..8e59332 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.74], + [2.4.75], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) commit 0ad0c12fd3e04eaabec313432436fca462ca69ac Author: Dave Airlie <ai...@re...> Date: Sat Jan 28 11:13:52 2017 +1000 intel: fix make distcheck Signed-off-by: Dave Airlie <ai...@re...> diff --git a/intel/intel-symbol-check b/intel/intel-symbol-check index 038c982..2aa2d81 100755 --- a/intel/intel-symbol-check +++ b/intel/intel-symbol-check @@ -50,6 +50,7 @@ drm_intel_bufmgr_fake_init drm_intel_bufmgr_fake_set_exec_callback drm_intel_bufmgr_fake_set_fence_callback drm_intel_bufmgr_fake_set_last_dispatch +drm_intel_bufmgr_gem_can_disable_implicit_sync drm_intel_bufmgr_gem_enable_fenced_relocs drm_intel_bufmgr_gem_enable_reuse drm_intel_bufmgr_gem_get_devid @@ -69,6 +70,9 @@ drm_intel_decode_set_output_file drm_intel_gem_bo_aub_dump_bmp drm_intel_gem_bo_clear_relocs drm_intel_gem_bo_context_exec +drm_intel_gem_bo_disable_implicit_sync +drm_intel_gem_bo_enable_implicit_sync +drm_intel_gem_bo_fence_exec drm_intel_gem_bo_get_reloc_count drm_intel_gem_bo_map__cpu drm_intel_gem_bo_map__gtt commit ab5a9635563e43f8f948e4a29ea531e44ac9e79a Author: Dave Airlie <ai...@re...> Date: Sat Jan 28 11:13:40 2017 +1000 Revert "Bump version for 2.4.75 release" This reverts commit 736970c49beb9de7ab549f076069d52f4e7bc6f2. diff --git a/configure.ac b/configure.ac index 8e59332..39973b6 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.75], + [2.4.74], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) |
From: <ag...@ke...> - 2017-02-02 20:24:35
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amdgpu/amdgpu_device.c | 24 +++++++----------------- amdgpu/amdgpu_internal.h | 4 ++-- amdgpu/amdgpu_vamgr.c | 6 +++--- 3 files changed, 12 insertions(+), 22 deletions(-) New commits: commit fe7cb34eda1855ac9770bc9f3e582897000e41b0 Author: Alex Xie <Ale...@am...> Date: Sat Jan 28 21:50:44 2017 +0200 amdgpu: vamgr can be a struct instead of a pointer vamgr is an integral part of amdgpu_device. We don't need to calloc and free it. This can save CPU time, reduce heap fragmentation. Reviewed-by: Edward O'Callaghan <fun...@fo...> Reviewed-by: Emil Velikov <emi...@gm...> Signed-off-by: Alex Xie <Ale...@am...> Reviewed-by: Christian König <chr...@am...> [Grazvydas Ignotas: rebase, correct a typo in commit message] Signed-off-by: Alex Deucher <ale...@am...> diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index 11714e4..f473d2d 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -132,8 +132,7 @@ static int amdgpu_get_auth(int fd, int *auth) static void amdgpu_device_free_internal(amdgpu_device_handle dev) { amdgpu_vamgr_deinit(&dev->vamgr_32); - amdgpu_vamgr_deinit(dev->vamgr); - free(dev->vamgr); + amdgpu_vamgr_deinit(&dev->vamgr); util_hash_table_destroy(dev->bo_flink_names); util_hash_table_destroy(dev->bo_handles); pthread_mutex_destroy(&dev->bo_table_mutex); @@ -254,16 +253,12 @@ int amdgpu_device_initialize(int fd, if (r) goto cleanup; - dev->vamgr = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); - if (dev->vamgr == NULL) - goto cleanup; - - amdgpu_vamgr_init(dev->vamgr, dev->dev_info.virtual_address_offset, + amdgpu_vamgr_init(&dev->vamgr, dev->dev_info.virtual_address_offset, dev->dev_info.virtual_address_max, dev->dev_info.virtual_address_alignment); max = MIN2(dev->dev_info.virtual_address_max, 0xffffffff); - start = amdgpu_vamgr_find_va(dev->vamgr, + start = amdgpu_vamgr_find_va(&dev->vamgr, max - dev->dev_info.virtual_address_offset, dev->dev_info.virtual_address_alignment, 0); if (start > 0xffffffff) @@ -282,10 +277,9 @@ int amdgpu_device_initialize(int fd, free_va: r = -ENOMEM; - amdgpu_vamgr_free_va(dev->vamgr, start, + amdgpu_vamgr_free_va(&dev->vamgr, start, max - dev->dev_info.virtual_address_offset); - amdgpu_vamgr_deinit(dev->vamgr); - free(dev->vamgr); + amdgpu_vamgr_deinit(&dev->vamgr); cleanup: if (dev->fd >= 0) diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 7e237ac..cf119a5 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -85,7 +85,7 @@ struct amdgpu_device { struct drm_amdgpu_info_device dev_info; struct amdgpu_gpu_info info; /** The global VA manager for the whole virtual address space */ - struct amdgpu_bo_va_mgr *vamgr; + struct amdgpu_bo_va_mgr vamgr; /** The VA manager for the 32bit address space */ struct amdgpu_bo_va_mgr vamgr_32; }; diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index 4dc4253..2b1388e 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -238,7 +238,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, if (flags & AMDGPU_VA_RANGE_32_BIT) vamgr = &dev->vamgr_32; else - vamgr = dev->vamgr; + vamgr = &dev->vamgr; va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); size = ALIGN(size, vamgr->va_alignment); commit 067e9a1d47a8373b3145481a70fec84ce8e76441 Author: Alex Xie <Ale...@am...> Date: Sat Jan 28 21:50:36 2017 +0200 amdgpu: vamgr_32 can be a struct instead of a pointer vamgr_32 is an integral part of amdgpu_device. We don't need to calloc and free it. This can save CPU time, reduce heap fragmentation. Reviewed-by: Edward O'Callaghan <fun...@fo...> Reviewed-by: Emil Velikov <emi...@gm...> Signed-off-by: Alex Xie <Ale...@am...> Reviewed-by: Christian König <chr...@am...> [Grazvydas Ignotas: rebase, correct a typo in commit message] Signed-off-by: Alex Deucher <ale...@am...> diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index cad7133..11714e4 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -131,8 +131,7 @@ static int amdgpu_get_auth(int fd, int *auth) static void amdgpu_device_free_internal(amdgpu_device_handle dev) { - amdgpu_vamgr_deinit(dev->vamgr_32); - free(dev->vamgr_32); + amdgpu_vamgr_deinit(&dev->vamgr_32); amdgpu_vamgr_deinit(dev->vamgr); free(dev->vamgr); util_hash_table_destroy(dev->bo_flink_names); @@ -270,10 +269,7 @@ int amdgpu_device_initialize(int fd, if (start > 0xffffffff) goto free_va; /* shouldn't get here */ - dev->vamgr_32 = calloc(1, sizeof(struct amdgpu_bo_va_mgr)); - if (dev->vamgr_32 == NULL) - goto free_va; - amdgpu_vamgr_init(dev->vamgr_32, start, max, + amdgpu_vamgr_init(&dev->vamgr_32, start, max, dev->dev_info.virtual_address_alignment); *major_version = dev->major_version; diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 4f039b6..7e237ac 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -87,7 +87,7 @@ struct amdgpu_device { /** The global VA manager for the whole virtual address space */ struct amdgpu_bo_va_mgr *vamgr; /** The VA manager for the 32bit address space */ - struct amdgpu_bo_va_mgr *vamgr_32; + struct amdgpu_bo_va_mgr vamgr_32; }; struct amdgpu_bo { diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c index 8a707cb..4dc4253 100644 --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -236,7 +236,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, struct amdgpu_bo_va_mgr *vamgr; if (flags & AMDGPU_VA_RANGE_32_BIT) - vamgr = dev->vamgr_32; + vamgr = &dev->vamgr_32; else vamgr = dev->vamgr; @@ -249,7 +249,7 @@ int amdgpu_va_range_alloc(amdgpu_device_handle dev, if (!(flags & AMDGPU_VA_RANGE_32_BIT) && (*va_base_allocated == AMDGPU_INVALID_VA_ADDRESS)) { /* fallback to 32bit address */ - vamgr = dev->vamgr_32; + vamgr = &dev->vamgr_32; *va_base_allocated = amdgpu_vamgr_find_va(vamgr, size, va_base_alignment, va_base_required); } commit 7a03cdf6a703911d2a8e8ab0781f1e6b88412329 Author: Alex Xie <Ale...@am...> Date: Sat Jan 28 21:49:30 2017 +0200 amdgpu: Free/uninit vamgr_32 in theoretically correct order vamgr_32 is a region inside general VAM range. It is better to free and deinitialize it before general VAM range. Reviewed-by: Edward O'Callaghan <fun...@fo...> Reviewed-by: Emil Velikov <emi...@gm...> Signed-off-by: Alex Xie <Ale...@am...> Reviewed-by: Christian König <chr...@am...> Signed-off-by: Alex Deucher <ale...@am...> diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c index f4ede03..cad7133 100644 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -131,10 +131,10 @@ static int amdgpu_get_auth(int fd, int *auth) static void amdgpu_device_free_internal(amdgpu_device_handle dev) { - amdgpu_vamgr_deinit(dev->vamgr); - free(dev->vamgr); amdgpu_vamgr_deinit(dev->vamgr_32); free(dev->vamgr_32); + amdgpu_vamgr_deinit(dev->vamgr); + free(dev->vamgr); util_hash_table_destroy(dev->bo_flink_names); util_hash_table_destroy(dev->bo_handles); pthread_mutex_destroy(&dev->bo_table_mutex); |
From: <nh...@ke...> - 2017-04-03 16:33:24
|
amdgpu/amdgpu_bo.c | 3 +- include/drm/README | 4 --- include/drm/amdgpu_drm.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 57 insertions(+), 6 deletions(-) New commits: commit eead59110771e617096d554ffd92360e023174e1 Author: Junwei Zhang <Jer...@am...> Date: Wed Mar 22 11:14:00 2017 +0800 amdgpu: add REPLACE and CLEAR checking for VA op (v2) v2: fix indent Signed-off-by: Junwei Zhang <Jer...@am...> Reviewed-by: Nicolai Hähnle <nic...@am...> Reviewed-by: Christian König <chr...@am...> Reviewed-by: Marek Olšák <mar...@am...> Acked-by: Emil Velikov <emi...@co...> diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index f725bfd8..9adfffa2 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -703,7 +703,8 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, struct drm_amdgpu_gem_va va; int r; - if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP) + if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP && + ops != AMDGPU_VA_OP_REPLACE && ops != AMDGPU_VA_OP_CLEAR) return -EINVAL; memset(&va, 0, sizeof(va)); commit 0a4626fead67f228bd7fad3c8b00812ab2613ec8 Author: Nicolai Hähnle <nic...@am...> Date: Mon Apr 3 10:23:03 2017 +0200 headers: the uint*_t vs. __u* discrepancy in amdgpu_drm is fixed This was already done in commit 3dc002df3e5 ("amdgpu: sync amdgpu_drm.h with kernel 4.11-rc2"), now update the README accordingly. Signed-off-by: Nicolai Hähnle <nic...@am...> Reviewed-by: Marek Olšák <mar...@am...> Acked-by: Emil Velikov <emi...@co...> diff --git a/include/drm/README b/include/drm/README index f3cdf5da..870b0b5b 100644 --- a/include/drm/README +++ b/include/drm/README @@ -96,10 +96,6 @@ Status: ? Promote to fixed size ints, which match the current (32bit) ones. -amdgpu_drm.h - - Using the stdint.h uint*_t over the respective __u* ones -Status: Trivial. - drm_mode.h - Missing DPI encode/connector pair. Status: Trivial. commit f104148e40d6285a04698f0fa5f4ef76383bee6f Author: Nicolai Hähnle <nic...@am...> Date: Mon Apr 3 10:22:59 2017 +0200 headers: sync amdgpu_drm.h from airlied/drm-next Changes include: PRT and preemption flags, sensor info, and some more changes for Vega10. Generated using make headers_install from airlied/drm-next commit 320d8c3d38739fa8e31a076b86cbdafcf8897d5e. Signed-off-by: Nicolai Hähnle <nic...@am...> Reviewed-by: Marek Olšák <mar...@am...> Acked-by: Emil Velikov <emi...@co...> diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index fa56499f..516a9f28 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -232,6 +232,7 @@ struct drm_amdgpu_gem_userptr { #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f +/* Set/Get helpers for tiling flags. */ #define AMDGPU_TILING_SET(field, value) \ (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) #define AMDGPU_TILING_GET(value, field) \ @@ -355,6 +356,8 @@ struct drm_amdgpu_gem_op { #define AMDGPU_VA_OP_MAP 1 #define AMDGPU_VA_OP_UNMAP 2 +#define AMDGPU_VA_OP_CLEAR 3 +#define AMDGPU_VA_OP_REPLACE 4 /* Delay the page table update till the next CS */ #define AMDGPU_VM_DELAY_UPDATE (1 << 0) @@ -366,6 +369,20 @@ struct drm_amdgpu_gem_op { #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) /* executable mapping, new for VI */ #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) +/* partially resident texture */ +#define AMDGPU_VM_PAGE_PRT (1 << 4) +/* MTYPE flags use bit 5 to 8 */ +#define AMDGPU_VM_MTYPE_MASK (0xf << 5) +/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ +#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) +/* Use NC MTYPE instead of default MTYPE */ +#define AMDGPU_VM_MTYPE_NC (1 << 5) +/* Use WC MTYPE instead of default MTYPE */ +#define AMDGPU_VM_MTYPE_WC (2 << 5) +/* Use CC MTYPE instead of default MTYPE */ +#define AMDGPU_VM_MTYPE_CC (3 << 5) +/* Use UC MTYPE instead of default MTYPE */ +#define AMDGPU_VM_MTYPE_UC (4 << 5) struct drm_amdgpu_gem_va { /** GEM object handle */ @@ -428,9 +445,12 @@ union drm_amdgpu_cs { /* This IB should be submitted to CE */ #define AMDGPU_IB_FLAG_CE (1<<0) -/* CE Preamble */ +/* Preamble flag, which means the IB could be dropped if no context switch */ #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) +/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ +#define AMDGPU_IB_FLAG_PREEMPT (1<<2) + struct drm_amdgpu_cs_chunk_ib { __u32 _pad; /** AMDGPU_IB_FLAG_* */ @@ -506,6 +526,10 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_FW_SMC 0x0a /* Subquery id: Query SDMA firmware version */ #define AMDGPU_INFO_FW_SDMA 0x0b + /* Subquery id: Query PSP SOS firmware version */ + #define AMDGPU_INFO_FW_SOS 0x0c + /* Subquery id: Query PSP ASD firmware version */ + #define AMDGPU_INFO_FW_ASD 0x0d /* number of bytes moved for TTM migration */ #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f /* the used VRAM size */ @@ -536,6 +560,22 @@ struct drm_amdgpu_cs_chunk_data { #define AMDGPU_INFO_VBIOS_IMAGE 0x2 /* Query UVD handles */ #define AMDGPU_INFO_NUM_HANDLES 0x1C +/* Query sensor related information */ +#define AMDGPU_INFO_SENSOR 0x1D + /* Subquery id: Query GPU shader clock */ + #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 + /* Subquery id: Query GPU memory clock */ + #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 + /* Subquery id: Query GPU temperature */ + #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 + /* Subquery id: Query GPU load */ + #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 + /* Subquery id: Query average GPU power */ + #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 + /* Subquery id: Query northbridge voltage */ + #define AMDGPU_INFO_SENSOR_VDDNB 0x6 + /* Subquery id: Query graphics voltage */ + #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff @@ -599,6 +639,10 @@ struct drm_amdgpu_info { __u32 type; __u32 offset; } vbios_info; + + struct { + __u32 type; + } sensor_info; }; }; @@ -710,6 +754,16 @@ struct drm_amdgpu_info_device { __u32 vram_bit_width; /* vce harvesting instance */ __u32 vce_harvest_config; + /* gfx double offchip LDS buffers */ + __u32 gc_double_offchip_lds_buf; + /* NGG Primitive Buffer */ + __u64 prim_buf_gpu_addr; + /* NGG Position Buffer */ + __u64 pos_buf_gpu_addr; + /* NGG Control Sideband */ + __u64 cntl_sb_buf_gpu_addr; + /* NGG Parameter Cache */ + __u64 param_buf_gpu_addr; }; struct drm_amdgpu_info_hw_ip { |