From: <an...@ke...> - 2008-12-23 00:20:09
|
linux-core/Makefile | 9 ------- linux-core/Makefile.kernel | 6 ----- shared-core/i915_drm.h | 54 ++++++++++++++++++++++++++++++++------------- 3 files changed, 40 insertions(+), 29 deletions(-) New commits: commit dfd7fdafd8a2bad0d63ced4a969b6278c221c000 Author: Eric Anholt <er...@an...> Date: Wed Dec 17 13:55:53 2008 -0800 intel: Rename plane[AB]* back to pipe[AB]*. The values are really going to continue meaning pipe, not plane, and that's what they're called in the kernel copy of the header. Userland hasn't ever made the switch to pipe!=plane, since userland checks are based on DRM version, which is still stuck at 1.6. However, Mesa did start using plane[AB] names, so provide a compat define. diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h index 628f7f8..04ab4cf 100644 --- a/shared-core/i915_drm.h +++ b/shared-core/i915_drm.h @@ -111,14 +111,25 @@ typedef struct drm_i915_sarea { unsigned int rotated_tiled; unsigned int rotated2_tiled; - int planeA_x; - int planeA_y; - int planeA_w; - int planeA_h; - int planeB_x; - int planeB_y; - int planeB_w; - int planeB_h; + /* compat defines for the period of time when pipeA_* got renamed + * to planeA_*. They mean pipe, really. + */ +#define planeA_x pipeA_x +#define planeA_y pipeA_y +#define planeA_w pipeA_w +#define planeA_h pipeA_h +#define planeB_x pipeB_x +#define planeB_y pipeB_y +#define planeB_w pipeB_w +#define planeB_h pipeB_h + int pipeA_x; + int pipeA_y; + int pipeA_w; + int pipeA_h; + int pipeB_x; + int pipeB_y; + int pipeB_w; + int pipeB_h; /* Triple buffering */ drm_handle_t third_handle; commit 28771e06dfe45027be6618f87335c19e8e88e3f6 Author: Eric Anholt <er...@an...> Date: Wed Dec 17 13:47:59 2008 -0800 intel: Remove linux build of i915 DRM, as it's unmaintained and a user trap. The code's in the linux kernel. diff --git a/linux-core/Makefile b/linux-core/Makefile index 157664e..5235721 100644 --- a/linux-core/Makefile +++ b/linux-core/Makefile @@ -63,7 +63,7 @@ MODULE_LIST := drm.o tdfx.o r128.o radeon.o mga.o sis.o savage.o via.o \ # Modules only for ix86 architectures ifneq (,$(findstring 86,$(MACHINE))) ARCHX86 := 1 -MODULE_LIST += i810.o i915.o +MODULE_LIST += i810.o endif ifneq (,$(findstring sparc64,$(MACHINE))) @@ -281,7 +281,6 @@ CONFIG_DRM_MGA := n CONFIG_DRM_I810 := n CONFIG_DRM_R128 := n CONFIG_DRM_RADEON := n -CONFIG_DRM_I915 := n CONFIG_DRM_SIS := n CONFIG_DRM_FFB := n CONFIG_DRM_SAVAGE := n @@ -335,11 +334,6 @@ endif ifneq (,$(findstring i810,$(DRM_MODULES))) CONFIG_DRM_I810 := m endif -ifneq (,$(findstring i915,$(DRM_MODULES))) -ifeq ($(OS_HAS_GEM), 1) -CONFIG_DRM_I915 := m -endif -endif GIT_REVISION := $(shell cd "$(DRMSRCDIR)" && git describe --abbrev=17) ifneq ($(GIT_REVISION),) @@ -354,7 +348,6 @@ $(tdfx-objs): $(TDFXHEADERS) $(r128-objs): $(R128HEADERS) $(mga-objs): $(MGAHEADERS) $(i810-objs): $(I810HEADERS) -$(i915-objs): $(I915HEADERS) $(radeon-objs): $(RADEONHEADERS) $(sis-objs): $(SISHEADERS) $(ffb-objs): $(FFBHEADERS) diff --git a/linux-core/Makefile.kernel b/linux-core/Makefile.kernel index e5af2ec..1d577a7 100644 --- a/linux-core/Makefile.kernel +++ b/linux-core/Makefile.kernel @@ -19,10 +19,6 @@ tdfx-objs := tdfx_drv.o r128-objs := r128_drv.o r128_cce.o r128_state.o r128_irq.o mga-objs := mga_drv.o mga_dma.o mga_state.o mga_warp.o mga_irq.o i810-objs := i810_drv.o i810_dma.o -i915-objs := i915_drv.o i915_dma.o i915_irq.o i915_mem.o i915_fence.o \ - i915_buffer.o i915_compat.o i915_execbuf.o i915_suspend.o \ - i915_opregion.o \ - i915_gem.o i915_gem_debug.o i915_gem_proc.o i915_gem_tiling.o nouveau-objs := nouveau_drv.o nouveau_state.o nouveau_fifo.o nouveau_mem.o \ nouveau_object.o nouveau_irq.o nouveau_notifier.o nouveau_swmthd.o \ nouveau_sgdma.o nouveau_dma.o nouveau_bo.o nouveau_fence.o \ @@ -49,7 +45,6 @@ drm-objs += drm_ioc32.o radeon-objs += radeon_ioc32.o mga-objs += mga_ioc32.o r128-objs += r128_ioc32.o -i915-objs += i915_ioc32.o nouveau-objs += nouveau_ioc32.o xgi-objs += xgi_ioc32.o endif @@ -60,7 +55,6 @@ obj-$(CONFIG_DRM_R128) += r128.o obj-$(CONFIG_DRM_RADEON)+= radeon.o obj-$(CONFIG_DRM_MGA) += mga.o obj-$(CONFIG_DRM_I810) += i810.o -obj-$(CONFIG_DRM_I915) += i915.o obj-$(CONFIG_DRM_SIS) += sis.o obj-$(CONFIG_DRM_FFB) += ffb.o obj-$(CONFIG_DRM_SAVAGE)+= savage.o commit d221e00105477be824ff8878ba3c06b77efff84f Author: Eric Anholt <er...@an...> Date: Wed Dec 17 13:45:01 2008 -0800 intel: Sync GEM ioctl comments for easier diffing against the kernel. diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h index 976ff18..628f7f8 100644 --- a/shared-core/i915_drm.h +++ b/shared-core/i915_drm.h @@ -469,8 +469,12 @@ struct drm_i915_gem_pread { uint64_t offset; /** Length of data to read */ uint64_t size; - /** Pointer to write the data into. */ - uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */ + /** + * Pointer to write the data into. + * + * This is a fixed-size type for 32/64 compatibility. + */ + uint64_t data_ptr; }; struct drm_i915_gem_pwrite { @@ -481,8 +485,12 @@ struct drm_i915_gem_pwrite { uint64_t offset; /** Length of data to write */ uint64_t size; - /** Pointer to read the data from. */ - uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */ + /** + * Pointer to read the data from. + * + * This is a fixed-size type for 32/64 compatibility. + */ + uint64_t data_ptr; }; struct drm_i915_gem_mmap { @@ -497,8 +505,12 @@ struct drm_i915_gem_mmap { * The value will be page-aligned. */ uint64_t size; - /** Returned pointer the data was mapped at */ - uint64_t addr_ptr; /* void *, but pointers are not 32/64 compatible */ + /** + * Returned pointer the data was mapped at. + * + * This is a fixed-size type for 32/64 compatibility. + */ + uint64_t addr_ptr; }; struct drm_i915_gem_mmap_gtt { @@ -643,7 +655,8 @@ struct drm_i915_gem_execbuffer { uint32_t DR1; uint32_t DR4; uint32_t num_cliprects; - uint64_t cliprects_ptr; /* struct drm_clip_rect *cliprects */ + /** This is a struct drm_clip_rect *cliprects */ + uint64_t cliprects_ptr; }; struct drm_i915_gem_pin { |
From: <an...@ke...> - 2009-01-28 01:25:01
|
libdrm/intel/Makefile.am | 1 libdrm/intel/intel_bufmgr_gem.c | 77 +++++++++++++++++++++++++++++++++++++++- libdrm/intel/intel_chipset.h | 71 ++++++++++++++++++++++++++++++++++++ shared-core/i915_drm.h | 2 + 4 files changed, 150 insertions(+), 1 deletion(-) New commits: commit cbdd6272c04f487c8a63b595829d2d551e2b58f8 Author: Eric Anholt <er...@an...> Date: Tue Jan 27 17:16:11 2009 -0800 intel: don't count fences on 965 and later, as they don't use them. diff --git a/libdrm/intel/Makefile.am b/libdrm/intel/Makefile.am index 5e3dee0..c7526f6 100644 --- a/libdrm/intel/Makefile.am +++ b/libdrm/intel/Makefile.am @@ -39,6 +39,7 @@ libdrm_intel_la_SOURCES = \ intel_bufmgr_priv.h \ intel_bufmgr_fake.c \ intel_bufmgr_gem.c \ + intel_chipset.h \ mm.c \ mm.h diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c index 765d903..f578a67 100644 --- a/libdrm/intel/intel_bufmgr_gem.c +++ b/libdrm/intel/intel_bufmgr_gem.c @@ -54,6 +54,7 @@ #include "errno.h" #include "intel_bufmgr.h" #include "intel_bufmgr_priv.h" +#include "intel_chipset.h" #include "string.h" #include "i915_drm.h" @@ -100,6 +101,7 @@ typedef struct _drm_intel_bufmgr_gem { uint64_t gtt_size; int available_fences; + int pci_device; } drm_intel_bufmgr_gem; struct _drm_intel_bo_gem { @@ -1311,13 +1313,23 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) (int)bufmgr_gem->gtt_size / 1024); } - gp.param = I915_PARAM_NUM_FENCES_AVAIL; - gp.value = &bufmgr_gem->available_fences; + gp.param = I915_PARAM_CHIPSET_ID; + gp.value = &bufmgr_gem->pci_device; ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); if (ret) { - fprintf(stderr, "get fences failed: %d\n", ret); + fprintf(stderr, "get chip id failed: %d\n", ret); fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value); - bufmgr_gem->available_fences = 0; + } + + if (!IS_I965G(bufmgr_gem)) { + gp.param = I915_PARAM_NUM_FENCES_AVAIL; + gp.value = &bufmgr_gem->available_fences; + ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); + if (ret) { + fprintf(stderr, "get fences failed: %d\n", ret); + fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value); + bufmgr_gem->available_fences = 0; + } } /* Let's go with one relocation per every 2 dwords (but round down a bit diff --git a/libdrm/intel/intel_chipset.h b/libdrm/intel/intel_chipset.h new file mode 100644 index 0000000..0b3af02 --- /dev/null +++ b/libdrm/intel/intel_chipset.h @@ -0,0 +1,71 @@ +/* + * + * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef _INTEL_CHIPSET_H +#define _INTEL_CHIPSET_H + +#define IS_I830(dev) ((dev)->pci_device == 0x3577) +#define IS_845G(dev) ((dev)->pci_device == 0x2562) +#define IS_I85X(dev) ((dev)->pci_device == 0x3582) +#define IS_I855(dev) ((dev)->pci_device == 0x3582) +#define IS_I865G(dev) ((dev)->pci_device == 0x2572) + +#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a) +#define IS_I915GM(dev) ((dev)->pci_device == 0x2592) +#define IS_I945G(dev) ((dev)->pci_device == 0x2772) +#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\ + (dev)->pci_device == 0x27AE) +#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \ + (dev)->pci_device == 0x2982 || \ + (dev)->pci_device == 0x2992 || \ + (dev)->pci_device == 0x29A2 || \ + (dev)->pci_device == 0x2A02 || \ + (dev)->pci_device == 0x2A12 || \ + (dev)->pci_device == 0x2A42 || \ + (dev)->pci_device == 0x2E02 || \ + (dev)->pci_device == 0x2E12 || \ + (dev)->pci_device == 0x2E22) + +#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02) + +#define IS_GM45(dev) ((dev)->pci_device == 0x2A42) + +#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \ + (dev)->pci_device == 0x2E12 || \ + (dev)->pci_device == 0x2E22) + +#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \ + (dev)->pci_device == 0x29B2 || \ + (dev)->pci_device == 0x29D2) + +#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ + IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) + +#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ + IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev)) + +#endif /* _INTEL_CHIPSET_H */ commit 9209c9a653e40d66435fbee7dde7450d5e470e03 Author: Eric Anholt <er...@an...> Date: Tue Jan 27 16:54:11 2009 -0800 intel: Fix under-counting of fences registers required in check_aperture. diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c index 7199cc1..765d903 100644 --- a/libdrm/intel/intel_bufmgr_gem.c +++ b/libdrm/intel/intel_bufmgr_gem.c @@ -166,6 +166,11 @@ struct _drm_intel_bo_gem { * the common case. */ int reloc_tree_size; + /** + * Number of potential fence registers required by this buffer and its + * relocations. + */ + int reloc_tree_fences; }; static void drm_intel_gem_bo_reference_locked(drm_intel_bo *bo); @@ -387,6 +392,7 @@ drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, bo_gem->refcount = 1; bo_gem->validate_index = -1; bo_gem->reloc_tree_size = bo_gem->bo.size; + bo_gem->reloc_tree_fences = 0; bo_gem->used_as_reloc_target = 0; bo_gem->tiling_mode = I915_TILING_NONE; bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; @@ -444,6 +450,10 @@ drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, const char *name, } bo_gem->tiling_mode = get_tiling.tiling_mode; bo_gem->swizzle_mode = get_tiling.swizzle_mode; + if (bo_gem->tiling_mode == I915_TILING_NONE) + bo_gem->reloc_tree_fences = 0; + else + bo_gem->reloc_tree_fences = 1; DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name); @@ -861,6 +871,7 @@ drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, */ assert(!bo_gem->used_as_reloc_target); bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size; + bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences; /* Flag the target to disallow further relocations in it. */ target_bo_gem->used_as_reloc_target = 1; @@ -1040,6 +1051,10 @@ drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode, if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode) return 0; + /* If we're going from non-tiling to tiling, bump fence count */ + if (bo_gem->tiling_mode == I915_TILING_NONE) + bo_gem->reloc_tree_fences++; + set_tiling.handle = bo_gem->gem_handle; set_tiling.tiling_mode = *tiling_mode; set_tiling.stride = stride; @@ -1052,6 +1067,10 @@ drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode, bo_gem->tiling_mode = set_tiling.tiling_mode; bo_gem->swizzle_mode = set_tiling.swizzle_mode; + /* If we're going from tiling to non-tiling, drop fence count */ + if (bo_gem->tiling_mode == I915_TILING_NONE) + bo_gem->reloc_tree_fences--; + *tiling_mode = bo_gem->tiling_mode; return 0; } @@ -1135,9 +1154,7 @@ drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo) * If the count is greater than the number of available regs, we'll have * to ask the caller to resubmit a batch with fewer tiled buffers. * - * This function under-counts buffers referenced from other buffers - * (such as the targets of the batchbuffer), and over-counts if the same - * buffer appears twice in the array. + * This function over-counts if the same buffer is used multiple times. */ static unsigned int drm_intel_gem_total_fences(drm_intel_bo **bo_array, int count) @@ -1151,8 +1168,7 @@ drm_intel_gem_total_fences(drm_intel_bo **bo_array, int count) if (bo_gem == NULL) continue; - if (bo_gem->tiling_mode != I915_TILING_NONE) - total++; + total += bo_gem->reloc_tree_fences; } return total; } commit 2fa5f28eeef4ce13a48c1998856a115c7e4161ac Author: Jesse Barnes <jb...@vi...> Date: Fri Jan 23 14:13:45 2009 -0800 intel: libdrm support for fence management in execbuf This patch tries to use the available fence count to figure out whether a given batch can succeed or not (just like the aperture check). Signed-off-by: Jesse Barnes <jb...@vi...> Signed-off-by: Eric Anholt <er...@an...> diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c index 7b821de..7199cc1 100644 --- a/libdrm/intel/intel_bufmgr_gem.c +++ b/libdrm/intel/intel_bufmgr_gem.c @@ -99,6 +99,7 @@ typedef struct _drm_intel_bufmgr_gem { struct drm_intel_gem_bo_bucket cache_bucket[DRM_INTEL_GEM_BO_BUCKETS]; uint64_t gtt_size; + int available_fences; } drm_intel_bufmgr_gem; struct _drm_intel_bo_gem { @@ -1129,6 +1130,34 @@ drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo) } /** + * Count the number of buffers in this list that need a fence reg + * + * If the count is greater than the number of available regs, we'll have + * to ask the caller to resubmit a batch with fewer tiled buffers. + * + * This function under-counts buffers referenced from other buffers + * (such as the targets of the batchbuffer), and over-counts if the same + * buffer appears twice in the array. + */ +static unsigned int +drm_intel_gem_total_fences(drm_intel_bo **bo_array, int count) +{ + int i; + unsigned int total = 0; + + for (i = 0; i < count; i++) { + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo_array[i]; + + if (bo_gem == NULL) + continue; + + if (bo_gem->tiling_mode != I915_TILING_NONE) + total++; + } + return total; +} + +/** * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready * for the next drm_intel_bufmgr_check_aperture_space() call. */ @@ -1206,9 +1235,17 @@ drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count) drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo_array[0]->bufmgr; unsigned int total = 0; unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4; + int total_fences; + + /* Check for fence reg constraints if necessary */ + if (bufmgr_gem->available_fences) { + total_fences = drm_intel_gem_total_fences(bo_array, count); + if (total_fences > bufmgr_gem->available_fences) + return -1; + } total = drm_intel_gem_estimate_batch_space(bo_array, count); - + if (total > threshold) total = drm_intel_gem_compute_batch_space(bo_array, count); @@ -1234,6 +1271,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) { drm_intel_bufmgr_gem *bufmgr_gem; struct drm_i915_gem_get_aperture aperture; + drm_i915_getparam_t gp; int ret, i; bufmgr_gem = calloc(1, sizeof(*bufmgr_gem)); @@ -1257,6 +1295,15 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) (int)bufmgr_gem->gtt_size / 1024); } + gp.param = I915_PARAM_NUM_FENCES_AVAIL; + gp.value = &bufmgr_gem->available_fences; + ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); + if (ret) { + fprintf(stderr, "get fences failed: %d\n", ret); + fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value); + bufmgr_gem->available_fences = 0; + } + /* Let's go with one relocation per every 2 dwords (but round down a bit * since a power of two will mean an extra page allocation for the reloc * buffer). diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h index 04ab4cf..5456e91 100644 --- a/shared-core/i915_drm.h +++ b/shared-core/i915_drm.h @@ -296,6 +296,7 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_LAST_DISPATCH 3 #define I915_PARAM_CHIPSET_ID 4 #define I915_PARAM_HAS_GEM 5 +#define I915_PARAM_NUM_FENCES_AVAIL 6 typedef struct drm_i915_getparam { int param; @@ -307,6 +308,7 @@ typedef struct drm_i915_getparam { #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 +#define I915_SETPARAM_NUM_USED_FENCES 4 typedef struct drm_i915_setparam { int param; |
From: <dar...@ke...> - 2009-02-09 23:27:57
|
shared-core/nouveau_fifo.c | 3 shared-core/nv50_fifo.c | 2 shared-core/nv50_graph.c | 4 shared-core/nv50_grctx.h | 2043 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 2049 insertions(+), 3 deletions(-) New commits: commit efcef2c2bcd7a8ea16381cc8d6ae06fff1bc3483 Author: Ben Skeggs <sk...@gm...> Date: Tue Feb 10 09:05:09 2009 +1000 drm/nv50: use a slightly different initial context for nv96 I'm not 100% sure that the nv94 one we were using won't work. The context layouts are identical (well.. same ctxprog, so of course!), only a couple of registers differ. But, be safe until we actually get some 9xxx chips working. diff --git a/shared-core/nv50_graph.c b/shared-core/nv50_graph.c index 84f3fd7..85dd332 100644 --- a/shared-core/nv50_graph.c +++ b/shared-core/nv50_graph.c @@ -199,9 +199,11 @@ nv50_graph_create_context(struct nouveau_channel *chan) ctxvals = nv92_ctxvals; break; case 0x94: - case 0x96: ctxvals = nv94_ctxvals; break; + case 0x96: + ctxvals = nv96_ctxvals; + break; case 0xaa: ctxvals = nvaa_ctxvals; break; diff --git a/shared-core/nv50_grctx.h b/shared-core/nv50_grctx.h index ef66608..245235f 100644 --- a/shared-core/nv50_grctx.h +++ b/shared-core/nv50_grctx.h @@ -11509,4 +11509,2047 @@ static unsigned nv94_ctxvals[] = { 0x0001, 0x00000001, 0x0000 }; + +static unsigned nv96_ctxvals[] = { + 0x0043, 0x00000000, + 0x0001, 0x00000030, + 0x0008, 0x00000000, + 0x0001, 0x00000002, + 0x0028, 0x00000000, + 0x0001, 0x00000003, + 0x0001, 0x00001000, + 0x000f, 0x00000000, + 0x0001, 0x0000fe0c, + 0x0004, 0x00000000, + 0x0001, 0x00001000, + 0x000a, 0x00000000, + 0x0001, 0x00000187, + 0x0004, 0x00000000, + 0x0001, 0x00001018, + 0x0001, 0x000000ff, + 0x000e, 0x00000000, + 0x0001, 0x00000004, + 0x0001, 0x042500df, + 0x0001, 0x00000000, + 0x0001, 0x00000600, + 0x0005, 0x00000000, + 0x0001, 0x01000000, + 0x0001, 0x000000ff, + 0x0001, 0x00000000, + 0x0001, 0x00000400, + 0x0005, 0x00000000, + 0x0001, 0x00000001, + 0x0001, 0x00000080, + 0x0001, 0x00000004, + 0x0006, 0x00000000, + 0x0001, 0x00000002, + 0x0001, 0x00000001, + 0x0003, 0x00000000, + 0x0001, 0x00000001, + 0x0001, 0x00000100, + 0x0005, 0x00000000, + 0x0001, 0x00000002, + 0x0002, 0x00000001, + 0x0003, 0x00000000, + 0x0001, 0x00000001, + 0x0001, 0x003fffff, + 0x0001, 0x00001fff, + 0x0001, 0x00000000, + 0x0002, 0x00000001, + 0x0001, 0x00000000, + 0x0003, 0x00000001, + 0x0001, 0x00000004, + 0x0003, 0x00000001, + 0x0001, 0x00000007, + 0x0001, 0x00000001, + 0x0001, 0x00000007, + 0x0003, 0x00000001, + 0x0004, 0x00000000, + 0x0001, 0x00000001, + 0x0001, 0x00000100, + 0x0001, 0x00000000, + 0x0001, 0x00000001, + 0x0002, 0x00000000, + 0x0001, 0x00000100, + 0x0001, 0x00000001, + 0x0001, 0x00000100, + 0x0001, 0x00000000, + 0x0001, 0x00000001, + 0x0002, 0x00000000, + 0x0001, 0x00000100, + 0x0004, 0x00000000, + 0x0001, 0x00000004, + 0x0001, 0x00000070, + 0x0001, 0x00000080, + 0x0004, 0x00000000, + 0x0001, 0x0000000c, + 0x0001, 0x00000000, + 0x0001, 0x00000008, + 0x0001, 0x00000014, + 0x0001, 0x00000000, + 0x0001, 0x00000029, + 0x0001, 0x00000027, + 0x0001, 0x00000026, + 0x0001, 0x00000008, + 0x0001, 0x00000004, + 0x0001, 0x00000027, + 0x0002, 0x00000000, + 0x0001, 0x00000001, + 0x0001, 0x00000002, + 0x0001, 0x00000003, + 0x0001, 0x00000004, + 0x0001, 0x00000005, + 0x0001, 0x00000006, + 0x0001, 0x00000007, + 0x0001, 0x00000001, + 0x0010, 0x00000000, + 0x0001, 0x000000cf, + 0x000b, 0x00000000, + 0x0001, 0x00000080, + 0x0002, 0x00000004, + 0x0001, 0x00000003, + 0x0001, 0x00000001, + 0x0002, 0x00000000, + 0x0001, 0x00000012, + 0x0001, 0x00000010, + 0x0001, 0x0000000c, + 0x0001, 0x00000001, + 0x0003, 0x00000000, + 0x0001, 0x00000004, + 0x0001, 0x00000002, + 0x0001, 0x00000004, + 0x0002, 0x00000000, + 0x0001, 0x003fffff, + 0x0001, 0x00001fff, + 0x0009, 0x00000000, + 0x0001, 0x00000004, + 0x0001, 0x00000014, + 0x0001, 0x00000001, + 0x0002, 0x00000000, + 0x0001, 0x00000002, + 0x0002, 0x00000000, + 0x0001, 0x00000001, + 0x0001, 0x00000000, + 0x0001, 0x00000002, + 0x0001, 0x00001000, + 0x0001, 0x00000e00, + 0x0001, 0x00001000, + 0x0001, 0x00001e00, + 0x0001, 0x00000000, + 0x0005, 0x00000001, + 0x0003, 0x00000000, + 0x0001, 0x00000200, + 0x0001, 0x00000000, + 0x0001, 0x00000001, + 0x0001, 0x00000070, + 0x0001, 0x00000080, + 0x0002, 0x00000000, + 0x0001, 0x00000001, + 0x0001, 0x00000070, + 0x0001, 0x00000080, + 0x0003, 0x00000000, + 0x0001, 0x00000001, + 0x0001, 0x000000cf, + 0x0001, 0x00000000, + 0x0001, 0x00000001, + 0x0003, 0x00000000, + 0x0001, 0x000000cf, + 0x0001, 0x00000000, + 0x0001, 0x00000002, + 0x0001, 0x00000000, + 0x0001, 0x00000001, + 0x0001, 0x00000000, + 0x0001, 0x00000001, + 0x0001, 0x00000000, + 0x0002, 0x000000cf, + 0x0001, 0x00000001, + 0x0001, 0x00000000, + 0x0001, 0x00001f80, + 0x0005, 0x00000000, + 0x0001, 0x3b74f821, + 0x0001, 0x89058001, + 0x0001, 0x00000000, + 0x0001, 0x00001000, + 0x0001, 0x0000001f, + 0x0001, 0x027c10fa, + 0x0001, 0x400000c0, + 0x0001, 0xb7892080, + 0x0002, 0x00000000, + 0x0001, 0x3b74f821, + 0x0001, 0x89058001, + 0x0001, 0x00000000, + 0x0001, 0x00001000, + 0x0001, 0x0000001f, + 0x0001, 0x027c10fa, + 0x0001, 0x400000c0, + 0x0001, 0xb7892080, + 0x0002, 0x00000000, + 0x0001, 0x3b74f821, + 0x0001, 0x89058001, + 0x0001, 0x00000000, + 0x0001, 0x00001000, + 0x0001, 0x0000001f, + 0x0001, 0x027c10fa, + 0x0001, 0x400000c0, + 0x0001, 0xb7892080, + 0x0002, 0x00000000, + 0x0001, 0x3b74f821, + 0x0001, 0x89058001, + 0x0001, 0x00000000, + 0x0001, 0x00001000, + 0x0001, 0x0000001f, + 0x0001, 0x027c10fa, + 0x0001, 0x400000c0, + 0x0001, 0xb7892080, + 0x0002, 0x00000000, + 0x0001, 0x00390040, + 0x0001, 0x00000000, + 0x0001, 0x00000022, + 0x0002, 0x00000000, + 0x0001, 0x00390040, + 0x0001, 0x00000022, + 0x0005, 0x00000000, + 0x0001, 0x01800000, + 0x0001, 0x00160000, + 0x0001, 0x01800000, + 0x0003, 0x00000000, + 0x0001, 0x0003ffff, + 0x0001, 0x118c0000, + 0x0008, 0x00000000, + 0x0001, 0x00010401, + 0x0001, 0x00000000, + 0x0001, 0x00000078, + 0x0001, 0x00000000, + 0x0001, 0x000000bf, + 0x0001, 0x00000000, + 0x0001, 0x00001210, + 0x0001, 0x08000080, + 0x0008, 0x00000000, + 0x0001, 0x01800000, + 0x0001, 0x00160000, + 0x0001, 0x01800000, + 0x0003, 0x00000000, + 0x0001, 0x0003ffff, + 0x0001, 0x118c0000, + 0x0008, 0x00000000, + 0x0001, 0x00010401, + 0x0001, 0x00000000, + 0x0001, 0x00000078, + 0x0001, 0x00000000, + 0x0001, 0x000000bf, + 0x0001, 0x00000000, + 0x0001, 0x00001210, + 0x0001, 0x08000080, + 0x0009, 0x00000000, + 0x0001, 0x00027070, + 0x0002, 0x00000000, + 0x0001, 0x03ffffff, + 0x0005, 0x00000000, + 0x0001, 0x00120407, + 0x0001, 0x05091507, + 0x0001, 0x05010202, + 0x0001, 0x00030201, + 0x0006, 0x00000000, + 0x0001, 0x00000040, + 0x0001, 0x0d0c0b0a, + 0x0001, 0x00141210, + 0x0001, 0x000001f0, + 0x0001, 0x00000001, + 0x0001, 0x00000003, + 0x0002, 0x00000000, + 0x0001, 0x00039e00, + 0x0001, 0x00000100, + 0x0001, 0x00003800, + 0x0001, 0x00404040, + 0x0001, 0x0000ff0a, + 0x0001, 0x00000000, + 0x0001, 0x0077f005, + 0x0001, 0x003f7fff, + 0x0003, 0x00000000, + 0x0001, 0x01800000, + 0x0001, 0x00160000, + 0x0001, 0x01800000, + 0x0003, 0x00000000, + 0x0001, 0x0003ffff, + 0x0001, 0x118c0000, + 0x0008, 0x00000000, + 0x0001, 0x00010401, + 0x0001, 0x00000000, + 0x0001, 0x00000078, + 0x0001, 0x00000000, + 0x0001, 0x000000bf, + 0x0001, 0x00000000, + 0x0001, 0x00001210, + 0x0001, 0x08000080, + 0x0008, 0x00000000, + 0x0001, 0x01800000, + 0x0001, 0x00160000, + 0x0001, 0x01800000, + 0x0003, 0x00000000, + 0x0001, 0x0003ffff, + 0x0001, 0x118c0000, + 0x0008, 0x00000000, + 0x0001, 0x00010401, + 0x0001, 0x00000000, + 0x0001, 0x00000078, + 0x0001, 0x00000000, + 0x0001, 0x000000bf, + 0x0001, 0x00000000, + 0x0001, 0x00001210, + 0x0001, 0x08000080, + 0x0009, 0x00000000, + 0x0001, 0x00027070, + 0x0002, 0x00000000, + 0x0001, 0x03ffffff, + 0x0005, 0x00000000, + 0x0001, 0x00120407, + 0x0001, 0x05091507, + 0x0001, 0x05010202, + 0x0001, 0x00030201, + 0x0006, 0x00000000, + 0x0001, 0x00000040, + 0x0001, 0x0d0c0b0a, + 0x0001, 0x00141210, + 0x0001, 0x000001f0, + 0x0001, 0x00000001, + 0x0001, 0x00000003, + 0x0002, 0x00000000, + 0x0001, 0x00039e00, + 0x0001, 0x00000100, + 0x0001, 0x00003800, + 0x0001, 0x00404040, + 0x0001, 0x0000ff0a, + 0x0001, 0x00000000, + 0x0001, 0x0077f005, + 0x0001, 0x003f7fff, + 0x0003, 0x00000000, + 0x0001, 0x01800000, + 0x0001, 0x00160000, + 0x0001, 0x01800000, + 0x0003, 0x00000000, + 0x0001, 0x0003ffff, + 0x0001, 0x118c0000, + 0x0008, 0x00000000, + 0x0001, 0x00010401, + 0x0001, 0x00000000, + 0x0001, 0x00000078, + 0x0001, 0x00000000, + 0x0001, 0x000000bf, + 0x0001, 0x00000000, + 0x0001, 0x00001210, + 0x0001, 0x08000080, + 0x0008, 0x00000000, + 0x0001, 0x01800000, + 0x0001, 0x00160000, + 0x0001, 0x01800000, + 0x0003, 0x00000000, + 0x0001, 0x0003ffff, + 0x0001, 0x118c0000, + 0x0008, 0x00000000, + 0x0001, 0x00010401, + 0x0001, 0x00000000, + 0x0001, 0x00000078, + 0x0001, 0x00000000, + 0x0001, 0x000000bf, + 0x0001, 0x00000000, + 0x0001, 0x00001210, + 0x0001, 0x08000080, + 0x0009, 0x00000000, + 0x0001, 0x00027070, + 0x0002, 0x00000000, + 0x0001, 0x03ffffff, + 0x0005, 0x00000000, + 0x0001, 0x00120407, + 0x0001, 0x05091507, + 0x0001, 0x05010202, + 0x0001, 0x00030201, + 0x0006, 0x00000000, + 0x0001, 0x00000040, + 0x0001, 0x0d0c0b0a, + 0x0001, 0x00141210, + 0x0001, 0x000001f0, + 0x0001, 0x00000001, + 0x0001, 0x00000003, + 0x0002, 0x00000000, + 0x0001, 0x00039e00, + 0x0001, 0x00000100, + 0x0001, 0x00003800, + 0x0001, 0x00404040, + 0x0001, 0x0000ff0a, + 0x0001, 0x00000000, + 0x0001, 0x0077f005, + 0x0001, 0x003f7fff, + 0x0003, 0x00000000, + 0x0001, 0x01800000, + 0x0001, 0x00160000, + 0x0001, 0x01800000, + 0x0003, 0x00000000, + 0x0001, 0x0003ffff, + 0x0001, 0x118c0000, + 0x0008, 0x00000000, + 0x0001, 0x00010401, + 0x0001, 0x00000000, + 0x0001, 0x00000078, + 0x0001, 0x00000000, + 0x0001, 0x000000bf, + 0x0001, 0x00000000, + 0x0001, 0x00001210, + 0x0001, 0x08000080, + 0x0008, 0x00000000, + 0x0001, 0x01800000, + 0x0001, 0x00160000, + 0x0001, 0x01800000, + 0x0003, 0x00000000, + 0x0001, 0x0003ffff, + 0x0001, 0x118c0000, + 0x0008, 0x00000000, + 0x0001, 0x00010401, + 0x0001, 0x00000000, + 0x0001, 0x00000078, + 0x0001, 0x00000000, + 0x0001, 0x000000bf, + 0x0001, 0x00000000, + 0x0001, 0x00001210, + 0x0001, 0x08000080, + 0x0009, 0x00000000, + 0x0001, 0x00027070, + 0x0002, 0x00000000, + 0x0001, 0x03ffffff, + 0x0005, 0x00000000, + 0x0001, 0x00120407, + 0x0001, 0x05091507, + 0x0001, 0x05010202, + 0x0001, 0x00030201, + 0x0006, 0x00000000, + 0x0001, 0x00000040, + 0x0001, 0x0d0c0b0a, + 0x0001, 0x00141210, + 0x0001, 0x000001f0, + 0x0001, 0x00000001, + 0x0001, 0x00000003, + 0x0002, 0x00000000, + 0x0001, 0x00039e00, + 0x0001, 0x00000100, + 0x0001, 0x00003800, + 0x0001, 0x00404040, + 0x0001, 0x0000ff0a, + 0x0001, 0x00000000, + 0x0001, 0x0077f005, + 0x0001, 0x003f7fff, + 0x0029, 0x00000000, + 0x0002, 0x00000004, + 0x0013, 0x00000000, + 0x0001, 0x0000000f, + 0x0021, 0x00000000, + 0x0001, 0x00000002, + 0x0005, 0x00000000, + 0x0001, 0x00000020, + 0x0009, 0x00000000, + 0x0001, 0x001ffe67, + 0x0067, 0x00000000, + 0x0001, 0x00000001, + 0x0002, 0x00000004, + 0x0003, 0x00000000, + 0x0001, 0x0000001a, + 0x0001, 0x00000000, + 0x0001, 0x00000010, + 0x0002, 0x00000004, + 0x0006, 0x00000000, + 0x0002, 0x00608080, + 0x000d, 0x00000000, + 0x0001, 0x00000001, + 0x0018, 0x00000000, + 0x0002, 0x00000004, + 0x0016, 0x00000000, + 0x0002, 0x00000004, + 0x0005, 0x00000000, + 0x0001, 0x00000002, + 0x0002, 0x00000004, + 0x0006, 0x00000000, + 0x0002, 0x00000080, + 0x0006, 0x00000000, + 0x0002, 0x00000004, + 0x000b, 0x00000000, + 0x0001, 0x00000004, + 0x0007, 0x00000000, + 0x0001, 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0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x00cf, 0x00000000, + 0x0001, 0x00000010, + 0x000f, 0x00000000, + 0x0001, 0x0000003f, + 0x0037, 0x00000000, + 0x0001, 0x00000001, + 0x000f, 0x00000000, + 0x0001, 0x00000001, + 0x000f, 0x00000000, + 0x0001, 0x00000001, + 0x0067, 0x00000000, + 0x0001, 0x00000011, + 0x003f, 0x00000000, + 0x0001, 0x0000000f, + 0x003f, 0x00000000, + 0x0001, 0x00000011, + 0x0037, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000002, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000002, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x000f, 0x00000000, + 0x0001, 0x001ffe67, + 0x000f, 0x00000000, + 0x0001, 0x0fac6881, + 0x00af, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000002, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000002, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x001f, 0x00000000, + 0x0001, 0x00000011, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x031f, 0x00000000, + 0x0001, 0x00000002, + 0x000f, 0x00000000, + 0x0001, 0x001ffe67, + 0x0067, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000010, + 0x0017, 0x00000000, + 0x0001, 0x00000001, + 0x0037, 0x00000000, + 0x0001, 0x00000002, + 0x0047, 0x00000000, + 0x0001, 0x00000001, + 0x0005, 0x00000000, + 0x0001, 0x0000000f, + 0x0001, 0x00000000, + 0x0001, 0x00000010, + 0x000d, 0x00000000, + 0x0001, 0x00000001, + 0x0001, 0x00000000, + 0x0001, 0x00000001, + 0x009f, 0x00000000, + 0x0001, 0x00000010, + 0x0087, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x0007, 0x00000000, + 0x0001, 0x3f800000, + 0x00cf, 0x00000000, + 0x0001, 0x00000010, + 0x000f, 0x00000000, + 0x0001, 0x0000003f, + 0x0037, 0x00000000, + 0x0001, 0x00000001, + 0x000f, 0x00000000, + 0x0001, 0x00000001, + 0x000d, 0x00000000, + 0x0001, 0x0000000f, + 0x0001, 0x00000000, + 0x0001, 0x00000001, + 0x0067, 0x00000000, + 0x0001, 0x00000011, + 0x003f, 0x00000000, + 0x0001, 0x0000000f, + 0x003f, 0x00000000, + 0x0001, 0x00000011, + 0x0037, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000002, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000002, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x000f, 0x00000000, + 0x0001, 0x001ffe67, + 0x000f, 0x00000000, + 0x0001, 0x0fac6881, + 0x00af, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000002, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000002, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x0007, 0x00000000, + 0x0001, 0x00000001, + 0x001f, 0x00000000, + 0x0001, 0x00000011, + 0x0007, 0x00000000, + 0x0001, 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0x00000000, + 0x0001, 0x00000004, + 0x0008, 0x00000000, + 0x0003, 0x00000002, + 0x0004, 0x00000000, + 0x0001, 0x00000002, + 0x0003, 0x00000011, + 0x0004, 0x00000000, + 0x0001, 0x00000011, + 0x0040, 0x00000000, + 0x0003, 0x0fac6881, + 0x0004, 0x00000000, + 0x0001, 0x0fac6881, + 0x0020, 0x00000000, + 0x0003, 0x00000004, + 0x0004, 0x00000000, + 0x0001, 0x00000004, + 0x0048, 0x00000000, + 0x0003, 0x00000002, + 0x0004, 0x00000000, + 0x0001, 0x00000002, + 0x0003, 0x00000001, + 0x0004, 0x00000000, + 0x0004, 0x00000001, + 0x0004, 0x00000000, + 0x0001, 0x00000001, + 0x0003, 0x00000002, + 0x0004, 0x00000000, + 0x0001, 0x00000002, + 0x0003, 0x00000001, + 0x0004, 0x00000000, + 0x0004, 0x00000001, + 0x0004, 0x00000000, + 0x0004, 0x00000001, + 0x0004, 0x00000000, + 0x0001, 0x00000001, + 0x0008, 0x00000000, + 0x0003, 0x00000004, + 0x0004, 0x00000000, + 0x0001, 0x00000004, + 0x1d18, 0x00000000, + 0x0003, 0x00000011, + 0x0004, 0x00000000, + 0x0001, 0x00000011, + 0x0008, 0x00000000, + 0x0003, 0x00000001, + 0x0004, 0x00000000, + 0x0001, 0x00000001, + 0x0000 +}; #endif commit f43039c52c7f27b61316beba5863968996a05bc0 Author: Ben Skeggs <sk...@gm...> Date: Tue Feb 10 09:02:17 2009 +1000 drm/nv50: correct ramfc pointer in channel header Suprisingly the card still worked without this... diff --git a/shared-core/nv50_fifo.c b/shared-core/nv50_fifo.c index d681066..c6dd0c3 100644 --- a/shared-core/nv50_fifo.c +++ b/shared-core/nv50_fifo.c @@ -269,7 +269,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan) if (!IS_G80) { INSTANCE_WR(chan->ramin->gpuobj, 0, chan->id); - INSTANCE_WR(chan->ramin->gpuobj, 1, chan->ramfc->instance); + INSTANCE_WR(chan->ramin->gpuobj, 1, chan->ramfc->instance >> 8); INSTANCE_WR(ramfc, 0x88/4, 0x3d520); /* some vram addy >> 10 */ INSTANCE_WR(ramfc, 0x98/4, chan->ramin->instance >> 12); commit 889b811e319ab80a4714854a0c0b242b5e36e0ca Author: Ben Skeggs <sk...@gm...> Date: Tue Feb 10 08:57:21 2009 +1000 drm/nv50: let the card handle the initial context switch Our PFIFO/PGRAPH context save/load functions don't really work well (at all?) on nv5x yet. Depending on what random state the card is in before the drm loads, fbcon probably won't work correctly. Luckily we've setup the GPU in such a way that it'll actually do a hw context switch for the first context. Not sure of how successful this'd be currently on the older chips (actually, pretty sure it won't work), so NV50 only for now. diff --git a/shared-core/nouveau_fifo.c b/shared-core/nouveau_fifo.c index 92ea8fc..114ed29 100644 --- a/shared-core/nouveau_fifo.c +++ b/shared-core/nouveau_fifo.c @@ -362,7 +362,8 @@ nouveau_fifo_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, /* If this is the first channel, setup PFIFO ourselves. For any * other case, the GPU will handle this when it switches contexts. */ - if (dev_priv->fifo_alloc_count == 1) { + if (dev_priv->card_type < NV_50 && + dev_priv->fifo_alloc_count == 1) { ret = engine->fifo.load_context(chan); if (ret) { nouveau_fifo_free(chan); |
From: <an...@ke...> - 2009-02-21 18:02:13
|
configure.ac | 7 --- libdrm/Makefile.am | 6 ++ libdrm/intel/intel_bufmgr.c | 7 +++ libdrm/intel/intel_bufmgr.h | 4 + libdrm/intel/intel_bufmgr_fake.c | 1 libdrm/intel/intel_bufmgr_gem.c | 81 ++++++++++++++++++++++++++------------- libdrm/intel/intel_bufmgr_priv.h | 10 ++++ libdrm/libdrm_lists.h | 2 8 files changed, 87 insertions(+), 31 deletions(-) New commits: commit 4d5341340fb6df22fffa7d4a214c54c085a1b1cf Author: Eric Anholt <er...@an...> Date: Sat Feb 21 10:01:40 2009 -0800 Fix distcheck for optional nouveau stuff. diff --git a/configure.ac b/configure.ac index 041374b..c1ee938 100644 --- a/configure.ac +++ b/configure.ac @@ -123,10 +123,7 @@ if test "x$UDEV" = xyes; then AC_DEFINE(UDEV, 1, [Have UDEV support]) fi -if test "x$NOUVEAU" = xyes; then -NOUVEAU_SUBDIR="nouveau" -AC_SUBST(NOUVEAU_SUBDIR) -fi +AM_CONDITIONAL(HAVE_NOUVEAU, [text "x$NOUVEAU" = xyes]) PKG_CHECK_MODULES(CAIRO, cairo, [HAVE_CAIRO=yes], [HAVE_CAIRO=no]) if test "x$HAVE_CAIRO" = xyes; then diff --git a/libdrm/Makefile.am b/libdrm/Makefile.am index 76145bc..4c066e0 100644 --- a/libdrm/Makefile.am +++ b/libdrm/Makefile.am @@ -18,7 +18,11 @@ # IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -SUBDIRS = . intel @NOUVEAU_SUBDIR@ +if HAVE_NOUVEAU +NOUVEAU_SUBDIR = nouveau +endif + +SUBDIRS = . intel $(NOUVEAU_SUBDIR) libdrm_la_LTLIBRARIES = libdrm.la libdrm_ladir = $(libdir) commit 2f1cdf79a7b7679f2602f27f18a0737f6e40e490 Author: Eric Anholt <er...@an...> Date: Sat Feb 21 09:57:19 2009 -0800 Bump version to 2.4.5 for new API additions. diff --git a/configure.ac b/configure.ac index dbead72..041374b 100644 --- a/configure.ac +++ b/configure.ac @@ -19,7 +19,7 @@ # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. AC_PREREQ(2.57) -AC_INIT([libdrm], 2.4.4, [dri...@li...], libdrm) +AC_INIT([libdrm], 2.4.5, [dri...@li...], libdrm) AC_CONFIG_SRCDIR([Makefile.am]) AM_INIT_AUTOMAKE([dist-bzip2]) commit 72abe983adfe7e8dcdcec11f1bc11d0b3daae063 Author: Eric Anholt <er...@an...> Date: Wed Feb 18 13:06:35 2009 -0800 intel: Add a new bufmgr alloc function to get BOs ready for rendering to. This avoids using the oldest BO in the BO cache and waiting for it to be idle before we turn around and render to it with the GPU. Thanks to Chris Wilson for pointing out how silly we were being. diff --git a/libdrm/intel/intel_bufmgr.c b/libdrm/intel/intel_bufmgr.c index 188eac2..25a6828 100644 --- a/libdrm/intel/intel_bufmgr.c +++ b/libdrm/intel/intel_bufmgr.c @@ -51,6 +51,13 @@ drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, return bufmgr->bo_alloc(bufmgr, name, size, alignment); } +drm_intel_bo * +drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, const char *name, + unsigned long size, unsigned int alignment) +{ + return bufmgr->bo_alloc_for_render(bufmgr, name, size, alignment); +} + void drm_intel_bo_reference(drm_intel_bo *bo) { diff --git a/libdrm/intel/intel_bufmgr.h b/libdrm/intel/intel_bufmgr.h index e8c2e06..111d2af 100644 --- a/libdrm/intel/intel_bufmgr.h +++ b/libdrm/intel/intel_bufmgr.h @@ -75,6 +75,10 @@ struct _drm_intel_bo { drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, unsigned long size, unsigned int alignment); +drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, + const char *name, + unsigned long size, + unsigned int alignment); void drm_intel_bo_reference(drm_intel_bo *bo); void drm_intel_bo_unreference(drm_intel_bo *bo); int drm_intel_bo_map(drm_intel_bo *bo, int write_enable); diff --git a/libdrm/intel/intel_bufmgr_fake.c b/libdrm/intel/intel_bufmgr_fake.c index 6c21625..e7cec35 100644 --- a/libdrm/intel/intel_bufmgr_fake.c +++ b/libdrm/intel/intel_bufmgr_fake.c @@ -1503,6 +1503,7 @@ drm_intel_bufmgr_fake_init(int fd, /* Hook in methods */ bufmgr_fake->bufmgr.bo_alloc = drm_intel_fake_bo_alloc; + bufmgr_fake->bufmgr.bo_alloc_for_render = drm_intel_fake_bo_alloc; bufmgr_fake->bufmgr.bo_reference = drm_intel_fake_bo_reference; bufmgr_fake->bufmgr.bo_unreference = drm_intel_fake_bo_unreference; bufmgr_fake->bufmgr.bo_map = drm_intel_fake_bo_map; diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c index 51641b7..6ddecf4 100644 --- a/libdrm/intel/intel_bufmgr_gem.c +++ b/libdrm/intel/intel_bufmgr_gem.c @@ -52,6 +52,7 @@ #include <sys/types.h> #include "errno.h" +#include "libdrm_lists.h" #include "intel_bufmgr.h" #include "intel_bufmgr_priv.h" #include "intel_chipset.h" @@ -67,7 +68,8 @@ typedef struct _drm_intel_bo_gem drm_intel_bo_gem; struct drm_intel_gem_bo_bucket { - drm_intel_bo_gem *head, **tail; + drmMMListHead head; + /** * Limit on the number of entries in this bucket. * @@ -145,8 +147,8 @@ struct _drm_intel_bo_gem { /** Mapped address for the buffer, saved across map/unmap cycles */ void *virtual; - /** free list */ - drm_intel_bo_gem *next; + /** BO cache list */ + drmMMListHead head; /** * Boolean of whether this BO and its children have been included in @@ -323,8 +325,9 @@ drm_intel_setup_reloc_list(drm_intel_bo *bo) } static drm_intel_bo * -drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, - unsigned long size, unsigned int alignment) +drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name, + unsigned long size, unsigned int alignment, + int for_render) { drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; drm_intel_bo_gem *bo_gem; @@ -353,19 +356,35 @@ drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, /* Get a buffer out of the cache if available */ if (bucket != NULL && bucket->num_entries > 0) { struct drm_i915_gem_busy busy; - - bo_gem = bucket->head; - memset(&busy, 0, sizeof(busy)); - busy.handle = bo_gem->gem_handle; - - ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy); - alloc_from_cache = (ret == 0 && busy.busy == 0); - - if (alloc_from_cache) { - bucket->head = bo_gem->next; - if (bo_gem->next == NULL) - bucket->tail = &bucket->head; + + if (for_render) { + /* Allocate new render-target BOs from the tail (MRU) + * of the list, as it will likely be hot in the GPU cache + * and in the aperture for us. + */ + bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.prev, head); + DRMLISTDEL(&bo_gem->head); bucket->num_entries--; + alloc_from_cache = 1; + } else { + /* For non-render-target BOs (where we're probably going to map it + * first thing in order to fill it with data), check if the + * last BO in the cache is unbusy, and only reuse in that case. + * Otherwise, allocating a new buffer is probably faster than + * waiting for the GPU to finish. + */ + bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.next, head); + + memset(&busy, 0, sizeof(busy)); + busy.handle = bo_gem->gem_handle; + + ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy); + alloc_from_cache = (ret == 0 && busy.busy == 0); + + if (alloc_from_cache) { + DRMLISTDEL(&bo_gem->head); + bucket->num_entries--; + } } } pthread_mutex_unlock(&bufmgr_gem->lock); @@ -406,6 +425,20 @@ drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, return &bo_gem->bo; } +static drm_intel_bo * +drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, const char *name, + unsigned long size, unsigned int alignment) +{ + return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, alignment, 1); +} + +static drm_intel_bo * +drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, + unsigned long size, unsigned int alignment) +{ + return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, alignment, 0); +} + /** * Returns a drm_intel_bo wrapping the given buffer object handle. * @@ -545,9 +578,7 @@ drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo) bo_gem->reloc_target_bo = NULL; bo_gem->reloc_count = 0; - bo_gem->next = NULL; - *bucket->tail = bo_gem; - bucket->tail = &bo_gem->next; + DRMLISTADDTAIL(&bo_gem->head, &bucket->head); bucket->num_entries++; } else { drm_intel_gem_bo_free(bo); @@ -827,10 +858,9 @@ drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr) struct drm_intel_gem_bo_bucket *bucket = &bufmgr_gem->cache_bucket[i]; drm_intel_bo_gem *bo_gem; - while ((bo_gem = bucket->head) != NULL) { - bucket->head = bo_gem->next; - if (bo_gem->next == NULL) - bucket->tail = &bucket->head; + while (!DRMLISTEMPTY(&bucket->head)) { + bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.next, head); + DRMLISTDEL(&bo_gem->head); bucket->num_entries--; drm_intel_gem_bo_free(&bo_gem->bo); @@ -1348,6 +1378,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2; bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc; + bufmgr_gem->bufmgr.bo_alloc_for_render = drm_intel_gem_bo_alloc_for_render; bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference; bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference; bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map; @@ -1367,7 +1398,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) bufmgr_gem->bufmgr.check_aperture_space = drm_intel_gem_check_aperture_space; /* Initialize the linked lists for BO reuse cache. */ for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) - bufmgr_gem->cache_bucket[i].tail = &bufmgr_gem->cache_bucket[i].head; + DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head); return &bufmgr_gem->bufmgr; } diff --git a/libdrm/intel/intel_bufmgr_priv.h b/libdrm/intel/intel_bufmgr_priv.h index 76d31e4..82d87b4 100644 --- a/libdrm/intel/intel_bufmgr_priv.h +++ b/libdrm/intel/intel_bufmgr_priv.h @@ -51,6 +51,16 @@ struct _drm_intel_bufmgr { drm_intel_bo *(*bo_alloc)(drm_intel_bufmgr *bufmgr, const char *name, unsigned long size, unsigned int alignment); + /** + * Allocate a buffer object, hinting that it will be used as a render target. + * + * This is otherwise the same as bo_alloc. + */ + drm_intel_bo *(*bo_alloc_for_render)(drm_intel_bufmgr *bufmgr, + const char *name, + unsigned long size, + unsigned int alignment); + /** Takes a reference on a buffer object */ void (*bo_reference)(drm_intel_bo *bo); diff --git a/libdrm/libdrm_lists.h b/libdrm/libdrm_lists.h index 8e23991..6410f57 100644 --- a/libdrm/libdrm_lists.h +++ b/libdrm/libdrm_lists.h @@ -29,6 +29,8 @@ * list handling. No list looping yet. */ +#include <stddef.h> + typedef struct _drmMMListHead { struct _drmMMListHead *prev; |
From: <rn...@ke...> - 2009-03-16 05:44:01
|
bsd-core/drm_drv.c | 8 ++++++-- bsd-core/drm_linux_list.h | 4 ++++ bsd-core/drm_vm.c | 7 ++++++- 3 files changed, 16 insertions(+), 3 deletions(-) New commits: commit dec955d728505f060afccd047ff2b572cb4ba3c1 Author: Robert Noland <rn...@2h...> Date: Mon Mar 16 00:41:23 2009 -0500 FreeBSD: Add support for matching solely on vedor id. This also adds that ability to set device name from VPD, but that doesn't seem to be working... diff --git a/bsd-core/drm_drv.c b/bsd-core/drm_drv.c index 883e3a0..a9165a4 100644 --- a/bsd-core/drm_drv.c +++ b/bsd-core/drm_drv.c @@ -179,7 +179,10 @@ int drm_probe(device_t kdev, drm_pci_id_list_t *idlist) id_entry = drm_find_description(vendor, device, idlist); if (id_entry != NULL) { - device_set_desc(kdev, id_entry->name); + if (!device_get_desc(kdev)) { + DRM_DEBUG("desc : %s\n", device_get_desc(kdev)); + device_set_desc(kdev, id_entry->name); + } return 0; } @@ -287,7 +290,8 @@ drm_pci_id_list_t *drm_find_description(int vendor, int device, for (i = 0; idlist[i].vendor != 0; i++) { if ((idlist[i].vendor == vendor) && - (idlist[i].device == device)) { + ((idlist[i].device == device) || + (idlist[i].device == 0))) { return &idlist[i]; } } commit 44fec1a8e487a14e0221e32759cc16ce9fcd7b00 Author: Robert Noland <rn...@2h...> Date: Mon Mar 16 00:35:18 2009 -0500 FreeBSD: Improve the debug output of drm_mmap(). diff --git a/bsd-core/drm_vm.c b/bsd-core/drm_vm.c index 4bc6f46..a7bee4b 100644 --- a/bsd-core/drm_vm.c +++ b/bsd-core/drm_vm.c @@ -83,8 +83,13 @@ int drm_mmap(struct cdev *kdev, vm_offset_t offset, vm_paddr_t *paddr, } if (map == NULL) { + DRM_DEBUG("Can't find map, requested offset = %016lx\n", + offset); + TAILQ_FOREACH(map, &dev->maplist, link) { + DRM_DEBUG("map offset = %016lx, handle = %016lx\n", + map->offset, (unsigned long)map->handle); + } DRM_UNLOCK(); - DRM_DEBUG("can't find map\n"); return -1; } if (((map->flags&_DRM_RESTRICTED) && !DRM_SUSER(DRM_CURPROC))) { commit f8f49aa6ec10e281b08279143f2bd999df118147 Author: Robert Noland <rn...@2h...> Date: Mon Mar 16 00:30:28 2009 -0500 FreeBSD: Add list_for_each_prev() to our bank of compat functions. diff --git a/bsd-core/drm_linux_list.h b/bsd-core/drm_linux_list.h index 7c6a447..15c1b6e 100644 --- a/bsd-core/drm_linux_list.h +++ b/bsd-core/drm_linux_list.h @@ -64,6 +64,10 @@ list_del(struct list_head *entry) { #define list_for_each(entry, head) \ for (entry = (head)->next; entry != head; entry = (entry)->next) +#define list_for_each_prev(entry, head) \ + for (entry = (head)->prev; entry != (head); \ + entry = entry->prev) + #define list_for_each_safe(entry, temp, head) \ for (entry = (head)->next, temp = (entry)->next; \ entry != head; \ |
From: <st...@ke...> - 2009-03-25 03:02:56
|
linux-core/drm_os_linux.h | 4 +++ shared-core/nouveau_dma.c | 1 shared-core/nouveau_mem.c | 54 ++++++++++++++++++++++++++++------------------ shared-core/nouveau_reg.h | 8 ++---- shared-core/nv40_mc.c | 2 - 5 files changed, 42 insertions(+), 27 deletions(-) New commits: commit c9cfeaa5542e08381a8144d0a5bd96036a19082f Author: Stuart Bennett <st...@fr...> Date: Tue Mar 24 23:39:41 2009 +0000 nouveau: plug drm fifo ioremap leak (#14941) diff --git a/shared-core/nouveau_dma.c b/shared-core/nouveau_dma.c index e519dc4..8b1549c 100644 --- a/shared-core/nouveau_dma.c +++ b/shared-core/nouveau_dma.c @@ -121,6 +121,7 @@ nouveau_dma_channel_takedown(struct drm_device *dev) DRM_DEBUG("\n"); if (dchan->chan) { + drm_core_ioremapfree(dchan->chan->pushbuf_mem->map, dev); nouveau_fifo_free(dchan->chan); dchan->chan = NULL; } commit 03ca202fa56ad7711ad0f7527a1e537154093e8a Author: Stuart Bennett <st...@fr...> Date: Tue Mar 24 23:26:30 2009 +0000 nouveau: add linux compat defines for PCI config access, use them for nvidia IGPs diff --git a/linux-core/drm_os_linux.h b/linux-core/drm_os_linux.h index 4f1e83b..f58296b 100644 --- a/linux-core/drm_os_linux.h +++ b/linux-core/drm_os_linux.h @@ -125,3 +125,7 @@ do { \ #define DRM_SPINLOCK_IRQSAVE(l, _flags) spin_lock_irqsave(l, _flags); #define DRM_SPINUNLOCK_IRQRESTORE(l, _flags) spin_unlock_irqrestore(l, _flags); #define DRM_SPINLOCK_ASSERT(l) do {} while (0) + +#define DRM_PCI_DEV struct pci_dev +#define drm_pci_get_bsf(b, s, f) pci_get_bus_and_slot(b, PCI_DEVFN(s, f)) +#define drm_pci_read_config_dword pci_read_config_dword diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 6d928f4..af23214 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -231,34 +231,46 @@ void nouveau_mem_close(struct drm_device *dev) nouveau_mem_takedown(&dev_priv->pci_heap); } -/*XXX won't work on BSD because of pci_read_config_dword */ +/*XXX BSD needs compat functions for pci access + * #define DRM_PCI_DEV struct device + * #define drm_pci_get_bsf pci_get_bsf + * and a small inline to do *val = pci_read_config(pdev->device, where, 4); + * might work + */ +static uint32_t nforce_pci_fn_read_config_dword(int devfn, int where, uint32_t *val) +{ +#ifdef __linux__ + DRM_PCI_DEV *pdev; + + if (!(pdev = drm_pci_get_bsf(0, 0, devfn))) { + DRM_ERROR("nForce PCI device function 0x%02x not found\n", + devfn); + return -ENODEV; + } + + return drm_pci_read_config_dword(pdev, where, val); +#else + DRM_ERROR("BSD compat for checking IGP memory amount needed\n"); + return 0; +#endif +} + static uint32_t nouveau_mem_fb_amount_igp(struct drm_device *dev) { -#if defined(__linux__) struct drm_nouveau_private *dev_priv = dev->dev_private; - struct pci_dev *bridge; - uint32_t mem; - - bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0,1)); - if (!bridge) { - DRM_ERROR("no bridge device\n"); - return 0; - } + uint32_t mem = 0; - if (dev_priv->flags&NV_NFORCE) { - pci_read_config_dword(bridge, 0x7C, &mem); + if (dev_priv->flags & NV_NFORCE) { + nforce_pci_fn_read_config_dword(1, 0x7C, &mem); return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; - } else - if(dev_priv->flags&NV_NFORCE2) { - pci_read_config_dword(bridge, 0x84, &mem); + } + if (dev_priv->flags & NV_NFORCE2) { + nforce_pci_fn_read_config_dword(1, 0x84, &mem); return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; } DRM_ERROR("impossible!\n"); -#else - DRM_ERROR("Linux kernel >= 2.6.19 required to check for igp memory amount\n"); -#endif return 0; } commit b71f3f114e6f0e94e15958c0aa12e804392f9df2 Author: Stuart Bennett <st...@fr...> Date: Tue Mar 24 16:42:36 2009 +0000 nouveau: use PFB_CSTATUS naming from ddx (reg introduced with nv10) NV04 had a PFB_FIFO_DATA at the same address, which we don't use, so remove it to reduce confusion diff --git a/shared-core/nouveau_mem.c b/shared-core/nouveau_mem.c index 64125b6..6d928f4 100644 --- a/shared-core/nouveau_mem.c +++ b/shared-core/nouveau_mem.c @@ -300,9 +300,9 @@ uint64_t nouveau_mem_fb_amount(struct drm_device *dev) } else { uint64_t mem; - mem = (NV_READ(NV04_FIFO_DATA) & - NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK) >> - NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT; + mem = (NV_READ(NV10_PFB_CSTATUS) & + NV10_PFB_CSTATUS_RAM_AMOUNT_MB_MASK) >> + NV10_PFB_CSTATUS_RAM_AMOUNT_MB_SHIFT; return mem*1024*1024; } break; diff --git a/shared-core/nouveau_reg.h b/shared-core/nouveau_reg.h index 060abe0..eade44e 100644 --- a/shared-core/nouveau_reg.h +++ b/shared-core/nouveau_reg.h @@ -11,10 +11,6 @@ # define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002 # define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003 -#define NV04_FIFO_DATA 0x0010020c -# define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000 -# define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20 - #define NV_RAMIN 0x00700000 #define NV_RAMHT_HANDLE_OFFSET 0 @@ -131,7 +127,9 @@ #define NV04_PFB_CFG0 0x00100200 #define NV04_PFB_CFG1 0x00100204 -#define NV40_PFB_020C 0x0010020C +#define NV10_PFB_CSTATUS 0x0010020C +# define NV10_PFB_CSTATUS_RAM_AMOUNT_MB_MASK 0xfff00000 +# define NV10_PFB_CSTATUS_RAM_AMOUNT_MB_SHIFT 20 #define NV10_PFB_TILE(i) (0x00100240 + (i*16)) #define NV10_PFB_TILE__SIZE 8 #define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16)) diff --git a/shared-core/nv40_mc.c b/shared-core/nv40_mc.c index ead6f87..cca8bf5 100644 --- a/shared-core/nv40_mc.c +++ b/shared-core/nv40_mc.c @@ -19,7 +19,7 @@ nv40_mc_init(struct drm_device *dev) case 0x46: /* G72 */ case 0x4e: case 0x4c: /* C51_G7X */ - tmp = NV_READ(NV40_PFB_020C); + tmp = NV_READ(NV10_PFB_CSTATUS); NV_WRITE(NV40_PMC_1700, tmp); NV_WRITE(NV40_PMC_1704, 0); NV_WRITE(NV40_PMC_1708, 0); |
From: <kr...@ke...> - 2009-04-06 21:27:54
|
configure.ac | 7 ++ tests/Makefile.am | 39 ++++++++++------ tests/drmtest.c | 117 ++++++++++++++++++++++++++++++++++---------------- tests/drmtest.h | 3 + tests/gem_basic.c | 6 ++ tests/gem_flink.c | 6 ++ tests/gem_mmap.c | 6 ++ tests/gem_readwrite.c | 6 ++ tests/getversion.c | 3 - tests/setversion.c | 5 ++ tests/updatedraw.c | 5 ++ 11 files changed, 147 insertions(+), 56 deletions(-) New commits: commit 751db3fe27d5e51925c28ceecadb828784d46028 Author: Kristian Høgsberg <kr...@re...> Date: Mon Apr 6 17:22:10 2009 -0400 Skip tests that require root This lets us do make distcheck as non-root. diff --git a/tests/setversion.c b/tests/setversion.c index f4bfbfb..3aaf7cc 100644 --- a/tests/setversion.c +++ b/tests/setversion.c @@ -40,6 +40,11 @@ int main(int argc, char **argv) int fd, ret; drm_set_version_t sv, version; + if (getuid() != 0) { + fprintf(stderr, "setversion test requires root, skipping\n"); + return 0; + } + fd = drm_open_any_master(); /* First, check that we can get the DD/DI versions. */ diff --git a/tests/updatedraw.c b/tests/updatedraw.c index 2f22fef..a61eb15 100644 --- a/tests/updatedraw.c +++ b/tests/updatedraw.c @@ -123,6 +123,11 @@ int main(int argc, char **argv) { int fd, ret, d1, d2; + if (getuid() != 0) { + fprintf(stderr, "updatedraw test requires root, skipping\n"); + return 0; + } + fd = drm_open_any_master(); d1 = add_drawable(fd); commit 8a5c4d567fafffbda57cbe5e4ed8c419193cada5 Author: Kristian Høgsberg <kr...@re...> Date: Mon Apr 6 17:18:17 2009 -0400 XFAIL auth and lock test cases They're writing to the read end of a pipe and failing. diff --git a/tests/Makefile.am b/tests/Makefile.am index 123c547..bc99447 100644 --- a/tests/Makefile.am +++ b/tests/Makefile.am @@ -22,17 +22,20 @@ libdrmtest_la_LIBADD = \ LDADD = libdrmtest.la -TESTS = auth \ - openclose \ - getversion \ - getclient \ - getstats \ - lock \ - setversion \ - updatedraw \ - gem_basic \ - gem_flink \ - gem_readwrite \ +XFAIL_TESTS = \ + auth \ + lock + +TESTS = \ + openclose \ + getversion \ + getclient \ + getstats \ + setversion \ + updatedraw \ + gem_basic \ + gem_flink \ + gem_readwrite \ gem_mmap EXTRA_PROGRAMS = $(TESTS) diff --git a/tests/getversion.c b/tests/getversion.c index 3de90de..711d376 100644 --- a/tests/getversion.c +++ b/tests/getversion.c @@ -40,7 +40,8 @@ int main(int argc, char **argv) assert(strlen(v->name) != 0); assert(strlen(v->date) != 0); assert(strlen(v->desc) != 0); - assert(v->version_major >= 1); + if (strcmp(v->name, "i915") == 0) + assert(v->version_major >= 1); drmFree(v); close(fd); return 0; commit e9d6116e5bd30639d6333ef95462fe300f47ccd5 Author: Kristian Høgsberg <kr...@re...> Date: Mon Apr 6 17:13:01 2009 -0400 Use libudev in test case to only run gem tests for intel devices. diff --git a/configure.ac b/configure.ac index 8be1e2a..2e32c84 100644 --- a/configure.ac +++ b/configure.ac @@ -131,6 +131,13 @@ if test "x$HAVE_CAIRO" = xyes; then fi AM_CONDITIONAL(HAVE_CAIRO, [test "x$HAVE_CAIRO" = xyes]) +# For enumerating devices in test case +PKG_CHECK_MODULES(LIBUDEV, libudev, [HAVE_LIBUDEV=yes], [HAVE_LIBUDEV=no]) +if test "x$HAVE_LIBUDEV" = xyes; then + AC_DEFINE(HAVE_LIBUDEV, 1, [Have libudev support]) +fi +AM_CONDITIONAL(HAVE_LIBUDEV, [test "x$HAVE_LIBUDEV" = xyes]) + AC_SUBST(WARN_CFLAGS) AC_OUTPUT([ diff --git a/tests/Makefile.am b/tests/Makefile.am index e66d1c8..123c547 100644 --- a/tests/Makefile.am +++ b/tests/Makefile.am @@ -6,19 +6,22 @@ noinst_PROGRAMS = \ dristat \ drmstat +SUBDIRS = \ + modeprint \ + modetest + +if HAVE_LIBUDEV + EXTRA_LTLIBRARIES = libdrmtest.la libdrmtest_la_SOURCES = \ drmtest.c \ drmtest.h libdrmtest_la_LIBADD = \ - $(top_builddir)/libdrm/libdrm.la + $(top_builddir)/libdrm/libdrm.la \ + $(LIBUDEV_LIBS) LDADD = libdrmtest.la -SUBDIRS = \ - modeprint \ - modetest - TESTS = auth \ openclose \ getversion \ @@ -33,5 +36,8 @@ TESTS = auth \ gem_mmap EXTRA_PROGRAMS = $(TESTS) + +endif + CLEANFILES = $(EXTRA_PROGRAMS) $(EXTRA_LTLIBRARIES) diff --git a/tests/drmtest.c b/tests/drmtest.c index 5453b10..15e5c4a 100644 --- a/tests/drmtest.c +++ b/tests/drmtest.c @@ -26,58 +26,103 @@ */ #include <fcntl.h> +#include <fnmatch.h> #include <sys/stat.h> #include "drmtest.h" -/** Open the first DRM device we can find, searching up to 16 device nodes */ -int drm_open_any(void) +#define LIBUDEV_I_KNOW_THE_API_IS_SUBJECT_TO_CHANGE +#include <libudev.h> + +static int is_master(int fd) { - char name[20]; + drm_client_t client; + int ret; + + /* Check that we're the only opener and authed. */ + client.idx = 0; + ret = ioctl(fd, DRM_IOCTL_GET_CLIENT, &client); + assert (ret == 0); + if (!client.auth) + return 0; + client.idx = 1; + ret = ioctl(fd, DRM_IOCTL_GET_CLIENT, &client); + if (ret != -1 || errno != EINVAL) + return 0; + + return 1; +} + +/** Open the first DRM device matching the criteria */ +int drm_open_matching(const char *pci_glob, int flags) +{ + struct udev *udev; + struct udev_enumerate *e; + struct udev_device *device, *parent; + struct udev_list_entry *entry; + const char *pci_id, *path; int i, fd; - for (i = 0; i < 16; i++) { - sprintf(name, "/dev/dri/card%d", i); - fd = open(name, O_RDWR); - if (fd != -1) - return fd; + udev = udev_new(); + if (udev == NULL) { + fprintf(stderr, "failed to initialize udev context\n"); + abort(); } - abort(); + + fd = -1; + e = udev_enumerate_new(udev); + udev_enumerate_add_match_subsystem(e, "drm"); + udev_enumerate_scan_devices(e); + udev_list_entry_foreach(entry, udev_enumerate_get_list_entry(e)) { + path = udev_list_entry_get_name(entry); + device = udev_device_new_from_syspath(udev, path); + parent = udev_device_get_parent(device); + /* Filter out KMS output devices. */ + if (strcmp(udev_device_get_subsystem(parent), "pci") != 0) + continue; + pci_id = udev_device_get_property_value(parent, "PCI_ID"); + if (fnmatch(pci_glob, pci_id, 0) != 0) + continue; + fd = open(udev_device_get_devnode(device), O_RDWR); + if (fd < 0) + continue; + if ((flags & DRM_TEST_MASTER) && !is_master(fd)) { + close(fd); + fd = -1; + continue; + } + + break; + } + udev_enumerate_unref(e); + udev_unref(udev); + + return fd; } +int drm_open_any(void) +{ + int fd = drm_open_matching("*:*", 0); + + if (fd < 0) { + fprintf(stderr, "failed to open any drm device\n"); + abort(); + } + + return fd; +} /** * Open the first DRM device we can find where we end up being the master. */ int drm_open_any_master(void) { - char name[20]; - int i, fd; + int fd = drm_open_matching("*:*", DRM_TEST_MASTER); - for (i = 0; i < 16; i++) { - drm_client_t client; - int ret; + if (fd < 0) { + fprintf(stderr, "failed to open any drm device\n"); + abort(); + } - sprintf(name, "/dev/dri/card%d", i); - fd = open(name, O_RDWR); - if (fd == -1) - continue; + return fd; - /* Check that we're the only opener and authed. */ - client.idx = 0; - ret = ioctl(fd, DRM_IOCTL_GET_CLIENT, &client); - assert (ret == 0); - if (!client.auth) { - close(fd); - continue; - } - client.idx = 1; - ret = ioctl(fd, DRM_IOCTL_GET_CLIENT, &client); - if (ret != -1 || errno != EINVAL) { - close(fd); - continue; - } - return fd; - } - fprintf(stderr, "Couldn't find an un-controlled DRM device\n"); - abort(); } diff --git a/tests/drmtest.h b/tests/drmtest.h index afa0df4..55bb446 100644 --- a/tests/drmtest.h +++ b/tests/drmtest.h @@ -33,5 +33,8 @@ #include "xf86drm.h" +#define DRM_TEST_MASTER 0x01 + int drm_open_any(void); int drm_open_any_master(void); +int drm_open_matching(const char *pci_glob, int flags); diff --git a/tests/gem_basic.c b/tests/gem_basic.c index b2176fb..4e4b6cb 100644 --- a/tests/gem_basic.c +++ b/tests/gem_basic.c @@ -88,7 +88,11 @@ int main(int argc, char **argv) { int fd; - fd = drm_open_any(); + fd = drm_open_matching("8086:*", 0); + if (fd < 0) { + fprintf(stderr, "failed to open intel drm device\n"); + return 0; + } test_bad_close(fd); test_create_close(fd); diff --git a/tests/gem_flink.c b/tests/gem_flink.c index d2e062f..ff999d2 100644 --- a/tests/gem_flink.c +++ b/tests/gem_flink.c @@ -117,7 +117,11 @@ int main(int argc, char **argv) { int fd; - fd = drm_open_any(); + fd = drm_open_matching("8086:*", 0); + if (fd < 0) { + fprintf(stderr, "failed to open intel drm device, skipping\n"); + return 0; + } test_flink(fd); test_double_flink(fd); diff --git a/tests/gem_mmap.c b/tests/gem_mmap.c index b5c1546..d24005b 100644 --- a/tests/gem_mmap.c +++ b/tests/gem_mmap.c @@ -81,7 +81,11 @@ int main(int argc, char **argv) int ret; int handle; - fd = drm_open_any(); + fd = drm_open_matching("8086:*", 0); + if (fd < 0) { + fprintf(stderr, "failed to open intel drm device, skipping\n"); + return 0; + } memset(&mmap, 0, sizeof(mmap)); mmap.handle = 0x10101010; diff --git a/tests/gem_readwrite.c b/tests/gem_readwrite.c index bd1d232..4f5cde6 100644 --- a/tests/gem_readwrite.c +++ b/tests/gem_readwrite.c @@ -78,7 +78,11 @@ int main(int argc, char **argv) int ret; int handle; - fd = drm_open_any(); + fd = drm_open_matching("8086:*", 0); + if (fd < 0) { + fprintf(stderr, "failed to open intel drm device, skipping\n"); + return 0; + } memset(&create, 0, sizeof(create)); create.size = OBJECT_SIZE; |
From: <dar...@ke...> - 2009-07-28 11:06:21
|
libdrm/nouveau/Makefile.am | 3 libdrm/nouveau/nouveau_bo.c | 403 ++---------------------------- libdrm/nouveau/nouveau_bo.h | 8 libdrm/nouveau/nouveau_channel.c | 66 ---- libdrm/nouveau/nouveau_class.h | 505 +++++++++++++++++++++++++++++++++----- libdrm/nouveau/nouveau_device.c | 10 libdrm/nouveau/nouveau_dma.c | 217 ---------------- libdrm/nouveau/nouveau_dma.h | 154 ----------- libdrm/nouveau/nouveau_drmif.h | 2 libdrm/nouveau/nouveau_fence.c | 243 ------------------ libdrm/nouveau/nouveau_notifier.c | 4 libdrm/nouveau/nouveau_private.h | 84 ------ libdrm/nouveau/nouveau_pushbuf.c | 100 +------ shared-core/nouveau_drm.h | 120 +-------- 14 files changed, 527 insertions(+), 1392 deletions(-) New commits: commit 5a73f066ba149816cc0fc2de4b97ec4714cf8ebc Author: Ben Skeggs <sk...@be...> Date: Tue Jul 28 08:12:21 2009 +1000 nouveau: don't overwrite user-specified bo size needlessly diff --git a/libdrm/nouveau/nouveau_bo.c b/libdrm/nouveau/nouveau_bo.c index 05e5a2e..520d5d7 100644 --- a/libdrm/nouveau/nouveau_bo.c +++ b/libdrm/nouveau/nouveau_bo.c @@ -49,7 +49,7 @@ nouveau_bo_info(struct nouveau_bo_priv *nvbo, struct drm_nouveau_gem_info *arg) { nvbo->handle = nvbo->base.handle = arg->handle; nvbo->domain = arg->domain; - nvbo->size = nvbo->base.size = arg->size; + nvbo->size = arg->size; nvbo->offset = arg->offset; nvbo->map_handle = arg->map_handle; nvbo->base.tile_mode = arg->tile_mode; @@ -268,6 +268,7 @@ nouveau_bo_wrap(struct nouveau_device *dev, uint32_t handle, } nouveau_bo_info(nvbo, &req); + nvbo->base.size = nvbo->size; return 0; } commit 0bf8fb3bce6b4d9b4820d38d37e1ac1e73e22d23 Author: Ben Skeggs <sk...@be...> Date: Tue Jul 28 07:46:20 2009 +1000 nouveau: user buffers need to be mappable diff --git a/libdrm/nouveau/nouveau_bo.c b/libdrm/nouveau/nouveau_bo.c index 4f91a5d..05e5a2e 100644 --- a/libdrm/nouveau/nouveau_bo.c +++ b/libdrm/nouveau/nouveau_bo.c @@ -235,7 +235,7 @@ nouveau_bo_user(struct nouveau_device *dev, void *ptr, int size, struct nouveau_bo_priv *nvbo; int ret; - ret = nouveau_bo_new(dev, 0, 0, size, bo); + ret = nouveau_bo_new(dev, NOUVEAU_BO_MAP, 0, size, bo); if (ret) return ret; nvbo = nouveau_bo(*bo); commit 001331f4f1f094ef02497aa618ae5eeb2febedfb Author: Ben Skeggs <bs...@re...> Date: Mon Jul 27 07:23:09 2009 +1000 nouveau: drm api 0.0.15, update object header, remove fake bo support diff --git a/libdrm/nouveau/Makefile.am b/libdrm/nouveau/Makefile.am index 688eeca..490ce57 100644 --- a/libdrm/nouveau/Makefile.am +++ b/libdrm/nouveau/Makefile.am @@ -18,9 +18,6 @@ libdrm_nouveau_la_SOURCES = \ nouveau_notifier.c \ nouveau_bo.c \ nouveau_resource.c \ - nouveau_dma.c \ - nouveau_fence.c \ - nouveau_dma.h \ nouveau_private.h libdrm_nouveaucommonincludedir = ${includedir}/nouveau diff --git a/libdrm/nouveau/nouveau_bo.c b/libdrm/nouveau/nouveau_bo.c index 6c8f6b0..4f91a5d 100644 --- a/libdrm/nouveau/nouveau_bo.c +++ b/libdrm/nouveau/nouveau_bo.c @@ -91,28 +91,6 @@ nouveau_bo_ufree(struct nouveau_bo_priv *nvbo) } static void -nouveau_bo_kfree_nomm(struct nouveau_bo_priv *nvbo) -{ - struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device); - struct drm_nouveau_mem_free req; - - if (nvbo->map) { - drmUnmap(nvbo->map, nvbo->size); - nvbo->map = NULL; - } - - req.offset = nvbo->offset; - if (nvbo->domain & NOUVEAU_BO_GART) - req.flags = NOUVEAU_MEM_AGP | NOUVEAU_MEM_PCI; - else - if (nvbo->domain & NOUVEAU_BO_VRAM) - req.flags = NOUVEAU_MEM_FB; - drmCommandWrite(nvdev->fd, DRM_NOUVEAU_MEM_FREE, &req, sizeof(req)); - - nvbo->handle = 0; -} - -static void nouveau_bo_kfree(struct nouveau_bo_priv *nvbo) { struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device); @@ -121,11 +99,6 @@ nouveau_bo_kfree(struct nouveau_bo_priv *nvbo) if (!nvbo->handle) return; - if (!nvdev->mm_enabled) { - nouveau_bo_kfree_nomm(nvbo); - return; - } - if (nvbo->map) { munmap(nvbo->map, nvbo->size); nvbo->map = NULL; @@ -137,51 +110,6 @@ nouveau_bo_kfree(struct nouveau_bo_priv *nvbo) } static int -nouveau_bo_kalloc_nomm(struct nouveau_bo_priv *nvbo) -{ - struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device); - struct drm_nouveau_mem_alloc req; - int ret; - - if (nvbo->handle) - return 0; - - if (!(nvbo->flags & (NOUVEAU_BO_VRAM|NOUVEAU_BO_GART))) - nvbo->flags |= (NOUVEAU_BO_GART | NOUVEAU_BO_VRAM); - - req.size = nvbo->size; - req.alignment = nvbo->align; - req.flags = 0; - if (nvbo->flags & NOUVEAU_BO_VRAM) - req.flags |= NOUVEAU_MEM_FB; - if (nvbo->flags & NOUVEAU_BO_GART) - req.flags |= (NOUVEAU_MEM_AGP | NOUVEAU_MEM_PCI); - if (nvbo->flags & NOUVEAU_BO_TILED) { - req.flags |= NOUVEAU_MEM_TILE; - if (nvbo->flags & NOUVEAU_BO_ZTILE) - req.flags |= NOUVEAU_MEM_TILE_ZETA; - } - req.flags |= NOUVEAU_MEM_MAPPED; - - ret = drmCommandWriteRead(nvdev->fd, DRM_NOUVEAU_MEM_ALLOC, - &req, sizeof(req)); - if (ret) - return ret; - - nvbo->handle = - nvbo->map_handle = req.map_handle; - nvbo->size = req.size; - nvbo->offset = req.offset; - if (req.flags & (NOUVEAU_MEM_AGP | NOUVEAU_MEM_PCI)) - nvbo->domain = NOUVEAU_BO_GART; - else - if (req.flags & NOUVEAU_MEM_FB) - nvbo->domain = NOUVEAU_BO_VRAM; - - return 0; -} - -static int nouveau_bo_kalloc(struct nouveau_bo_priv *nvbo, struct nouveau_channel *chan) { struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device); @@ -192,9 +120,6 @@ nouveau_bo_kalloc(struct nouveau_bo_priv *nvbo, struct nouveau_channel *chan) if (nvbo->handle || (nvbo->flags & NOUVEAU_BO_PIN)) return 0; - if (!nvdev->mm_enabled) - return nouveau_bo_kalloc_nomm(nvbo); - req.channel_hint = chan ? chan->id : 0; req.align = nvbo->align; @@ -227,21 +152,6 @@ nouveau_bo_kalloc(struct nouveau_bo_priv *nvbo, struct nouveau_channel *chan) } static int -nouveau_bo_kmap_nomm(struct nouveau_bo_priv *nvbo) -{ - struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device); - int ret; - - ret = drmMap(nvdev->fd, nvbo->handle, nvbo->size, &nvbo->map); - if (ret) { - nvbo->map = NULL; - return ret; - } - - return 0; -} - -static int nouveau_bo_kmap(struct nouveau_bo_priv *nvbo) { struct nouveau_device_priv *nvdev = nouveau_device(nvbo->base.device); @@ -252,9 +162,6 @@ nouveau_bo_kmap(struct nouveau_bo_priv *nvbo) if (!nvbo->map_handle) return -EINVAL; - if (!nvdev->mm_enabled) - return nouveau_bo_kmap_nomm(nvbo); - nvbo->map = mmap(0, nvbo->size, PROT_READ | PROT_WRITE, MAP_SHARED, nvdev->fd, nvbo->map_handle); if (nvbo->map == MAP_FAILED) { @@ -339,28 +246,6 @@ nouveau_bo_user(struct nouveau_device *dev, void *ptr, int size, } int -nouveau_bo_fake(struct nouveau_device *dev, uint64_t offset, uint32_t flags, - uint32_t size, void *map, struct nouveau_bo **bo) -{ - struct nouveau_bo_priv *nvbo; - int ret; - - ret = nouveau_bo_new(dev, flags & ~NOUVEAU_BO_PIN, 0, size, bo); - if (ret) - return ret; - nvbo = nouveau_bo(*bo); - - nvbo->flags = flags | NOUVEAU_BO_PIN; - nvbo->domain = (flags & (NOUVEAU_BO_VRAM|NOUVEAU_BO_GART)); - nvbo->offset = offset; - nvbo->size = nvbo->base.size = size; - nvbo->map = map; - nvbo->base.flags = nvbo->flags; - nvbo->base.offset = nvbo->offset; - return 0; -} - -int nouveau_bo_wrap(struct nouveau_device *dev, uint32_t handle, struct nouveau_bo **bo) { @@ -369,9 +254,6 @@ nouveau_bo_wrap(struct nouveau_device *dev, uint32_t handle, struct nouveau_bo_priv *nvbo; int ret; - if (!nvdev->mm_enabled) - return -ENODEV; - ret = nouveau_bo_new(dev, 0, 0, 0, bo); if (ret) return ret; @@ -406,18 +288,14 @@ nouveau_bo_handle_get(struct nouveau_bo *bo, uint32_t *handle) if (ret) return ret; - if (nvdev->mm_enabled) { - req.handle = nvbo->handle; - ret = ioctl(nvdev->fd, DRM_IOCTL_GEM_FLINK, &req); - if (ret) { - nouveau_bo_kfree(nvbo); - return ret; - } - - nvbo->global_handle = req.name; - } else { - nvbo->global_handle = nvbo->offset; + req.handle = nvbo->handle; + ret = ioctl(nvdev->fd, DRM_IOCTL_GEM_FLINK, &req); + if (ret) { + nouveau_bo_kfree(nvbo); + return ret; } + + nvbo->global_handle = req.name; } *handle = nvbo->global_handle; @@ -433,51 +311,25 @@ nouveau_bo_handle_ref(struct nouveau_device *dev, uint32_t handle, struct drm_gem_open req; int ret; - if (!nvdev->mm_enabled) { - ret = nouveau_bo_new(dev, 0, 0, 0, bo); - if (ret) - return ret; - nvbo = nouveau_bo(*bo); - - nvbo->handle = 0; - nvbo->offset = handle; - nvbo->domain = NOUVEAU_BO_VRAM; - nvbo->flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_PIN; - nvbo->base.offset = nvbo->offset; - nvbo->base.flags = nvbo->flags; - } else { - req.name = handle; - ret = ioctl(nvdev->fd, DRM_IOCTL_GEM_OPEN, &req); - if (ret) { - nouveau_bo_ref(NULL, bo); - return ret; - } - - ret = nouveau_bo_wrap(dev, req.handle, bo); - if (ret) { - nouveau_bo_ref(NULL, bo); - return ret; - } + req.name = handle; + ret = ioctl(nvdev->fd, DRM_IOCTL_GEM_OPEN, &req); + if (ret) { + nouveau_bo_ref(NULL, bo); + return ret; + } - nvbo = nouveau_bo(*bo); + ret = nouveau_bo_wrap(dev, req.handle, bo); + if (ret) { + nouveau_bo_ref(NULL, bo); + return ret; } + nvbo = nouveau_bo(*bo); nvbo->base.handle = nvbo->handle; return 0; } static void -nouveau_bo_del_cb(void *priv) -{ - struct nouveau_bo_priv *nvbo = priv; - - nouveau_fence_ref(NULL, &nvbo->fence); - nouveau_fence_ref(NULL, &nvbo->wr_fence); - nouveau_bo_kfree(nvbo); - free(nvbo); -} - -static void nouveau_bo_del(struct nouveau_bo **bo) { struct nouveau_bo_priv *nvbo; @@ -496,18 +348,8 @@ nouveau_bo_del(struct nouveau_bo **bo) } nouveau_bo_ufree(nvbo); - - if (!nouveau_device(nvbo->base.device)->mm_enabled && nvbo->fence) { - nouveau_fence_flush(nvbo->fence->channel); - if (nouveau_fence(nvbo->fence)->signalled) { - nouveau_bo_del_cb(nvbo); - } else { - nouveau_fence_signal_cb(nvbo->fence, - nouveau_bo_del_cb, nvbo); - } - } else { - nouveau_bo_del_cb(nvbo); - } + nouveau_bo_kfree(nvbo); + free(nvbo); } int @@ -527,24 +369,7 @@ nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pbo) } static int -nouveau_bo_wait_nomm(struct nouveau_bo *bo, int cpu_write) -{ - struct nouveau_bo_priv *nvbo = nouveau_bo(bo); - int ret = 0; - - if (cpu_write) - ret = nouveau_fence_wait(&nvbo->fence); - else - ret = nouveau_fence_wait(&nvbo->wr_fence); - if (ret) - return ret; - - nvbo->write_marker = 0; - return 0; -} - -static int -nouveau_bo_wait(struct nouveau_bo *bo, int cpu_write) +nouveau_bo_wait(struct nouveau_bo *bo, int cpu_write, int no_wait, int no_block) { struct nouveau_device_priv *nvdev = nouveau_device(bo->device); struct nouveau_bo_priv *nvbo = nouveau_bo(bo); @@ -560,10 +385,15 @@ nouveau_bo_wait(struct nouveau_bo *bo, int cpu_write) nouveau_pushbuf_flush(nvbo->pending_channel, 0); } - if (!nvdev->mm_enabled) - return nouveau_bo_wait_nomm(bo, cpu_write); - req.handle = nvbo->handle; + req.flags = 0; + if (cpu_write) + req.flags |= NOUVEAU_GEM_CPU_PREP_WRITE; + if (no_wait) + req.flags |= NOUVEAU_GEM_CPU_PREP_NOWAIT; + if (no_block) + req.flags |= NOUVEAU_GEM_CPU_PREP_NOBLOCK; + do { ret = drmCommandWrite(nvdev->fd, DRM_NOUVEAU_GEM_CPU_PREP, &req, sizeof(req)); @@ -608,7 +438,8 @@ nouveau_bo_map_range(struct nouveau_bo *bo, uint32_t delta, uint32_t size, return ret; if (!(flags & NOUVEAU_BO_NOSYNC)) { - ret = nouveau_bo_wait(bo, (flags & NOUVEAU_BO_WR)); + ret = nouveau_bo_wait(bo, (flags & NOUVEAU_BO_WR), + (flags & NOUVEAU_BO_NOWAIT), 0); if (ret) return ret; } @@ -633,10 +464,9 @@ nouveau_bo_map(struct nouveau_bo *bo, uint32_t flags) void nouveau_bo_unmap(struct nouveau_bo *bo) { - struct nouveau_device_priv *nvdev = nouveau_device(bo->device); struct nouveau_bo_priv *nvbo = nouveau_bo(bo); - if (nvdev->mm_enabled && bo->map && !nvbo->sysmem) { + if (bo->map && !nvbo->sysmem) { struct nouveau_device_priv *nvdev = nouveau_device(bo->device); struct drm_nouveau_gem_cpu_fini req; @@ -649,95 +479,6 @@ nouveau_bo_unmap(struct nouveau_bo *bo) } int -nouveau_bo_validate_nomm(struct nouveau_bo_priv *nvbo, uint32_t flags) -{ - struct nouveau_bo *new = NULL; - uint32_t t_handle, t_domain, t_offset, t_size, t_maph; - void *t_map; - int ret; - - if ((flags & NOUVEAU_BO_VRAM) && nvbo->domain == NOUVEAU_BO_VRAM) - return 0; - if ((flags & NOUVEAU_BO_GART) && nvbo->domain == NOUVEAU_BO_GART) - return 0; - assert(flags & (NOUVEAU_BO_VRAM|NOUVEAU_BO_GART)); - - /* Keep tiling info */ - flags |= (nvbo->flags & (NOUVEAU_BO_TILED|NOUVEAU_BO_ZTILE)); - - ret = nouveau_bo_new(nvbo->base.device, flags, 0, nvbo->size, &new); - if (ret) - return ret; - - ret = nouveau_bo_kalloc(nouveau_bo(new), NULL); - if (ret) { - nouveau_bo_ref(NULL, &new); - return ret; - } - - if (nvbo->handle || nvbo->sysmem) { - nouveau_bo_kmap(nouveau_bo(new)); - - if (!nvbo->base.map) { - nouveau_bo_map(&nvbo->base, NOUVEAU_BO_RD); - memcpy(nouveau_bo(new)->map, nvbo->base.map, nvbo->base.size); - nouveau_bo_unmap(&nvbo->base); - } else { - memcpy(nouveau_bo(new)->map, nvbo->base.map, nvbo->base.size); - } - } - - t_handle = nvbo->handle; - t_maph = nvbo->map_handle; - t_domain = nvbo->domain; - t_offset = nvbo->offset; - t_size = nvbo->size; - t_map = nvbo->map; - - nvbo->handle = nouveau_bo(new)->handle; - nvbo->map_handle = nouveau_bo(new)->map_handle; - nvbo->domain = nouveau_bo(new)->domain; - nvbo->offset = nouveau_bo(new)->offset; - nvbo->size = nouveau_bo(new)->size; - nvbo->map = nouveau_bo(new)->map; - - nouveau_bo(new)->handle = t_handle; - nouveau_bo(new)->map_handle = t_maph; - nouveau_bo(new)->domain = t_domain; - nouveau_bo(new)->offset = t_offset; - nouveau_bo(new)->size = t_size; - nouveau_bo(new)->map = t_map; - - nouveau_bo_ref(NULL, &new); - - return 0; -} - -static int -nouveau_bo_pin_nomm(struct nouveau_bo *bo, uint32_t flags) -{ - struct nouveau_bo_priv *nvbo = nouveau_bo(bo); - int ret; - - if (!nvbo->handle) { - if (!(flags & (NOUVEAU_BO_VRAM | NOUVEAU_BO_GART))) - return -EINVAL; - - ret = nouveau_bo_validate_nomm(nvbo, flags & ~NOUVEAU_BO_PIN); - if (ret) - return ret; - } - - nvbo->pinned = 1; - - /* Fill in public nouveau_bo members */ - bo->flags = nvbo->domain; - bo->offset = nvbo->offset; - - return 0; -} - -int nouveau_bo_pin(struct nouveau_bo *bo, uint32_t flags) { struct nouveau_device_priv *nvdev = nouveau_device(bo->device); @@ -748,9 +489,6 @@ nouveau_bo_pin(struct nouveau_bo *bo, uint32_t flags) if (nvbo->pinned) return 0; - if (!nvdev->mm_enabled) - return nouveau_bo_pin_nomm(bo, flags); - /* Ensure we have a kernel object... */ if (!nvbo->flags) { if (!(flags & (NOUVEAU_BO_VRAM | NOUVEAU_BO_GART))) @@ -801,80 +539,16 @@ nouveau_bo_unpin(struct nouveau_bo *bo) if (!nvbo->pinned) return; - if (nvdev->mm_enabled) { - req.handle = nvbo->handle; - drmCommandWrite(nvdev->fd, DRM_NOUVEAU_GEM_UNPIN, - &req, sizeof(req)); - } + req.handle = nvbo->handle; + drmCommandWrite(nvdev->fd, DRM_NOUVEAU_GEM_UNPIN, &req, sizeof(req)); nvbo->pinned = bo->offset = bo->flags = 0; } int -nouveau_bo_tile(struct nouveau_bo *bo, uint32_t flags, uint32_t delta, - uint32_t size) -{ - struct nouveau_device_priv *nvdev = nouveau_device(bo->device); - struct nouveau_bo_priv *nvbo = nouveau_bo(bo); - uint32_t kern_flags = 0; - int ret = 0; - - if (flags & NOUVEAU_BO_TILED) { - kern_flags |= NOUVEAU_MEM_TILE; - if (flags & NOUVEAU_BO_ZTILE) - kern_flags |= NOUVEAU_MEM_TILE_ZETA; - } - - if (nvdev->mm_enabled) { - struct drm_nouveau_gem_tile req; - - req.handle = nvbo->handle; - req.delta = delta; - req.size = size; - req.flags = kern_flags; - ret = drmCommandWrite(nvdev->fd, DRM_NOUVEAU_GEM_TILE, - &req, sizeof(req)); - } else { - struct drm_nouveau_mem_tile req; - - req.offset = nvbo->offset; - req.delta = delta; - req.size = size; - req.flags = kern_flags; - - if (flags & NOUVEAU_BO_VRAM) - req.flags |= NOUVEAU_MEM_FB; - if (flags & NOUVEAU_BO_GART) - req.flags |= NOUVEAU_MEM_AGP; - - ret = drmCommandWrite(nvdev->fd, DRM_NOUVEAU_MEM_TILE, - &req, sizeof(req)); - } - - return 0; -} - -int nouveau_bo_busy(struct nouveau_bo *bo, uint32_t access) { - struct nouveau_device_priv *nvdev = nouveau_device(bo->device); - struct nouveau_bo_priv *nvbo = nouveau_bo(bo); - - if (!nvdev->mm_enabled) { - struct nouveau_fence *fence; - - if (nvbo->pending && (nvbo->pending->write_domains || - (access & NOUVEAU_BO_WR))) - return 1; - - if (access & NOUVEAU_BO_WR) - fence = nvbo->fence; - else - fence = nvbo->wr_fence; - return !nouveau_fence(fence)->signalled; - } - - return 1; + return nouveau_bo_wait(bo, (access & NOUVEAU_BO_WR), 1, 1); } struct drm_nouveau_gem_pushbuf_bo * @@ -909,7 +583,7 @@ nouveau_bo_emit_buffer(struct nouveau_channel *chan, struct nouveau_bo *bo) } } - if (nvpb->nr_buffers >= NOUVEAU_PUSHBUF_MAX_BUFFERS) + if (nvpb->nr_buffers >= NOUVEAU_GEM_MAX_BUFFERS) return NULL; pbbo = nvpb->buffers + nvpb->nr_buffers++; nvbo->pending = pbbo; diff --git a/libdrm/nouveau/nouveau_bo.h b/libdrm/nouveau/nouveau_bo.h index 9b1feff..97ad2d7 100644 --- a/libdrm/nouveau/nouveau_bo.h +++ b/libdrm/nouveau/nouveau_bo.h @@ -72,10 +72,6 @@ nouveau_bo_user(struct nouveau_device *, void *ptr, int size, struct nouveau_bo **); int -nouveau_bo_fake(struct nouveau_device *dev, uint64_t offset, uint32_t flags, - uint32_t size, void *map, struct nouveau_bo **); - -int nouveau_bo_wrap(struct nouveau_device *, uint32_t handle, struct nouveau_bo **); int @@ -108,10 +104,6 @@ void nouveau_bo_unpin(struct nouveau_bo *); int -nouveau_bo_tile(struct nouveau_bo *, uint32_t flags, uint32_t delta, - uint32_t size); - -int nouveau_bo_busy(struct nouveau_bo *, uint32_t access); #endif diff --git a/libdrm/nouveau/nouveau_channel.c b/libdrm/nouveau/nouveau_channel.c index 5de27dc..674c5c3 100644 --- a/libdrm/nouveau/nouveau_channel.c +++ b/libdrm/nouveau/nouveau_channel.c @@ -74,8 +74,10 @@ nouveau_channel_alloc(struct nouveau_device *dev, uint32_t fb_ctxdma, nvchan->base.subc[i].gr = &gr->base; } - ret = drmMap(nvdev->fd, nvchan->drm.notifier, nvchan->drm.notifier_size, - (drmAddressPtr)&nvchan->notifier_block); + ret = nouveau_bo_wrap(dev, nvchan->drm.notifier_handle, + &nvchan->notifier_bo); + if (!ret) + ret = nouveau_bo_map(nvchan->notifier_bo, NOUVEAU_BO_RDWR); if (ret) { nouveau_channel_free((void *)&nvchan); return ret; @@ -88,49 +90,8 @@ nouveau_channel_alloc(struct nouveau_device *dev, uint32_t fb_ctxdma, return ret; } - if (!nvdev->mm_enabled) { - ret = drmMap(nvdev->fd, nvchan->drm.ctrl, nvchan->drm.ctrl_size, - (void*)&nvchan->user); - if (ret) { - nouveau_channel_free((void *)&nvchan); - return ret; - } - nvchan->put = &nvchan->user[0x40/4]; - nvchan->get = &nvchan->user[0x44/4]; - nvchan->ref_cnt = &nvchan->user[0x48/4]; - - ret = drmMap(nvdev->fd, nvchan->drm.cmdbuf, - nvchan->drm.cmdbuf_size, (void*)&nvchan->pushbuf); - if (ret) { - nouveau_channel_free((void *)&nvchan); - return ret; - } - - nouveau_dma_channel_init(&nvchan->base); - } - nouveau_pushbuf_init(&nvchan->base); - if (!nvdev->mm_enabled && dev->chipset < 0x10) { - ret = nouveau_grobj_alloc(&nvchan->base, 0xbeef3904, 0x5039, - &nvchan->fence_grobj); - if (ret) { - nouveau_channel_free((void *)&nvchan); - return ret; - } - - ret = nouveau_notifier_alloc(&nvchan->base, 0xbeef3905, 1, - &nvchan->fence_ntfy); - if (ret) { - nouveau_channel_free((void *)&nvchan); - return ret; - } - - BEGIN_RING(&nvchan->base, nvchan->fence_grobj, 0x0180, 1); - OUT_RING (&nvchan->base, nvchan->fence_ntfy->handle); - nvchan->fence_grobj->bound = NOUVEAU_GROBJ_BOUND_EXPLICIT; - } - *chan = &nvchan->base; return 0; } @@ -147,28 +108,15 @@ nouveau_channel_free(struct nouveau_channel **chan) nvchan = nouveau_channel(*chan); *chan = NULL; nvdev = nouveau_device(nvchan->base.device); - - FIRE_RING(&nvchan->base); - - if (!nvdev->mm_enabled) { - struct nouveau_fence *fence = NULL; - /* Make sure all buffer objects on delayed delete queue - * actually get freed. - */ - nouveau_fence_new(&nvchan->base, &fence); - nouveau_fence_emit(fence); - nouveau_fence_wait(&fence); - } + FIRE_RING(&nvchan->base); - if (nvchan->notifier_block) - drmUnmap(nvchan->notifier_block, nvchan->drm.notifier_size); + nouveau_bo_unmap(nvchan->notifier_bo); + nouveau_bo_ref(NULL, &nvchan->notifier_bo); nouveau_grobj_free(&nvchan->base.vram); nouveau_grobj_free(&nvchan->base.gart); nouveau_grobj_free(&nvchan->base.nullobj); - nouveau_grobj_free(&nvchan->fence_grobj); - nouveau_notifier_free(&nvchan->fence_ntfy); cf.channel = nvchan->drm.channel; drmCommandWrite(nvdev->fd, DRM_NOUVEAU_CHANNEL_FREE, &cf, sizeof(cf)); diff --git a/libdrm/nouveau/nouveau_class.h b/libdrm/nouveau/nouveau_class.h index 3df3d7b..4d1c509 100644 --- a/libdrm/nouveau/nouveau_class.h +++ b/libdrm/nouveau/nouveau_class.h @@ -6564,6 +6564,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV40TCL_BLEND_FUNC_DST_ALPHA_CONSTANT_ALPHA 0x80030000 #define NV40TCL_BLEND_FUNC_DST_ALPHA_ONE_MINUS_CONSTANT_ALPHA 0x80040000 #define NV40TCL_BLEND_COLOR 0x0000031c +#define NV40TCL_BLEND_COLOR_B_SHIFT 0 +#define NV40TCL_BLEND_COLOR_B_MASK 0x000000ff +#define NV40TCL_BLEND_COLOR_G_SHIFT 8 +#define NV40TCL_BLEND_COLOR_G_MASK 0x0000ff00 +#define NV40TCL_BLEND_COLOR_R_SHIFT 16 +#define NV40TCL_BLEND_COLOR_R_MASK 0x00ff0000 +#define NV40TCL_BLEND_COLOR_A_SHIFT 24 +#define NV40TCL_BLEND_COLOR_A_MASK 0xff000000 #define NV40TCL_BLEND_EQUATION 0x00000320 #define NV40TCL_BLEND_EQUATION_RGB_SHIFT 0 #define NV40TCL_BLEND_EQUATION_RGB_MASK 0x0000ffff @@ -6778,6 +6786,25 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV40TCL_VTX_ATTR_3I_Z__SIZE 0x00000010 #define NV40TCL_VTX_ATTR_3I_Z_Z_SHIFT 0 #define NV40TCL_VTX_ATTR_3I_Z_Z_MASK 0x0000ffff +#define NV40TCL_TEX_FILTER_OPTIMIZATION 0x00000b00 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_SHIFT 0 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_MASK 0x0000001f +#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_OFF 0x00000000 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_HIGH_QUALITY 0x00000004 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_QUALITY 0x00000006 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_PERFORMANCE 0x00000008 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_TRILINEAR_HIGH_PERFORMANCE 0x00000018 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_SHIFT 6 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_MASK 0x000001c0 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_OFF 0x00000000 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_HIGH_QUALITY 0x000000c0 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_QUALITY 0x000001c0 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_ANISO_SAMPLE_PERFORMANCE 0x00000140 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_SHIFT 10 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_MASK 0x00007c00 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_OFF 0x00000000 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_PARTIAL 0x00002c00 +#define NV40TCL_TEX_FILTER_OPTIMIZATION_UNKNOWN_FULL 0x00007c00 #define NV40TCL_UNK0B40(x) (0x00000b40+((x)*4)) #define NV40TCL_UNK0B40__SIZE 0x00000008 #define NV40TCL_VP_UPLOAD_INST(x) (0x00000b80+((x)*4)) @@ -6951,7 +6978,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV40TCL_TEX_WRAP(x) (0x00001a08+((x)*32)) #define NV40TCL_TEX_WRAP__SIZE 0x00000010 #define NV40TCL_TEX_WRAP_S_SHIFT 0 -#define NV40TCL_TEX_WRAP_S_MASK 0x000000ff +#define NV40TCL_TEX_WRAP_S_MASK 0x0000000f #define NV40TCL_TEX_WRAP_S_REPEAT 0x00000001 #define NV40TCL_TEX_WRAP_S_MIRRORED_REPEAT 0x00000002 #define NV40TCL_TEX_WRAP_S_CLAMP_TO_EDGE 0x00000003 @@ -6960,6 +6987,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_EDGE 0x00000006 #define NV40TCL_TEX_WRAP_S_MIRROR_CLAMP_TO_BORDER 0x00000007 #define NV40TCL_TEX_WRAP_S_MIRROR_CLAMP 0x00000008 +#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_SHIFT 4 +#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_MASK 0x00000070 +#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_OFF 0x00000000 +#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_QUALITY 0x00000020 +#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_PERFORMANCE 0x00000030 +#define NV40TCL_TEX_WRAP_ANISO_MIP_FILTER_OPTIMIZATION_HIGH_PERFORMANCE 0x00000070 #define NV40TCL_TEX_WRAP_T_SHIFT 8 #define NV40TCL_TEX_WRAP_T_MASK 0x00000f00 #define NV40TCL_TEX_WRAP_T_REPEAT 0x00000100 @@ -6973,7 +7006,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV40TCL_TEX_WRAP_EXPAND_NORMAL_SHIFT 12 #define NV40TCL_TEX_WRAP_EXPAND_NORMAL_MASK 0x0000f000 #define NV40TCL_TEX_WRAP_R_SHIFT 16 -#define NV40TCL_TEX_WRAP_R_MASK 0x00ff0000 +#define NV40TCL_TEX_WRAP_R_MASK 0x000f0000 #define NV40TCL_TEX_WRAP_R_REPEAT 0x00010000 #define NV40TCL_TEX_WRAP_R_MIRRORED_REPEAT 0x00020000 #define NV40TCL_TEX_WRAP_R_CLAMP_TO_EDGE 0x00030000 @@ -6982,6 +7015,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV40TCL_TEX_WRAP_R_MIRROR_CLAMP_TO_EDGE 0x00060000 #define NV40TCL_TEX_WRAP_R_MIRROR_CLAMP_TO_BORDER 0x00070000 #define NV40TCL_TEX_WRAP_R_MIRROR_CLAMP 0x00080000 +#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_SHIFT 20 +#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_MASK 0x00f00000 +#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_NONE 0x00000000 +#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_RED 0x00100000 +#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_GREEN 0x00200000 +#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_BLUE 0x00400000 +#define NV40TCL_TEX_WRAP_GAMMA_DECREASE_FILTER_ALL 0x00f00000 #define NV40TCL_TEX_WRAP_RCOMP_SHIFT 28 #define NV40TCL_TEX_WRAP_RCOMP_MASK 0xf0000000 #define NV40TCL_TEX_WRAP_RCOMP_NEVER 0x00000000 @@ -7150,22 +7190,74 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50_2D_DMA_IN_MEMORY1 0x00000188 #define NV50_2D_DMA_IN_MEMORY2 0x0000018c #define NV50_2D_DST_FORMAT 0x00000200 -#define NV50_2D_DST_FORMAT_32BPP 0x000000cf -#define NV50_2D_DST_FORMAT_24BPP 0x000000e6 -#define NV50_2D_DST_FORMAT_16BPP 0x000000e8 -#define NV50_2D_DST_FORMAT_8BPP 0x000000f3 -#define NV50_2D_DST_FORMAT_15BPP 0x000000f8 +#define NV50_2D_DST_FORMAT_R32G32B32A32_FLOAT 0x000000c0 +#define NV50_2D_DST_FORMAT_R32G32B32_FLOAT 0x000000c3 +#define NV50_2D_DST_FORMAT_R16G16B16A16_UNORM 0x000000c6 +#define NV50_2D_DST_FORMAT_R16G16B16A16_SNORM 0x000000c7 +#define NV50_2D_DST_FORMAT_R16G16B16A16_FLOAT 0x000000ca +#define NV50_2D_DST_FORMAT_R32G32_FLOAT 0x000000cb +#define NV50_2D_DST_FORMAT_R16G16B16X16_FLOAT 0x000000ce +#define NV50_2D_DST_FORMAT_A8R8G8B8_UNORM 0x000000cf +#define NV50_2D_DST_FORMAT_A2B10G10R10_UNORM 0x000000d1 +#define NV50_2D_DST_FORMAT_A8B8G8R8_UNORM 0x000000d6 +#define NV50_2D_DST_FORMAT_A8B8G8R8_SNORM 0x000000d7 +#define NV50_2D_DST_FORMAT_R16G16_UNORM 0x000000da +#define NV50_2D_DST_FORMAT_R16G16_SNORM 0x000000db +#define NV50_2D_DST_FORMAT_R16G16_FLOAT 0x000000de +#define NV50_2D_DST_FORMAT_A2R10G10B10_UNORM 0x000000df +#define NV50_2D_DST_FORMAT_B10G11R11_FLOAT 0x000000e0 +#define NV50_2D_DST_FORMAT_R32_FLOAT 0x000000e5 +#define NV50_2D_DST_FORMAT_X8R8G8B8_UNORM 0x000000e6 +#define NV50_2D_DST_FORMAT_R5G6B5_UNORM 0x000000e8 +#define NV50_2D_DST_FORMAT_R16_FLOAT 0x000000e9 +#define NV50_2D_DST_FORMAT_R8G8_UNORM 0x000000ea +#define NV50_2D_DST_FORMAT_R8G8_SNORM 0x000000eb +#define NV50_2D_DST_FORMAT_R16_UNORM 0x000000ee +#define NV50_2D_DST_FORMAT_R16_SNORM 0x000000ef +#define NV50_2D_DST_FORMAT_R8_UNORM 0x000000f3 +#define NV50_2D_DST_FORMAT_R32_BOOLEAN 0x000000f6 +#define NV50_2D_DST_FORMAT_A8_UNORM 0x000000f7 +#define NV50_2D_DST_FORMAT_X1B5G5R5_UNORM 0x000000f8 +#define NV50_2D_DST_FORMAT_X8B8G8R8_UNORM 0x000000f9 +#define NV50_2D_DST_LINEAR 0x00000204 +#define NV50_2D_DST_TILE_MODE 0x00000208 #define NV50_2D_DST_PITCH 0x00000214 #define NV50_2D_DST_WIDTH 0x00000218 #define NV50_2D_DST_HEIGHT 0x0000021c #define NV50_2D_DST_ADDRESS_HIGH 0x00000220 #define NV50_2D_DST_ADDRESS_LOW 0x00000224 #define NV50_2D_SRC_FORMAT 0x00000230 -#define NV50_2D_SRC_FORMAT_32BPP 0x000000cf -#define NV50_2D_SRC_FORMAT_24BPP 0x000000e6 -#define NV50_2D_SRC_FORMAT_16BPP 0x000000e8 -#define NV50_2D_SRC_FORMAT_8BPP 0x000000f3 -#define NV50_2D_SRC_FORMAT_15BPP 0x000000f8 +#define NV50_2D_SRC_FORMAT_R32G32B32A32_FLOAT 0x000000c0 +#define NV50_2D_SRC_FORMAT_R32G32B32_FLOAT 0x000000c3 +#define NV50_2D_SRC_FORMAT_R16G16B16A16_UNORM 0x000000c6 +#define NV50_2D_SRC_FORMAT_R16G16B16A16_SNORM 0x000000c7 +#define NV50_2D_SRC_FORMAT_R16G16B16A16_FLOAT 0x000000ca +#define NV50_2D_SRC_FORMAT_R32G32_FLOAT 0x000000cb +#define NV50_2D_SRC_FORMAT_R16G16B16X16_FLOAT 0x000000ce +#define NV50_2D_SRC_FORMAT_A8R8G8B8_UNORM 0x000000cf +#define NV50_2D_SRC_FORMAT_A2B10G10R10_UNORM 0x000000d1 +#define NV50_2D_SRC_FORMAT_A8B8G8R8_UNORM 0x000000d6 +#define NV50_2D_SRC_FORMAT_A8B8G8R8_SNORM 0x000000d7 +#define NV50_2D_SRC_FORMAT_R16G16_UNORM 0x000000da +#define NV50_2D_SRC_FORMAT_R16G16_SNORM 0x000000db +#define NV50_2D_SRC_FORMAT_R16G16_FLOAT 0x000000de +#define NV50_2D_SRC_FORMAT_A2R10G10B10_UNORM 0x000000df +#define NV50_2D_SRC_FORMAT_B10G11R11_FLOAT 0x000000e0 +#define NV50_2D_SRC_FORMAT_R32_FLOAT 0x000000e5 +#define NV50_2D_SRC_FORMAT_X8R8G8B8_UNORM 0x000000e6 +#define NV50_2D_SRC_FORMAT_R5G6B5_UNORM 0x000000e8 +#define NV50_2D_SRC_FORMAT_R16_FLOAT 0x000000e9 +#define NV50_2D_SRC_FORMAT_R8G8_UNORM 0x000000ea +#define NV50_2D_SRC_FORMAT_R8G8_SNORM 0x000000eb +#define NV50_2D_SRC_FORMAT_R16_UNORM 0x000000ee +#define NV50_2D_SRC_FORMAT_R16_SNORM 0x000000ef +#define NV50_2D_SRC_FORMAT_R8_UNORM 0x000000f3 +#define NV50_2D_SRC_FORMAT_R32_BOOLEAN 0x000000f6 +#define NV50_2D_SRC_FORMAT_A8_UNORM 0x000000f7 +#define NV50_2D_SRC_FORMAT_X1B5G5R5_UNORM 0x000000f8 +#define NV50_2D_SRC_FORMAT_X8B8G8R8_UNORM 0x000000f9 +#define NV50_2D_SRC_LINEAR 0x00000234 +#define NV50_2D_SRC_TILE_MODE 0x00000238 #define NV50_2D_SRC_PITCH 0x00000244 #define NV50_2D_SRC_WIDTH 0x00000248 #define NV50_2D_SRC_HEIGHT 0x0000024c @@ -7193,11 +7285,35 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50_2D_PATTERN_BITMAP(x) (0x000002f8+((x)*4)) #define NV50_2D_PATTERN_BITMAP__SIZE 0x00000002 #define NV50_2D_RECT_FORMAT 0x00000584 -#define NV50_2D_RECT_FORMAT_32BPP 0x000000cf -#define NV50_2D_RECT_FORMAT_24BPP 0x000000e6 -#define NV50_2D_RECT_FORMAT_16BPP 0x000000e8 -#define NV50_2D_RECT_FORMAT_8BPP 0x000000f3 -#define NV50_2D_RECT_FORMAT_15BPP 0x000000f8 +#define NV50_2D_RECT_FORMAT_R32G32B32A32_FLOAT 0x000000c0 +#define NV50_2D_RECT_FORMAT_R32G32B32_FLOAT 0x000000c3 +#define NV50_2D_RECT_FORMAT_R16G16B16A16_UNORM 0x000000c6 +#define NV50_2D_RECT_FORMAT_R16G16B16A16_SNORM 0x000000c7 +#define NV50_2D_RECT_FORMAT_R16G16B16A16_FLOAT 0x000000ca +#define NV50_2D_RECT_FORMAT_R32G32_FLOAT 0x000000cb +#define NV50_2D_RECT_FORMAT_R16G16B16X16_FLOAT 0x000000ce +#define NV50_2D_RECT_FORMAT_A8R8G8B8_UNORM 0x000000cf +#define NV50_2D_RECT_FORMAT_A2B10G10R10_UNORM 0x000000d1 +#define NV50_2D_RECT_FORMAT_A8B8G8R8_UNORM 0x000000d6 +#define NV50_2D_RECT_FORMAT_A8B8G8R8_SNORM 0x000000d7 +#define NV50_2D_RECT_FORMAT_R16G16_UNORM 0x000000da +#define NV50_2D_RECT_FORMAT_R16G16_SNORM 0x000000db +#define NV50_2D_RECT_FORMAT_R16G16_FLOAT 0x000000de +#define NV50_2D_RECT_FORMAT_A2R10G10B10_UNORM 0x000000df +#define NV50_2D_RECT_FORMAT_B10G11R11_FLOAT 0x000000e0 +#define NV50_2D_RECT_FORMAT_R32_FLOAT 0x000000e5 +#define NV50_2D_RECT_FORMAT_X8R8G8B8_UNORM 0x000000e6 +#define NV50_2D_RECT_FORMAT_R5G6B5_UNORM 0x000000e8 +#define NV50_2D_RECT_FORMAT_R16_FLOAT 0x000000e9 +#define NV50_2D_RECT_FORMAT_R8G8_UNORM 0x000000ea +#define NV50_2D_RECT_FORMAT_R8G8_SNORM 0x000000eb +#define NV50_2D_RECT_FORMAT_R16_UNORM 0x000000ee +#define NV50_2D_RECT_FORMAT_R16_SNORM 0x000000ef +#define NV50_2D_RECT_FORMAT_R8_UNORM 0x000000f3 +#define NV50_2D_RECT_FORMAT_R32_BOOLEAN 0x000000f6 +#define NV50_2D_RECT_FORMAT_A8_UNORM 0x000000f7 +#define NV50_2D_RECT_FORMAT_X1B5G5R5_UNORM 0x000000f8 +#define NV50_2D_RECT_FORMAT_X8B8G8R8_UNORM 0x000000f9 #define NV50_2D_RECT_COLOR 0x00000588 #define NV50_2D_RECT_X1 0x00000600 #define NV50_2D_RECT_Y1 0x00000604 @@ -7205,11 +7321,35 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50_2D_RECT_Y2 0x0000060c #define NV50_2D_SIFC_UNK0800 0x00000800 #define NV50_2D_SIFC_FORMAT 0x00000804 -#define NV50_2D_SIFC_FORMAT_32BPP 0x000000cf -#define NV50_2D_SIFC_FORMAT_24BPP 0x000000e6 -#define NV50_2D_SIFC_FORMAT_16BPP 0x000000e8 -#define NV50_2D_SIFC_FORMAT_8BPP 0x000000f3 -#define NV50_2D_SIFC_FORMAT_15BPP 0x000000f8 +#define NV50_2D_SIFC_FORMAT_R32G32B32A32_FLOAT 0x000000c0 +#define NV50_2D_SIFC_FORMAT_R32G32B32_FLOAT 0x000000c3 +#define NV50_2D_SIFC_FORMAT_R16G16B16A16_UNORM 0x000000c6 +#define NV50_2D_SIFC_FORMAT_R16G16B16A16_SNORM 0x000000c7 +#define NV50_2D_SIFC_FORMAT_R16G16B16A16_FLOAT 0x000000ca +#define NV50_2D_SIFC_FORMAT_R32G32_FLOAT 0x000000cb +#define NV50_2D_SIFC_FORMAT_R16G16B16X16_FLOAT 0x000000ce +#define NV50_2D_SIFC_FORMAT_A8R8G8B8_UNORM 0x000000cf +#define NV50_2D_SIFC_FORMAT_A2B10G10R10_UNORM 0x000000d1 +#define NV50_2D_SIFC_FORMAT_A8B8G8R8_UNORM 0x000000d6 +#define NV50_2D_SIFC_FORMAT_A8B8G8R8_SNORM 0x000000d7 +#define NV50_2D_SIFC_FORMAT_R16G16_UNORM 0x000000da +#define NV50_2D_SIFC_FORMAT_R16G16_SNORM 0x000000db +#define NV50_2D_SIFC_FORMAT_R16G16_FLOAT 0x000000de +#define NV50_2D_SIFC_FORMAT_A2R10G10B10_UNORM 0x000000df +#define NV50_2D_SIFC_FORMAT_B10G11R11_FLOAT 0x000000e0 +#define NV50_2D_SIFC_FORMAT_R32_FLOAT 0x000000e5 +#define NV50_2D_SIFC_FORMAT_X8R8G8B8_UNORM 0x000000e6 +#define NV50_2D_SIFC_FORMAT_R5G6B5_UNORM 0x000000e8 +#define NV50_2D_SIFC_FORMAT_R16_FLOAT 0x000000e9 +#define NV50_2D_SIFC_FORMAT_R8G8_UNORM 0x000000ea +#define NV50_2D_SIFC_FORMAT_R8G8_SNORM 0x000000eb +#define NV50_2D_SIFC_FORMAT_R16_UNORM 0x000000ee +#define NV50_2D_SIFC_FORMAT_R16_SNORM 0x000000ef +#define NV50_2D_SIFC_FORMAT_R8_UNORM 0x000000f3 +#define NV50_2D_SIFC_FORMAT_R32_BOOLEAN 0x000000f6 +#define NV50_2D_SIFC_FORMAT_A8_UNORM 0x000000f7 +#define NV50_2D_SIFC_FORMAT_X1B5G5R5_UNORM 0x000000f8 +#define NV50_2D_SIFC_FORMAT_X8B8G8R8_UNORM 0x000000f9 #define NV50_2D_SIFC_WIDTH 0x00000838 #define NV50_2D_SIFC_HEIGHT 0x0000083c #define NV50_2D_SIFC_SCALE_UNK0840 0x00000840 @@ -7231,8 +7371,24 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 +#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_IN 0x00000200 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_IN 0x00000204 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_IN 0x00000208 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_IN 0x0000020c +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_IN 0x00000218 +#define NV50_MEMORY_TO_MEMORY_FORMAT_LINEAR_OUT 0x0000021c +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_MODE_OUT 0x00000220 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_PITCH_OUT 0x00000224 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_HEIGHT_OUT 0x00000228 +#define NV50_MEMORY_TO_MEMORY_FORMAT_TILING_POSITION_OUT 0x00000234 #define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 #define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c +#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c +#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT 0x00000310 +#define NV50_MEMORY_TO_MEMORY_FORMAT_PITCH_IN 0x00000314 +#define NV50_MEMORY_TO_MEMORY_FORMAT_PITCH_OUT 0x00000318 +#define NV50_MEMORY_TO_MEMORY_FORMAT_LINE_LENGTH_IN 0x0000031c +#define NV50_MEMORY_TO_MEMORY_FORMAT_LINE_COUNT 0x00000320 #define NV50TCL 0x00005097 @@ -7250,13 +7406,37 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50TCL_RT_ADDRESS_LOW__SIZE 0x00000008 #define NV50TCL_RT_FORMAT(x) (0x00000208+((x)*32)) #define NV50TCL_RT_FORMAT__SIZE 0x00000008 -#define NV50TCL_RT_FORMAT_32BPP 0x000000cf -#define NV50TCL_RT_FORMAT_24BPP 0x000000e6 -#define NV50TCL_RT_FORMAT_16BPP 0x000000e8 -#define NV50TCL_RT_FORMAT_8BPP 0x000000f3 -#define NV50TCL_RT_FORMAT_15BPP 0x000000f8 -#define NV50TCL_RT_TILE_UNK(x) (0x0000020c+((x)*32)) -#define NV50TCL_RT_TILE_UNK__SIZE 0x00000008 +#define NV50TCL_RT_FORMAT_R32G32B32A32_FLOAT 0x000000c0 +#define NV50TCL_RT_FORMAT_R32G32B32_FLOAT 0x000000c3 +#define NV50TCL_RT_FORMAT_R16G16B16A16_UNORM 0x000000c6 +#define NV50TCL_RT_FORMAT_R16G16B16A16_SNORM 0x000000c7 +#define NV50TCL_RT_FORMAT_R16G16B16A16_FLOAT 0x000000ca +#define NV50TCL_RT_FORMAT_R32G32_FLOAT 0x000000cb +#define NV50TCL_RT_FORMAT_R16G16B16X16_FLOAT 0x000000ce +#define NV50TCL_RT_FORMAT_A8R8G8B8_UNORM 0x000000cf +#define NV50TCL_RT_FORMAT_A2B10G10R10_UNORM 0x000000d1 +#define NV50TCL_RT_FORMAT_A8B8G8R8_UNORM 0x000000d6 +#define NV50TCL_RT_FORMAT_A8B8G8R8_SNORM 0x000000d7 +#define NV50TCL_RT_FORMAT_R16G16_UNORM 0x000000da +#define NV50TCL_RT_FORMAT_R16G16_SNORM 0x000000db +#define NV50TCL_RT_FORMAT_R16G16_FLOAT 0x000000de +#define NV50TCL_RT_FORMAT_A2R10G10B10_UNORM 0x000000df +#define NV50TCL_RT_FORMAT_B10G11R11_FLOAT 0x000000e0 +#define NV50TCL_RT_FORMAT_R32_FLOAT 0x000000e5 +#define NV50TCL_RT_FORMAT_X8R8G8B8_UNORM 0x000000e6 +#define NV50TCL_RT_FORMAT_R5G6B5_UNORM 0x000000e8 +#define NV50TCL_RT_FORMAT_R16_FLOAT 0x000000e9 +#define NV50TCL_RT_FORMAT_R8G8_UNORM 0x000000ea +#define NV50TCL_RT_FORMAT_R8G8_SNORM 0x000000eb +#define NV50TCL_RT_FORMAT_R16_UNORM 0x000000ee +#define NV50TCL_RT_FORMAT_R16_SNORM 0x000000ef +#define NV50TCL_RT_FORMAT_R8_UNORM 0x000000f3 +#define NV50TCL_RT_FORMAT_R32_BOOLEAN 0x000000f6 +#define NV50TCL_RT_FORMAT_A8_UNORM 0x000000f7 +#define NV50TCL_RT_FORMAT_X1B5G5R5_UNORM 0x000000f8 +#define NV50TCL_RT_FORMAT_X8B8G8R8_UNORM 0x000000f9 +#define NV50TCL_RT_TILE_MODE(x) (0x0000020c+((x)*32)) +#define NV50TCL_RT_TILE_MODE__SIZE 0x00000008 #define NV50TCL_RT_UNK4(x) (0x00000210+((x)*32)) #define NV50TCL_RT_UNK4__SIZE 0x00000008 #define NV50TCL_VTX_ATTR_1F(x) (0x00000300+((x)*4)) @@ -7313,10 +7493,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50TCL_VTX_ATTR_4NI_1_W_MASK 0xffff0000 #define NV50TCL_VERTEX_ARRAY_FORMAT(x) (0x00000900+((x)*16)) #define NV50TCL_VERTEX_ARRAY_FORMAT__SIZE 0x00000010 -#define NV50TCL_VIEWPORT_UNK0(x) (0x00000a00+((x)*4)) -#define NV50TCL_VIEWPORT_UNK0__SIZE 0x00000003 -#define NV50TCL_VIEWPORT_UNK1(x) (0x00000a0c+((x)*4)) -#define NV50TCL_VIEWPORT_UNK1__SIZE 0x00000003 +#define NV50TCL_VERTEX_ARRAY_FORMAT_STRIDE_SHIFT 0 +#define NV50TCL_VERTEX_ARRAY_FORMAT_STRIDE_MASK 0x000000ff +#define NV50TCL_UNK0904_OFFSET_HIGH(x) (0x00000904+((x)*16)) +#define NV50TCL_UNK0904_OFFSET_HIGH__SIZE 0x00000010 +#define NV50TCL_UNK0904_OFFSET_LOW(x) (0x00000908+((x)*16)) +#define NV50TCL_UNK0904_OFFSET_LOW__SIZE 0x00000010 +#define NV50TCL_VIEWPORT_SCALE(x) (0x00000a00+((x)*4)) +#define NV50TCL_VIEWPORT_SCALE__SIZE 0x00000003 +#define NV50TCL_VIEWPORT_TRANSLATE(x) (0x00000a0c+((x)*4)) +#define NV50TCL_VIEWPORT_TRANSLATE__SIZE 0x00000003 #define NV50TCL_VIEWPORT_HORIZ 0x00000c00 #define NV50TCL_VIEWPORT_HORIZ_X_SHIFT 0 #define NV50TCL_VIEWPORT_HORIZ_X_MASK 0x0000ffff @@ -7339,6 +7525,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50TCL_CLEAR_COLOR__SIZE 0x00000004 #define NV50TCL_CLEAR_DEPTH 0x00000d90 #define NV50TCL_CLEAR_STENCIL 0x00000da0 +#define NV50TCL_STRMOUT_UNK0DA8 0x00000da8 #define NV50TCL_POLYGON_MODE_FRONT 0x00000dac #define NV50TCL_POLYGON_MODE_FRONT_POINT 0x00001b00 #define NV50TCL_POLYGON_MODE_FRONT_LINE 0x00001b01 @@ -7351,16 +7538,19 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50TCL_POLYGON_OFFSET_POINT_ENABLE 0x00000dc0 #define NV50TCL_POLYGON_OFFSET_LINE_ENABLE 0x00000dc4 #define NV50TCL_POLYGON_OFFSET_FILL_ENABLE 0x00000dc8 +#define NV50TCL_WINDOW_LEFT 0x00000df8 +#define NV50TCL_WINDOW_BOTTOM 0x00000dfc +#define NV50TCL_SCISSOR_ENABLE 0x00000e00 #define NV50TCL_SCISSOR_HORIZ 0x00000e04 #define NV50TCL_SCISSOR_HORIZ_L_SHIFT 0 #define NV50TCL_SCISSOR_HORIZ_L_MASK 0x0000ffff #define NV50TCL_SCISSOR_HORIZ_R_SHIFT 16 #define NV50TCL_SCISSOR_HORIZ_R_MASK 0xffff0000 #define NV50TCL_SCISSOR_VERT 0x00000e08 -#define NV50TCL_SCISSOR_VERT_T_SHIFT 0 -#define NV50TCL_SCISSOR_VERT_T_MASK 0x0000ffff -#define NV50TCL_SCISSOR_VERT_B_SHIFT 16 -#define NV50TCL_SCISSOR_VERT_B_MASK 0xffff0000 +#define NV50TCL_SCISSOR_VERT_B_SHIFT 0 +#define NV50TCL_SCISSOR_VERT_B_MASK 0x0000ffff +#define NV50TCL_SCISSOR_VERT_T_SHIFT 16 +#define NV50TCL_SCISSOR_VERT_T_MASK 0xffff0000 #define NV50TCL_CB_ADDR 0x00000f00 #define NV50TCL_CB_ADDR_ID_SHIFT 8 #define NV50TCL_CB_ADDR_ID_MASK 0xffffff00 @@ -7375,16 +7565,40 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50TCL_GP_ADDRESS_LOW 0x00000f74 #define NV50TCL_VP_ADDRESS_HIGH 0x00000f7c #define NV50TCL_VP_ADDRESS_LOW 0x00000f80 +#define NV50TCL_UNK0F84_ADDRESS_HIGH 0x00000f84 +#define NV50TCL_UNK0F84_ADDRESS_LOW 0x00000f88 +#define NV50TCL_DEPTH_BOUNDS(x) (0x00000f9c+((x)*4)) +#define NV50TCL_DEPTH_BOUNDS__SIZE 0x00000002 #define NV50TCL_FP_ADDRESS_HIGH 0x00000fa4 #define NV50TCL_FP_ADDRESS_LOW 0x00000fa8 +#define NV50TCL_MSAA_MASK(x) (0x00000fbc+((x)*4)) +#define NV50TCL_MSAA_MASK__SIZE 0x00000004 #define NV50TCL_ZETA_ADDRESS_HIGH 0x00000fe0 #define NV50TCL_ZETA_ADDRESS_LOW 0x00000fe4 -#define NV50TCL_UNKFF4 0x00000ff4 -#define NV50TCL_UNKFF4_W_SHIFT 16 -#define NV50TCL_UNKFF4_W_MASK 0xffff0000 -#define NV50TCL_UNKFF8 0x00000ff8 -#define NV50TCL_UNKFF8_H_SHIFT 16 -#define NV50TCL_UNKFF8_H_MASK 0xffff0000 +#define NV50TCL_ZETA_FORMAT 0x00000fe8 +#define NV50TCL_ZETA_FORMAT_Z32_FLOAT 0x0000000a +#define NV50TCL_ZETA_FORMAT_Z24S8_UNORM 0x00000014 +#define NV50TCL_ZETA_FORMAT_X8Z24_UNORM 0x00000015 +#define NV50TCL_ZETA_FORMAT_S8Z24_UNORM 0x00000016 +#define NV50TCL_ZETA_FORMAT_Z32_FLOAT_X24S8_UNORM 0x00000019 +#define NV50TCL_ZETA_TILE_MODE 0x00000fec +#define NV50TCL_ZETA_UNK 0x00000ff0 +#define NV50TCL_SCREEN_SCISSOR_HORIZ 0x00000ff4 +#define NV50TCL_SCREEN_SCISSOR_HORIZ_W_SHIFT 16 +#define NV50TCL_SCREEN_SCISSOR_HORIZ_W_MASK 0xffff0000 +#define NV50TCL_SCREEN_SCISSOR_HORIZ_X_SHIFT 0 +#define NV50TCL_SCREEN_SCISSOR_HORIZ_X_MASK 0x0000ffff +#define NV50TCL_SCREEN_SCISSOR_VERT 0x00000ff8 +#define NV50TCL_SCREEN_SCISSOR_VERT_H_SHIFT 16 +#define NV50TCL_SCREEN_SCISSOR_VERT_H_MASK 0xffff0000 +#define NV50TCL_SCREEN_SCISSOR_VERT_Y_SHIFT 0 +#define NV50TCL_SCREEN_SCISSOR_VERT_Y_MASK 0x0000ffff +#define NV50TCL_UNK1080_OFFSET_HIGH(x) (0x00001080+((x)*8)) +#define NV50TCL_UNK1080_OFFSET_HIGH__SIZE 0x00000010 +#define NV50TCL_UNK1080_OFFSET_LOW(x) (0x00001084+((x)*8)) +#define NV50TCL_UNK1080_OFFSET_LOW__SIZE 0x00000010 +#define NV50TCL_ZETA_HORIZ 0x00001228 +#define NV50TCL_ZETA_VERT 0x0000122c #define NV50TCL_RT_HORIZ(x) (0x00001240+((x)*8)) #define NV50TCL_RT_HORIZ__SIZE 0x00000008 #define NV50TCL_RT_VERT(x) (0x00001244+((x)*8)) @@ -7396,6 +7610,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50TCL_CB_DEF_SET_SIZE_MASK 0x0000ffff #define NV50TCL_CB_DEF_SET_BUFFER_SHIFT 16 #define NV50TCL_CB_DEF_SET_BUFFER_MASK 0xffff0000 +#define NV50TCL_STRMOUT_BUFFERS_CTRL 0x00001294 +#define NV50TCL_STRMOUT_BUFFERS_CTRL_INTERLEAVED (1 << 0) +#define NV50TCL_STRMOUT_BUFFERS_CTRL_SEPARATE_SHIFT 4 +#define NV50TCL_STRMOUT_BUFFERS_CTRL_SEPARATE_MASK 0x000000f0 +#define NV50TCL_STRMOUT_BUFFERS_CTRL_STRIDE_SHIFT 8 +#define NV50TCL_STRMOUT_BUFFERS_CTRL_STRIDE_MASK 0x0000ff00 +#define NV50TCL_FP_RESULT_COUNT 0x00001298 #define NV50TCL_DEPTH_TEST_ENABLE 0x000012cc #define NV50TCL_SHADE_MODEL 0x000012d4 #define NV50TCL_SHADE_MODEL_FLAT 0x00001d00 @@ -7544,11 +7765,34 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50TCL_STENCIL_BACK_FUNC_REF 0x00001394 #define NV50TCL_STENCIL_BACK_MASK 0x00001398 #define NV50TCL_STENCIL_BACK_FUNC_MASK 0x0000139c +#define NV50TCL_FRAG_COLOR_CLAMP_EN 0x000013a8 #define NV50TCL_LINE_WIDTH 0x000013b0 +#define NV50TCL_POINT_COORD_REPLACE_MAP(x) (0x000013c0+((x)*4)) +#define NV50TCL_POINT_COORD_REPLACE_MAP__SIZE 0x00000008 #define NV50TCL_VP_START_ID 0x0000140c #define NV50TCL_GP_START_ID 0x00001410 #define NV50TCL_FP_START_ID 0x00001414 +#define NV50TCL_GP_VERTEX_OUTPUT_COUNT 0x00001420 +#define NV50TCL_SET_SAMPLER_TEX 0x00001458 +#define NV50TCL_SET_SAMPLER_TEX_SAMPLER_SHIFT 1 +#define NV50TCL_SET_SAMPLER_TEX_SAMPLER_MASK 0x000001fe +#define NV50TCL_SET_SAMPLER_TEX_TIC_SHIFT 9 +#define NV50TCL_SET_SAMPLER_TEX_TIC_MASK 0x0001fe00 +#define NV50TCL_SET_SAMPLER_TEX_VALID (1 << 0) +#define NV50TCL_STRMOUT_MAP(x) (0x00001480+((x)*4)) +#define NV50TCL_STRMOUT_MAP__SIZE 0x00000020 +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE 0x00001510 +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_0 (1 << 0) +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_1 (1 << 1) +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_2 (1 << 2) +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_3 (1 << 3) +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_4 (1 << 4) +#define NV50TCL_VP_CLIP_DISTANCE_ENABLE_5 (1 << 5) #define NV50TCL_POINT_SIZE 0x00001518 +#define NV50TCL_POINT_SPRITE_ENABLE 0x00001520 +#define NV50TCL_MULTISAMPLE_CTRL 0x0000153c +#define NV50TCL_MULTISAMPLE_CTRL_ALPHA_TO_COVERAGE (1 << 0) +#define NV50TCL_MULTISAMPLE_CTRL_ALPHA_TO_ONE (1 << 4) #define NV50TCL_TSC_ADDRESS_HIGH 0x0000155c #define NV50TCL_TSC_ADDRESS_LOW 0x00001560 #define NV50TCL_POLYGON_OFFSET_FACTOR 0x0000156c @@ -7594,6 +7838,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50TCL_STENCIL_FRONT_FUNC_FUNC_GEQUAL 0x00000206 #define NV50TCL_STENCIL_FRONT_FUNC_FUNC_ALWAYS 0x00000207 #define NV50TCL_POLYGON_OFFSET_UNITS 0x000015bc +#define NV50TCL_MULTISAMPLE_SAMPLES_LOG2 0x000015d0 #define NV50TCL_VERTEX_BEGIN 0x000015dc #define NV50TCL_VERTEX_BEGIN_POINTS 0x00000000 #define NV50TCL_VERTEX_BEGIN_LINES 0x00000001 @@ -7605,8 +7850,14 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50TCL_VERTEX_BEGIN_QUADS 0x00000007 #define NV50TCL_VERTEX_BEGIN_QUAD_STRIP 0x00000008 #define NV50TCL_VERTEX_BEGIN_POLYGON 0x00000009 +#define NV50TCL_VERTEX_BEGIN_LINES_ADJACENCY 0x0000000a +#define NV50TCL_VERTEX_BEGIN_LINE_STRIP_ADJACENCY 0x0000000b +#define NV50TCL_VERTEX_BEGIN_TRIANGLES_ADJACENCY 0x0000000c +#define NV50TCL_VERTEX_BEGIN_TRIANGLE_STRIP_ADJACENCY 0x0000000d #define NV50TCL_VERTEX_END 0x000015e0 #define NV50TCL_VERTEX_DATA 0x00001640 +#define NV50TCL_PRIM_RESTART_ENABLE 0x00001644 +#define NV50TCL_PRIM_RESTART_INDEX 0x00001648 #define NV50TCL_VP_ATTR_EN_0 0x00001650 #define NV50TCL_VP_ATTR_EN_0_7_SHIFT 28 #define NV50TCL_VP_ATTR_EN_0_7_MASK 0xf0000000 @@ -7897,29 +8148,87 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50TCL_VP_ATTR_EN_1_8_XNZW 0x0000000d #define NV50TCL_VP_ATTR_EN_1_8_NYZW 0x0000000e #define NV50TCL_VP_ATTR_EN_1_8_XYZW 0x0000000f +#define NV50TCL_POINT_SPRITE_CTRL 0x00001660 #define NV50TCL_LINE_STIPPLE_ENABLE 0x0000166c #define NV50TCL_LINE_STIPPLE_PATTERN 0x00001680 +#define NV50TCL_VERTEX_TWO_SIDE_ENABLE 0x00001688 #define NV50TCL_POLYGON_STIPPLE_ENABLE 0x0000168c -#define NV50TCL_VP_REG_HPOS 0x000016bc -#define NV50TCL_VP_REG_HPOS_X_SHIFT 0 -#define NV50TCL_VP_REG_HPOS_X_MASK 0x000000ff -#define NV50TCL_VP_REG_HPOS_Y_SHIFT 8 -#define NV50TCL_VP_REG_HPOS_Y_MASK 0x0000ff00 -#define NV50TCL_VP_REG_HPOS_Z_SHIFT 16 -#define NV50TCL_VP_REG_HPOS_Z_MASK 0x00ff0000 -#define NV50TCL_VP_REG_HPOS_W_SHIFT 24 -#define NV50TCL_VP_REG_HPOS_W_MASK 0xff000000 -#define NV50TCL_VP_REG_COL0 0x000016c0 -#define NV50TCL_VP_REG_COL0_X_SHIFT 0 -#define NV50TCL_VP_REG_COL0_X_MASK 0x000000ff -#define NV50TCL_VP_REG_COL0_Y_SHIFT 8 -#define NV50TCL_VP_REG_COL0_Y_MASK 0x0000ff00 -#define NV50TCL_VP_REG_COL0_Z_SHIFT 16 -#define NV50TCL_VP_REG_COL0_Z_MASK 0x00ff0000 -#define NV50TCL_VP_REG_COL0_W_SHIFT 24 -#define NV50TCL_VP_REG_COL0_W_MASK 0xff000000 +#define NV50TCL_SET_PROGRAM_CB 0x00001694 +#define NV50TCL_SET_PROGRAM_CB_PROGRAM_SHIFT 4 +#define NV50TCL_SET_PROGRAM_CB_PROGRAM_MASK 0x000000f0 +#define NV50TCL_SET_PROGRAM_CB_PROGRAM_VERTEX 0x00000000 +#define NV50TCL_SET_PROGRAM_CB_PROGRAM_GEOMETRY 0x00000020 +#define NV50TCL_SET_PROGRAM_CB_PROGRAM_FRAGMENT 0x00000030 +#define NV50TCL_SET_PROGRAM_CB_INDEX_SHIFT 8 +#define NV50TCL_SET_PROGRAM_CB_INDEX_MASK 0x00000f00 +#define NV50TCL_SET_PROGRAM_CB_BUFFER_SHIFT 12 +#define NV50TCL_SET_PROGRAM_CB_BUFFER_MASK 0x000ff000 +#define NV50TCL_SET_PROGRAM_CB_VALID (1 << 0) +#define NV50TCL_VP_RESULT_MAP_SIZE 0x000016ac +#define NV50TCL_VP_REG_ALLOC_TEMP 0x000016b0 +#define NV50TCL_VP_REG_ALLOC_RESULT 0x000016b8 +#define NV50TCL_VP_RESULT_MAP(x) (0x000016bc+((x)*4)) +#define NV50TCL_VP_RESULT_MAP__SIZE 0x00000008 +#define NV50TCL_VP_RESULT_MAP_0_SHIFT 0 +#define NV50TCL_VP_RESULT_MAP_0_MASK 0x000000ff +#define NV50TCL_VP_RESULT_MAP_1_SHIFT 8 +#define NV50TCL_VP_RESULT_MAP_1_MASK 0x0000ff00 +#define NV50TCL_VP_RESULT_MAP_2_SHIFT 16 +#define NV50TCL_VP_RESULT_MAP_2_MASK 0x00ff0000 +#define NV50TCL_VP_RESULT_MAP_3_SHIFT 24 +#define NV50TCL_VP_RESULT_MAP_3_MASK 0xff000000 #define NV50TCL_POLYGON_STIPPLE_PATTERN(x) (0x00001700+((x)*4)) #define NV50TCL_POLYGON_STIPPLE_PATTERN__SIZE 0x00000020 +#define NV50TCL_GP_ENABLE 0x00001798 +#define NV50TCL_GP_REG_ALLOC_TEMP 0x000017a0 +#define NV50TCL_GP_REG_ALLOC_RESULT 0x000017a8 +#define NV50TCL_GP_RESULT_MAP_SIZE 0x000017ac +#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE 0x000017b0 +#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_POINTS 0x00000001 +#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_LINE_STRIP 0x00000002 +#define NV50TCL_GP_OUTPUT_PRIMITIVE_TYPE_TRIANGLE_STRIP 0x00000003 +#define NV50TCL_RASTERIZE_ENABLE 0x000017b4 +#define NV50TCL_GP_RESULT_MAP(x) (0x000017fc+((x)*4)) +#define NV50TCL_GP_RESULT_MAP__SIZE 0x00000008 +#define NV50TCL_GP_RESULT_MAP_0_SHIFT 0 +#define NV50TCL_GP_RESULT_MAP_0_MASK 0x000000ff +#define NV50TCL_GP_RESULT_MAP_1_SHIFT 8 +#define NV50TCL_GP_RESULT_MAP_1_MASK 0x0000ff00 +#define NV50TCL_GP_RESULT_MAP_2_SHIFT 16 +#define NV50TCL_GP_RESULT_MAP_2_MASK 0x00ff0000 +#define NV50TCL_GP_RESULT_MAP_3_SHIFT 24 +#define NV50TCL_GP_RESULT_MAP_3_MASK 0xff000000 +#define NV50TCL_MAP_SEMANTIC_0 0x00001904 +#define NV50TCL_MAP_SEMANTIC_0_FFC0_ID_SHIFT 0 +#define NV50TCL_MAP_SEMANTIC_0_FFC0_ID_MASK 0x000000ff +#define NV50TCL_MAP_SEMANTIC_0_BFC0_ID_SHIFT 8 +#define NV50TCL_MAP_SEMANTIC_0_BFC0_ID_MASK 0x0000ff00 +#define NV50TCL_MAP_SEMANTIC_0_COLR_NR_SHIFT 16 +#define NV50TCL_MAP_SEMANTIC_0_COLR_NR_MASK 0x00ff0000 +#define NV50TCL_MAP_SEMANTIC_0_CLMP_EN_SHIFT 24 +#define NV50TCL_MAP_SEMANTIC_0_CLMP_EN_MASK 0xff000000 +#define NV50TCL_MAP_SEMANTIC_1 0x00001908 +#define NV50TCL_MAP_SEMANTIC_1_CLIP_LO_SHIFT 0 +#define NV50TCL_MAP_SEMANTIC_1_CLIP_LO_MASK 0x000000ff +#define NV50TCL_MAP_SEMANTIC_1_CLIP_HI_SHIFT 8 +#define NV50TCL_MAP_SEMANTIC_1_CLIP_HI_MASK 0x0000ff00 +#define NV50TCL_MAP_SEMANTIC_1_UNKN_02_SHIFT 16 +#define NV50TCL_MAP_SEMANTIC_1_UNKN_02_MASK 0x00ff0000 +#define NV50TCL_MAP_SEMANTIC_1_UNKN_03_SHIFT 24 +#define NV50TCL_MAP_SEMANTIC_1_UNKN_03_MASK 0xff000000 +#define NV50TCL_MAP_SEMANTIC_2 0x0000190c +#define NV50TCL_MAP_SEMANTIC_2_UNKN_00_SHIFT 0 +#define NV50TCL_MAP_SEMANTIC_2_UNKN_00_MASK 0x000000ff +#define NV50TCL_MAP_SEMANTIC_2_UNKN_01_SHIFT 8 +#define NV50TCL_MAP_SEMANTIC_2_UNKN_01_MASK 0x0000ff00 +#define NV50TCL_MAP_SEMANTIC_2_UNKN_02_SHIFT 16 +#define NV50TCL_MAP_SEMANTIC_2_UNKN_02_MASK 0x00ff0000 +#define NV50TCL_MAP_SEMANTIC_2_UNKN_03_SHIFT 24 +#define NV50TCL_MAP_SEMANTIC_2_UNKN_03_MASK 0xff000000 +#define NV50TCL_MAP_SEMANTIC_3 0x00001910 +#define NV50TCL_MAP_SEMANTIC_3_PTSZ_EN (1 << 0) +#define NV50TCL_MAP_SEMANTIC_3_PTSZ_ID_SHIFT 4 +#define NV50TCL_MAP_SEMANTIC_3_PTSZ_ID_MASK 0x00000ff0 #define NV50TCL_CULL_FACE_ENABLE 0x00001918 #define NV50TCL_FRONT_FACE 0x0000191c #define NV50TCL_FRONT_FACE_CW 0x00000900 @@ -7928,6 +8237,39 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50TCL_CULL_FACE_FRONT 0x00000404 #define NV50TCL_CULL_FACE_BACK 0x00000405 #define NV50TCL_CULL_FACE_FRONT_AND_BACK 0x00000408 +#define NV50TCL_VIEWPORT_TRANSFORM_EN 0x0000192c +#define NV50TCL_VIEW_VOLUME_CLIP_CTRL 0x0000193c +#define NV50TCL_FP_CTRL_UNK196C 0x0000196c +#define NV50TCL_FP_INTERPOLANT_CTRL 0x00001988 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_SHIFT 24 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_MASK 0xff000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NONE 0x00000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNNN 0x01000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYNN 0x02000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYNN 0x03000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NNZN 0x04000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNZN 0x05000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYZN 0x06000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYZN 0x07000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NNNW 0x08000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNNW 0x09000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYNW 0x0a000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYNW 0x0b000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NNZW 0x0c000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XNZW 0x0d000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_NYZW 0x0e000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_UMASK_XYZW 0x0f000000 +#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_SHIFT 16 +#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_MASK 0x00ff0000 +#define NV50TCL_FP_INTERPOLANT_CTRL_OFFSET_SHIFT 8 +#define NV50TCL_FP_INTERPOLANT_CTRL_OFFSET_MASK 0x0000ff00 +#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_UNK_SHIFT 0 +#define NV50TCL_FP_INTERPOLANT_CTRL_COUNT_UNK_MASK 0x000000ff +#define NV50TCL_FP_REG_ALLOC_TEMP 0x0000198c +#define NV50TCL_FP_CTRL_UNK19A8 0x000019a8 +#define NV50TCL_FP_CTRL_UNK19A8_DEP (1 << 20) +#define NV50TCL_FP_CTRL_UNK19A8_KIL (1 << 8) +#define NV50TCL_DEPTH_BOUNDS_EN 0x000019bc #define NV50TCL_LOGIC_OP_ENABLE 0x000019c4 #define NV50TCL_LOGIC_OP 0x000019c8 #define NV50TCL_LOGIC_OP_CLEAR 0x00001500 @@ -7957,6 +8299,43 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50TCL_COLOR_MASK_B_MASK 0x00000f00 #define NV50TCL_COLOR_MASK_A_SHIFT 12 #define NV50TCL_COLOR_MASK_A_MASK 0x0000f000 +#define NV50TCL_STRMOUT_ADDRESS_HIGH(x) (0x00001a80+((x)*16)) +#define NV50TCL_STRMOUT_ADDRESS_HIGH__SIZE 0x00000004 +#define NV50TCL_STRMOUT_ADDRESS_LOW(x) (0x00001a84+((x)*16)) +#define NV50TCL_STRMOUT_ADDRESS_LOW__SIZE 0x00000004 +#define NV50TCL_STRMOUT_NUM_ATTRIBS(x) (0x00001a88+((x)*16)) +#define NV50TCL_STRMOUT_NUM_ATTRIBS__SIZE 0x00000004 +#define NV50TCL_VERTEX_ARRAY_ATTRIB(x) (0x00001ac0+((x)*4)) +#define NV50TCL_VERTEX_ARRAY_ATTRIB__SIZE 0x00000010 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_BUFFER_SHIFT 0 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_BUFFER_MASK 0x000000ff +#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_SHIFT 16 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_MASK 0x00ff0000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32_32_32_32 0x00080000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32_32_32 0x00100000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32_32 0x00200000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_32 0x00900000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16_16_16_16 0x00180000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16_16_16 0x00280000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16_16 0x00780000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_16 0x00d80000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8_8_8_8 0x00500000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8_8_8 0x00980000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZE_8_8 0x00c00000 +#define NV50TCL_VERTEX_ARRAY_ATTRIB_SIZ... [truncated message content] |
From: <ag...@ke...> - 2009-08-18 19:01:54
|
libdrm/radeon/radeon_cs.h | 9 +++++++++ libdrm/radeon/radeon_cs_gem.c | 12 ++++++------ libdrm/radeon/radeon_track.c | 1 + 3 files changed, 16 insertions(+), 6 deletions(-) New commits: commit 8c43b79b21929e9e54e13e892f7787e222e73f39 Author: Pauli Nieminen <su...@gm...> Date: Tue Aug 18 18:51:38 2009 +0300 libdrm_radeon: Optimize copy of table to cs buffer with specialized call. Using this call in OUT_BATCH_TABLE reduces radeonEmitState cpu usage from 9% to 5% and emit_vpu goes from 7% to 1.5%. I did use calgrind to profile gears for cpu hotspots with r500 card. Signed-off-by: Pauli Nieminen <su...@gm...> diff --git a/libdrm/radeon/radeon_cs.h b/libdrm/radeon/radeon_cs.h index 7efec7e..1117a85 100644 --- a/libdrm/radeon/radeon_cs.h +++ b/libdrm/radeon/radeon_cs.h @@ -201,6 +201,15 @@ static inline void radeon_cs_write_qword(struct radeon_cs *cs, uint64_t qword) } } +static inline void radeon_cs_write_table(struct radeon_cs *cs, void *data, uint32_t size) +{ + memcpy(cs->packets + cs->cdw, data, size * 4); + cs->cdw += size; + if (cs->section) { + cs->section_cdw += size; + } +} + static inline void radeon_cs_space_set_flush(struct radeon_cs *cs, void (*fn)(void *), void *data) { cs->space_flush_fn = fn; commit a474fd978c0dedbed21b5dff24126acb1c7effef Author: Pauli Nieminen <su...@gm...> Date: Tue Aug 18 18:51:37 2009 +0300 libdrm_radeon: Fix loops so that compiler can optimize them. GCC did war about optimization not possible because possible forever loop. Signed-off-by: Pauli Nieminen <su...@gm...> diff --git a/libdrm/radeon/radeon_cs_gem.c b/libdrm/radeon/radeon_cs_gem.c index 264b067..a0db53b 100644 --- a/libdrm/radeon/radeon_cs_gem.c +++ b/libdrm/radeon/radeon_cs_gem.c @@ -354,21 +354,21 @@ static void cs_gem_print(struct radeon_cs *cs, FILE *file) unsigned opcode; unsigned reg; unsigned cnt; - int i, j; + unsigned int i, j; for (i = 0; i < cs->cdw;) { - cnt = CP_PACKET_GET_COUNT(cs->packets[i]); + cnt = CP_PACKET_GET_COUNT(cs->packets[i]) + 1; switch (CP_PACKET_GET_TYPE(cs->packets[i])) { case PACKET_TYPE0: - fprintf(file, "Pkt0 at %d (%d dwords):\n", i, cnt + 1); + fprintf(file, "Pkt0 at %d (%d dwords):\n", i, cnt); reg = CP_PACKET0_GET_REG(cs->packets[i]); if (CP_PACKET0_GET_ONE_REG_WR(cs->packets[i++])) { - for (j = 0; j <= cnt; j++) { + for (j = 0; j < cnt; j++) { fprintf(file, " 0x%08X -> 0x%04X\n", cs->packets[i++], reg); } } else { - for (j = 0; j <= cnt; j++) { + for (j = 0; j < cnt; j++) { fprintf(file, " 0x%08X -> 0x%04X\n", cs->packets[i++], reg); reg += 4; @@ -410,7 +410,7 @@ static void cs_gem_print(struct radeon_cs *cs, FILE *file) fprintf(file, "Unknow opcode 0x%02X at %d\n", opcode, i); return; } - for (j = 0; j <= cnt; j++) { + for (j = 0; j < cnt; j++) { fprintf(file, " 0x%08X\n", cs->packets[i++]); } break; commit 64cef1e46554fbf82388acfcfc8051ce956a3dc2 Author: Pauli Nieminen <su...@gm...> Date: Fri Aug 7 20:03:26 2009 +0300 libdrm/radeon: Update head of linked list not to point freed memory. Signed-off-by: Pauli Nieminen <su...@gm...> diff --git a/libdrm/radeon/radeon_track.c b/libdrm/radeon/radeon_track.c index 1623906..9ab0927 100644 --- a/libdrm/radeon/radeon_track.c +++ b/libdrm/radeon/radeon_track.c @@ -137,4 +137,5 @@ void radeon_tracker_print(struct radeon_tracker *tracker, FILE *file) track = track->next; free(tmp); } + tracker->tracks.next = NULL; } |
From: <an...@ke...> - 2009-09-21 22:35:01
|
configure.ac | 2 libdrm/intel/intel_bufmgr_gem.c | 92 +++++++++++++--------------------------- 2 files changed, 31 insertions(+), 63 deletions(-) New commits: commit ac71f0849928f4b2fbb69c01304ac6f9df8916a1 Author: Eric Anholt <er...@an...> Date: Mon Sep 21 15:29:58 2009 -0700 Bump to 2.4.14 for release. diff --git a/configure.ac b/configure.ac index 425417e..d707052 100644 --- a/configure.ac +++ b/configure.ac @@ -19,7 +19,7 @@ # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. AC_PREREQ(2.60) -AC_INIT([libdrm], 2.4.13, [dri...@li...], libdrm) +AC_INIT([libdrm], 2.4.14, [dri...@li...], libdrm) AC_USE_SYSTEM_EXTENSIONS AC_CONFIG_SRCDIR([Makefile.am]) AM_INIT_AUTOMAKE([dist-bzip2]) commit 51b89733c53458b6827f0db99eb46a20fa1c7020 Author: Eric Anholt <er...@an...> Date: Sun Sep 6 23:17:14 2009 -0700 intel: Remove the max_entries stuff that complicated bo reuse. I thought I was going to do all sorts of crazy experiments with it. I never did, and it turned out the free-after-a-few-seconds plan is working out fine. diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c index 84836a8..78297e0 100644 --- a/libdrm/intel/intel_bufmgr_gem.c +++ b/libdrm/intel/intel_bufmgr_gem.c @@ -69,15 +69,6 @@ typedef struct _drm_intel_bo_gem drm_intel_bo_gem; struct drm_intel_gem_bo_bucket { drmMMListHead head; - - /** - * Limit on the number of entries in this bucket. - * - * 0 means that this caching at this bucket size is disabled. - * -1 means that there is no limit to caching at this size. - */ - int max_entries; - int num_entries; unsigned long size; }; @@ -105,6 +96,7 @@ typedef struct _drm_intel_bufmgr_gem { uint64_t gtt_size; int available_fences; int pci_device; + char bo_reuse; } drm_intel_bufmgr_gem; struct _drm_intel_bo_gem { @@ -342,7 +334,7 @@ drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name, /* If we don't have caching at this size, don't actually round the * allocation up. */ - if (bucket == NULL || bucket->max_entries == 0) { + if (bucket == NULL) { bo_size = size; if (bo_size < page_size) bo_size = page_size; @@ -352,7 +344,7 @@ drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name, pthread_mutex_lock(&bufmgr_gem->lock); /* Get a buffer out of the cache if available */ - if (bucket != NULL && bucket->num_entries > 0) { + if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) { if (for_render) { /* Allocate new render-target BOs from the tail (MRU) * of the list, as it will likely be hot in the GPU cache @@ -360,7 +352,6 @@ drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name, */ bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.prev, head); DRMLISTDEL(&bo_gem->head); - bucket->num_entries--; alloc_from_cache = 1; } else { /* For non-render-target BOs (where we're probably going to map it @@ -374,7 +365,6 @@ drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name, if (!drm_intel_gem_bo_busy(&bo_gem->bo)) { alloc_from_cache = 1; DRMLISTDEL(&bo_gem->head); - bucket->num_entries--; } } } @@ -553,7 +543,6 @@ drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time) break; DRMLISTDEL(&bo_gem->head); - bucket->num_entries--; drm_intel_gem_bo_free(&bo_gem->bo); } @@ -587,11 +576,7 @@ drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo) bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size); /* Put the buffer into our internal cache for reuse if we can. */ tiling_mode = I915_TILING_NONE; - if (bo_gem->reusable && - bucket != NULL && - (bucket->max_entries == -1 || - (bucket->max_entries > 0 && - bucket->num_entries < bucket->max_entries)) && + if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL && drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0) { struct timespec time; @@ -606,7 +591,6 @@ drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo) bo_gem->reloc_count = 0; DRMLISTADDTAIL(&bo_gem->head, &bucket->head); - bucket->num_entries++; drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec); } else { @@ -931,7 +915,6 @@ drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr) while (!DRMLISTEMPTY(&bucket->head)) { bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.next, head); DRMLISTDEL(&bo_gem->head); - bucket->num_entries--; drm_intel_gem_bo_free(&bo_gem->bo); } @@ -1225,11 +1208,8 @@ void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr) { drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; - int i; - for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) { - bufmgr_gem->cache_bucket[i].max_entries = -1; - } + bufmgr_gem->bo_reuse = 1; } /** commit 456a358b9ade5c90ff86b2322a79648c69cddcdc Author: Eric Anholt <er...@an...> Date: Sun Sep 6 23:02:21 2009 -0700 intel: Remove the old swrast flag for reducing cache flushing. It hasn't been doing anything effective since 52e5d24fae4af6f2f4a5304a516c8c5ab347a11b, and we pretty much don't bo_map pinned buffers any more anyway. diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c index baa0ee6..84836a8 100644 --- a/libdrm/intel/intel_bufmgr_gem.c +++ b/libdrm/intel/intel_bufmgr_gem.c @@ -127,13 +127,6 @@ struct _drm_intel_bo_gem { int validate_index; /** - * Boolean whether we've started swrast - * Set when the buffer has been mapped - * Cleared when the buffer is unmapped - */ - int swrast; - - /** * Current tiling mode */ uint32_t tiling_mode; @@ -663,30 +656,26 @@ drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable) return ret; } bo_gem->mem_virtual = (void *)(uintptr_t)mmap_arg.addr_ptr; - bo_gem->swrast = 0; } DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, bo_gem->mem_virtual); bo->virtual = bo_gem->mem_virtual; - if (bo_gem->global_name != 0 || !bo_gem->swrast) { - set_domain.handle = bo_gem->gem_handle; - set_domain.read_domains = I915_GEM_DOMAIN_CPU; - if (write_enable) - set_domain.write_domain = I915_GEM_DOMAIN_CPU; - else - set_domain.write_domain = 0; - do { - ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, - &set_domain); - } while (ret == -1 && errno == EINTR); - if (ret != 0) { - fprintf (stderr, "%s:%d: Error setting swrast %d: %s\n", - __FILE__, __LINE__, bo_gem->gem_handle, strerror (errno)); - pthread_mutex_unlock(&bufmgr_gem->lock); - return ret; - } - bo_gem->swrast = 1; + set_domain.handle = bo_gem->gem_handle; + set_domain.read_domains = I915_GEM_DOMAIN_CPU; + if (write_enable) + set_domain.write_domain = I915_GEM_DOMAIN_CPU; + else + set_domain.write_domain = 0; + do { + ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, + &set_domain); + } while (ret == -1 && errno == EINTR); + if (ret != 0) { + fprintf (stderr, "%s:%d: Error setting to CPU domain %d: %s\n", + __FILE__, __LINE__, bo_gem->gem_handle, strerror (errno)); + pthread_mutex_unlock(&bufmgr_gem->lock); + return ret; } pthread_mutex_unlock(&bufmgr_gem->lock); @@ -797,14 +786,16 @@ drm_intel_gem_bo_unmap(drm_intel_bo *bo) assert(bo_gem->mem_virtual != NULL); pthread_mutex_lock(&bufmgr_gem->lock); - if (bo_gem->swrast) { - sw_finish.handle = bo_gem->gem_handle; - do { - ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SW_FINISH, - &sw_finish); - } while (ret == -1 && errno == EINTR); - bo_gem->swrast = 0; - } + + /* Cause a flush to happen if the buffer's pinned for scanout, so the + * results show up in a timely manner. + */ + sw_finish.handle = bo_gem->gem_handle; + do { + ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SW_FINISH, + &sw_finish); + } while (ret == -1 && errno == EINTR); + bo->virtual = NULL; pthread_mutex_unlock(&bufmgr_gem->lock); return 0; @@ -1100,9 +1091,6 @@ drm_intel_gem_bo_exec(drm_intel_bo *bo, int used, drm_intel_bo *bo = bufmgr_gem->exec_bos[i]; drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; - /* Need to call swrast on next bo_map */ - bo_gem->swrast = 0; - /* Disconnect the buffer from the validate list */ bo_gem->validate_index = -1; drm_intel_gem_bo_unreference_locked(bo); |
From: <an...@ke...> - 2009-10-02 20:03:12
|
libdrm/intel/intel_bufmgr.c | 6 ++ libdrm/intel/intel_bufmgr.h | 1 libdrm/intel/intel_bufmgr_gem.c | 85 +++++++++++++++++++++++++++++++++++---- libdrm/intel/intel_bufmgr_priv.h | 3 + shared-core/i915_drm.h | 16 +++++++ 5 files changed, 103 insertions(+), 8 deletions(-) New commits: commit 0fb215ae3199b5be0c9a9474e5941f8d8998c11a Author: Chris Wilson <ch...@ch...> Date: Fri Oct 2 04:31:34 2009 +0100 intel: Mark cached bo as purgeable Set the DONTNEED flag on cached buffers so that the kernel is free to discard those when under memory pressure. [anholt: This takes firefox-talos-gfx time from ~62 seconds to ~65 seconds on my GM965, but it seems like a hit worth taking for the improved functionality from saving memory] Signed-off-by: Chris Wilson <ch...@ch...> Signed-off-by: Eric Anholt <er...@an...> diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c index 44d096f..902c1ed 100644 --- a/libdrm/intel/intel_bufmgr_gem.c +++ b/libdrm/intel/intel_bufmgr_gem.c @@ -191,6 +191,9 @@ drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode, static void drm_intel_gem_bo_unreference(drm_intel_bo *bo); +static void +drm_intel_gem_bo_free(drm_intel_bo *bo); + static struct drm_intel_gem_bo_bucket * drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size) @@ -315,6 +318,38 @@ drm_intel_gem_bo_busy(drm_intel_bo *bo) return (ret == 0 && busy.busy); } +static int +drm_intel_gem_bo_madvise(drm_intel_bufmgr_gem *bufmgr_gem, + drm_intel_bo_gem *bo_gem, + int state) +{ + struct drm_i915_gem_madvise madv; + + madv.handle = bo_gem->gem_handle; + madv.madv = state; + madv.retained = 1; + ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv); + + return madv.retained; +} + +/* drop the oldest entries that have been purged by the kernel */ +static void +drm_intel_gem_bo_cache_purge_bucket(drm_intel_bufmgr_gem *bufmgr_gem, + struct drm_intel_gem_bo_bucket *bucket) +{ + while (!DRMLISTEMPTY(&bucket->head)) { + drm_intel_bo_gem *bo_gem; + + bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.next, head); + if (drm_intel_gem_bo_madvise (bufmgr_gem, bo_gem, I915_MADV_DONTNEED)) + break; + + DRMLISTDEL(&bo_gem->head); + drm_intel_gem_bo_free(&bo_gem->bo); + } +} + static drm_intel_bo * drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name, unsigned long size, unsigned int alignment, @@ -325,7 +360,7 @@ drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name, unsigned int page_size = getpagesize(); int ret; struct drm_intel_gem_bo_bucket *bucket; - int alloc_from_cache = 0; + int alloc_from_cache; unsigned long bo_size; /* Round the allocated size up to a power of two number of pages. */ @@ -344,6 +379,8 @@ drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name, pthread_mutex_lock(&bufmgr_gem->lock); /* Get a buffer out of the cache if available */ +retry: + alloc_from_cache = 0; if (bucket != NULL && !DRMLISTEMPTY(&bucket->head)) { if (for_render) { /* Allocate new render-target BOs from the tail (MRU) @@ -361,12 +398,19 @@ drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name, * waiting for the GPU to finish. */ bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.next, head); - if (!drm_intel_gem_bo_busy(&bo_gem->bo)) { alloc_from_cache = 1; DRMLISTDEL(&bo_gem->head); } } + + if (alloc_from_cache) { + if(!drm_intel_gem_bo_madvise(bufmgr_gem, bo_gem, I915_MADV_WILLNEED)) { + drm_intel_gem_bo_free(&bo_gem->bo); + drm_intel_gem_bo_cache_purge_bucket(bufmgr_gem, bucket); + goto retry; + } + } } pthread_mutex_unlock(&bufmgr_gem->lock); @@ -591,6 +635,7 @@ drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo) DRMLISTADDTAIL(&bo_gem->head, &bucket->head); + drm_intel_gem_bo_madvise(bufmgr_gem, bo_gem, I915_MADV_DONTNEED); drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec); } else { drm_intel_gem_bo_free(bo); diff --git a/shared-core/i915_drm.h b/shared-core/i915_drm.h index 2539966..b214600 100644 --- a/shared-core/i915_drm.h +++ b/shared-core/i915_drm.h @@ -206,6 +206,7 @@ typedef struct drm_i915_sarea { #define DRM_I915_GEM_GET_APERTURE 0x23 #define DRM_I915_GEM_MMAP_GTT 0x24 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 +#define DRM_I915_GEM_MADVISE 0x26 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) @@ -244,6 +245,7 @@ typedef struct drm_i915_sarea { #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) +#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) /* Asynchronous page flipping: */ @@ -727,4 +729,18 @@ struct drm_i915_get_pipe_from_crtc_id { uint32_t pipe; }; +#define I915_MADV_WILLNEED 0 +#define I915_MADV_DONTNEED 1 + +struct drm_i915_gem_madvise { + /** Handle of the buffer to change the backing store advice. */ + uint32_t handle; + + /** Advice. */ + uint32_t madv; + + /** Whether or not the backing store still exists */ + uint32_t retained; +}; + #endif /* _I915_DRM_H_ */ commit 12d9b7cc8550c1999e5c39a38b1b14e654f49065 Author: Eric Anholt <er...@an...> Date: Fri Oct 2 11:11:31 2009 -0700 intel: Don't free the reloc list when putting a freed BO in the cache. This takes firefox-talos-gfx from 74 seconds to 70 seconds on my GM965. diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c index d4fa159..44d096f 100644 --- a/libdrm/intel/intel_bufmgr_gem.c +++ b/libdrm/intel/intel_bufmgr_gem.c @@ -514,6 +514,9 @@ drm_intel_gem_bo_free(drm_intel_bo *bo) if (bo_gem->gtt_virtual) munmap (bo_gem->gtt_virtual, bo_gem->bo.size); + free(bo_gem->reloc_target_bo); + free(bo_gem->relocs); + /* Close this object */ memset(&close, 0, sizeof(close)); close.handle = bo_gem->gem_handle; @@ -566,8 +569,6 @@ drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo) /* Unreference all the target buffers */ for (i = 0; i < bo_gem->reloc_count; i++) drm_intel_gem_bo_unreference_locked(bo_gem->reloc_target_bo[i]); - free(bo_gem->reloc_target_bo); - free(bo_gem->relocs); } DBG("bo_unreference final: %d (%s)\n", @@ -586,8 +587,6 @@ drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo) bo_gem->name = NULL; bo_gem->validate_index = -1; - bo_gem->relocs = NULL; - bo_gem->reloc_target_bo = NULL; bo_gem->reloc_count = 0; DRMLISTADDTAIL(&bo_gem->head, &bucket->head); commit 769b10578083aa7bbee0052246d8ea6000435ae8 Author: Eric Anholt <er...@an...> Date: Thu Oct 1 19:09:26 2009 -0700 intel: Add a new function to check if a BO's reloc tree references some BO. There are a bunch of places in GL where if we can't do this we have to flush the batchbuffer, and the cost of lookups here is outweighed by flush savings. diff --git a/libdrm/intel/intel_bufmgr.c b/libdrm/intel/intel_bufmgr.c index 219c761..20e59b8 100644 --- a/libdrm/intel/intel_bufmgr.c +++ b/libdrm/intel/intel_bufmgr.c @@ -228,6 +228,12 @@ int drm_intel_bo_busy(drm_intel_bo *bo) } int +drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo) +{ + return bo->bufmgr->bo_references(bo, target_bo); +} + +int drm_intel_get_pipe_from_crtc_id (drm_intel_bufmgr *bufmgr, int crtc_id) { if (bufmgr->get_pipe_from_crtc_id) diff --git a/libdrm/intel/intel_bufmgr.h b/libdrm/intel/intel_bufmgr.h index 218b759..cb7196c 100644 --- a/libdrm/intel/intel_bufmgr.h +++ b/libdrm/intel/intel_bufmgr.h @@ -110,6 +110,7 @@ int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t *name); int drm_intel_bo_busy(drm_intel_bo *bo); int drm_intel_bo_disable_reuse(drm_intel_bo *bo); +int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo); /* drm_intel_bufmgr_gem.c */ drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size); diff --git a/libdrm/intel/intel_bufmgr_gem.c b/libdrm/intel/intel_bufmgr_gem.c index 78297e0..d4fa159 100644 --- a/libdrm/intel/intel_bufmgr_gem.c +++ b/libdrm/intel/intel_bufmgr_gem.c @@ -681,7 +681,7 @@ drm_intel_gem_bo_map_gtt(drm_intel_bo *bo) if (bo_gem->gtt_virtual == NULL) { struct drm_i915_gem_mmap_gtt mmap_arg; - DBG("bo_map_gtt: %d (%s)\n", bo_gem->gem_handle, bo_gem->name); + DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle, bo_gem->name); memset(&mmap_arg, 0, sizeof(mmap_arg)); mmap_arg.handle = bo_gem->gem_handle; @@ -715,7 +715,7 @@ drm_intel_gem_bo_map_gtt(drm_intel_bo *bo) bo->virtual = bo_gem->gtt_virtual; - DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, + DBG("bo_map_gtt: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name, bo_gem->gtt_virtual); /* Now move it to the GTT domain so that the CPU caches are flushed */ @@ -1390,6 +1390,29 @@ drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo) } /** + * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready + * for the next drm_intel_bufmgr_check_aperture_space() call. + */ +static int +drm_intel_gem_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; + int i; + + if (bo == NULL || target_bo == NULL) + return 0; + + for (i = 0; i < bo_gem->reloc_count; i++) { + if (bo_gem->reloc_target_bo[i] == target_bo) + return 1; + if (drm_intel_gem_bo_references(bo_gem->reloc_target_bo[i], target_bo)) + return 1; + } + + return 0; +} + +/** * Initializes the GEM buffer manager, which uses the kernel to allocate, map, * and manage map buffer objections. * @@ -1474,6 +1497,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) bufmgr_gem->bufmgr.check_aperture_space = drm_intel_gem_check_aperture_space; bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse; bufmgr_gem->bufmgr.get_pipe_from_crtc_id = drm_intel_gem_get_pipe_from_crtc_id; + bufmgr_gem->bufmgr.bo_references = drm_intel_gem_bo_references; + /* Initialize the linked lists for BO reuse cache. */ for (i = 0, size = 4096; i < DRM_INTEL_GEM_BO_BUCKETS; i++, size *= 2) { DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head); diff --git a/libdrm/intel/intel_bufmgr_priv.h b/libdrm/intel/intel_bufmgr_priv.h index af17c12..454d457 100644 --- a/libdrm/intel/intel_bufmgr_priv.h +++ b/libdrm/intel/intel_bufmgr_priv.h @@ -207,6 +207,9 @@ struct _drm_intel_bufmgr { */ int (*get_pipe_from_crtc_id)(drm_intel_bufmgr *bufmgr, int crtc_id); + /** Returns true if target_bo is in the relocation tree rooted at bo. */ + int (*bo_references)(drm_intel_bo *bo, drm_intel_bo *target_bo); + int debug; /**< Enables verbose debugging printouts */ }; |
From: <dar...@ke...> - 2009-11-04 07:54:35
|
libdrm/nouveau/nouveau_bo.c | 1 libdrm/nouveau/nouveau_private.h | 4 + libdrm/nouveau/nouveau_pushbuf.c | 83 ++++++++++++++++++++++++++++++++++----- libdrm/nouveau/nouveau_pushbuf.h | 53 ++++++++++++++++-------- 4 files changed, 114 insertions(+), 27 deletions(-) New commits: commit b7ed162d2912d53d03d94f9ceaebf7d96d570c04 Author: Ben Skeggs <skeggsb@beleth.(none)> Date: Wed Nov 4 17:31:18 2009 +1000 nouveau: turn another assertion into an error Signed-off-by: Ben Skeggs <skeggsb@beleth.(none)> diff --git a/libdrm/nouveau/nouveau_pushbuf.c b/libdrm/nouveau/nouveau_pushbuf.c index df43eff..90250c0 100644 --- a/libdrm/nouveau/nouveau_pushbuf.c +++ b/libdrm/nouveau/nouveau_pushbuf.c @@ -87,8 +87,12 @@ nouveau_pushbuf_emit_reloc(struct nouveau_channel *chan, void *ptr, domains |= NOUVEAU_GEM_DOMAIN_VRAM; if (flags & NOUVEAU_BO_GART) domains |= NOUVEAU_GEM_DOMAIN_GART; + + if (!(pbbo->valid_domains & domains)) { + fprintf(stderr, "no valid domains remain!\n"); + return -EINVAL; + } pbbo->valid_domains &= domains; - assert(pbbo->valid_domains); assert(flags & NOUVEAU_BO_RDWR); if (flags & NOUVEAU_BO_RD) { commit f4c50630269df4201b89a538cbf8e11646f17d82 Author: Ben Skeggs <skeggsb@beleth.(none)> Date: Wed Nov 4 15:23:53 2009 +1000 nouveau: modify api slightly to allow caller to handle reloc failures Signed-off-by: Ben Skeggs <skeggsb@beleth.(none)> diff --git a/libdrm/nouveau/nouveau_private.h b/libdrm/nouveau/nouveau_private.h index 743c831..784afc9 100644 --- a/libdrm/nouveau/nouveau_private.h +++ b/libdrm/nouveau/nouveau_private.h @@ -52,6 +52,9 @@ struct nouveau_pushbuf_priv { unsigned *pushbuf; unsigned size; + unsigned marker; + unsigned marker_relocs; + struct drm_nouveau_gem_pushbuf_bo *buffers; unsigned nr_buffers; struct drm_nouveau_gem_pushbuf_reloc *relocs; diff --git a/libdrm/nouveau/nouveau_pushbuf.c b/libdrm/nouveau/nouveau_pushbuf.c index af181b2..df43eff 100644 --- a/libdrm/nouveau/nouveau_pushbuf.c +++ b/libdrm/nouveau/nouveau_pushbuf.c @@ -67,7 +67,6 @@ nouveau_pushbuf_emit_reloc(struct nouveau_channel *chan, void *ptr, if (nvpb->nr_relocs >= NOUVEAU_GEM_MAX_RELOCS) { fprintf(stderr, "too many relocs!!\n"); - assert(0); return -ENOMEM; } @@ -79,7 +78,6 @@ nouveau_pushbuf_emit_reloc(struct nouveau_channel *chan, void *ptr, pbbo = nouveau_bo_emit_buffer(chan, bo); if (!pbbo) { fprintf(stderr, "buffer emit fail :(\n"); - assert(0); return -ENOMEM; } @@ -353,6 +351,57 @@ restart_push: if (chan->flush_notify) chan->flush_notify(chan); + nvpb->marker = 0; return ret; } +int +nouveau_pushbuf_marker_emit(struct nouveau_channel *chan, + unsigned wait_dwords, unsigned wait_relocs) +{ + struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(chan->pushbuf); + + if (AVAIL_RING(chan) < wait_dwords) + return nouveau_pushbuf_flush(chan, wait_dwords); + + if (nvpb->nr_relocs + wait_relocs >= NOUVEAU_GEM_MAX_RELOCS) + return nouveau_pushbuf_flush(chan, wait_dwords); + + nvpb->marker = nvpb->base.cur - nvpb->pushbuf; + nvpb->marker_relocs = nvpb->nr_relocs; + return 0; +} + +void +nouveau_pushbuf_marker_undo(struct nouveau_channel *chan) +{ + struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(chan->pushbuf); + unsigned i; + + if (!nvpb->marker) + return; + + /* undo any relocs/buffers added to the list since last marker */ + for (i = nvpb->marker_relocs; i < nvpb->nr_relocs; i++) { + struct drm_nouveau_gem_pushbuf_reloc *r = &nvpb->relocs[i]; + struct drm_nouveau_gem_pushbuf_bo *pbbo = + &nvpb->buffers[r->bo_index]; + struct nouveau_bo *bo = (void *)(unsigned long)pbbo->user_priv; + struct nouveau_bo_priv *nvbo = nouveau_bo(bo); + + if (--nvbo->pending_refcnt) + continue; + + nvbo->pending = NULL; + nouveau_bo_ref(NULL, &bo); + nvpb->nr_buffers--; + } + nvpb->nr_relocs = nvpb->marker_relocs; + + /* reset pushbuf back to last marker */ + nvpb->base.cur = nvpb->pushbuf + nvpb->marker; + nvpb->base.remaining = nvpb->size - nvpb->marker; + nvpb->marker = 0; +} + + diff --git a/libdrm/nouveau/nouveau_pushbuf.h b/libdrm/nouveau/nouveau_pushbuf.h index 3c746ed..c7ac8c4 100644 --- a/libdrm/nouveau/nouveau_pushbuf.h +++ b/libdrm/nouveau/nouveau_pushbuf.h @@ -40,11 +40,30 @@ int nouveau_pushbuf_flush(struct nouveau_channel *, unsigned min); int +nouveau_pushbuf_marker_emit(struct nouveau_channel *chan, + unsigned wait_dwords, unsigned wait_relocs); + +void +nouveau_pushbuf_marker_undo(struct nouveau_channel *chan); + +int nouveau_pushbuf_emit_reloc(struct nouveau_channel *, void *ptr, struct nouveau_bo *, uint32_t data, uint32_t data2, uint32_t flags, uint32_t vor, uint32_t tor); /* Push buffer access macros */ +static __inline__ int +MARK_RING(struct nouveau_channel *chan, unsigned dwords, unsigned relocs) +{ + return nouveau_pushbuf_marker_emit(chan, dwords, relocs); +} + +static __inline__ void +MARK_UNDO(struct nouveau_channel *chan) +{ + nouveau_pushbuf_marker_undo(chan); +} + static __inline__ void OUT_RING(struct nouveau_channel *chan, unsigned data) { @@ -116,62 +135,62 @@ BIND_RING(struct nouveau_channel *chan, struct nouveau_grobj *gr, unsigned sc) OUT_RING (chan, gr->handle); } -static __inline__ void +static __inline__ int OUT_RELOC(struct nouveau_channel *chan, struct nouveau_bo *bo, unsigned data, unsigned flags, unsigned vor, unsigned tor) { - nouveau_pushbuf_emit_reloc(chan, chan->pushbuf->cur++, bo, - data, 0, flags, vor, tor); + return nouveau_pushbuf_emit_reloc(chan, chan->pushbuf->cur++, bo, + data, 0, flags, vor, tor); } -static __inline__ void +static __inline__ int OUT_RELOC2(struct nouveau_channel *chan, struct nouveau_bo *bo, unsigned data, unsigned data2, unsigned flags, unsigned vor, unsigned tor) { - nouveau_pushbuf_emit_reloc(chan, chan->pushbuf->cur++, bo, - data, data2, flags, vor, tor); + return nouveau_pushbuf_emit_reloc(chan, chan->pushbuf->cur++, bo, + data, data2, flags, vor, tor); } /* Raw data + flags depending on FB/TT buffer */ -static __inline__ void +static __inline__ int OUT_RELOCd(struct nouveau_channel *chan, struct nouveau_bo *bo, unsigned data, unsigned flags, unsigned vor, unsigned tor) { - OUT_RELOC(chan, bo, data, flags | NOUVEAU_BO_OR, vor, tor); + return OUT_RELOC(chan, bo, data, flags | NOUVEAU_BO_OR, vor, tor); } /* FB/TT object handle */ -static __inline__ void +static __inline__ int OUT_RELOCo(struct nouveau_channel *chan, struct nouveau_bo *bo, unsigned flags) { - OUT_RELOC(chan, bo, 0, flags | NOUVEAU_BO_OR, - chan->vram->handle, chan->gart->handle); + return OUT_RELOC(chan, bo, 0, flags | NOUVEAU_BO_OR, + chan->vram->handle, chan->gart->handle); } /* Low 32-bits of offset */ -static __inline__ void +static __inline__ int OUT_RELOCl(struct nouveau_channel *chan, struct nouveau_bo *bo, unsigned delta, unsigned flags) { - OUT_RELOC(chan, bo, delta, flags | NOUVEAU_BO_LOW, 0, 0); + return OUT_RELOC(chan, bo, delta, flags | NOUVEAU_BO_LOW, 0, 0); } /* Low 32-bits of offset + GPU linear access range info */ -static __inline__ void +static __inline__ int OUT_RELOCr(struct nouveau_channel *chan, struct nouveau_bo *bo, unsigned delta, unsigned size, unsigned flags) { - OUT_RELOC2(chan, bo, delta, size, flags | NOUVEAU_BO_LOW, 0, 0); + return OUT_RELOC2(chan, bo, delta, size, flags | NOUVEAU_BO_LOW, 0, 0); } /* High 32-bits of offset */ -static __inline__ void +static __inline__ int OUT_RELOCh(struct nouveau_channel *chan, struct nouveau_bo *bo, unsigned delta, unsigned flags) { - OUT_RELOC(chan, bo, delta, flags | NOUVEAU_BO_HIGH, 0, 0); + return OUT_RELOC(chan, bo, delta, flags | NOUVEAU_BO_HIGH, 0, 0); } #endif commit a8bdf0e00c0653fd343fd7fd64b5f2e8437bb130 Author: Ben Skeggs <bs...@re...> Date: Tue Oct 27 14:32:40 2009 +1000 nouveau: add reloc refcnt to pending bo list Signed-off-by: Ben Skeggs <bs...@re...> diff --git a/libdrm/nouveau/nouveau_bo.c b/libdrm/nouveau/nouveau_bo.c index b7e6d86..85fc14f 100644 --- a/libdrm/nouveau/nouveau_bo.c +++ b/libdrm/nouveau/nouveau_bo.c @@ -607,6 +607,7 @@ nouveau_bo_emit_buffer(struct nouveau_channel *chan, struct nouveau_bo *bo) pbbo = nvpb->buffers + nvpb->nr_buffers++; nvbo->pending = pbbo; nvbo->pending_channel = chan; + nvbo->pending_refcnt = 0; nouveau_bo_ref(bo, &ref); pbbo->user_priv = (uint64_t)(unsigned long)ref; diff --git a/libdrm/nouveau/nouveau_private.h b/libdrm/nouveau/nouveau_private.h index 9ce87fb..743c831 100644 --- a/libdrm/nouveau/nouveau_private.h +++ b/libdrm/nouveau/nouveau_private.h @@ -99,6 +99,7 @@ struct nouveau_bo_priv { /* Tracking */ struct drm_nouveau_gem_pushbuf_bo *pending; struct nouveau_channel *pending_channel; + int pending_refcnt; int write_marker; /* Userspace object */ diff --git a/libdrm/nouveau/nouveau_pushbuf.c b/libdrm/nouveau/nouveau_pushbuf.c index d434a5f..af181b2 100644 --- a/libdrm/nouveau/nouveau_pushbuf.c +++ b/libdrm/nouveau/nouveau_pushbuf.c @@ -60,6 +60,7 @@ nouveau_pushbuf_emit_reloc(struct nouveau_channel *chan, void *ptr, uint32_t flags, uint32_t vor, uint32_t tor) { struct nouveau_pushbuf_priv *nvpb = nouveau_pushbuf(chan->pushbuf); + struct nouveau_bo_priv *nvbo = nouveau_bo(bo); struct drm_nouveau_gem_pushbuf_reloc *r; struct drm_nouveau_gem_pushbuf_bo *pbbo; uint32_t domains = 0; @@ -70,7 +71,7 @@ nouveau_pushbuf_emit_reloc(struct nouveau_channel *chan, void *ptr, return -ENOMEM; } - if (nouveau_bo(bo)->user && (flags & NOUVEAU_BO_WR)) { + if (nvbo->user && (flags & NOUVEAU_BO_WR)) { fprintf(stderr, "write to user buffer!!\n"); return -EINVAL; } @@ -82,6 +83,8 @@ nouveau_pushbuf_emit_reloc(struct nouveau_channel *chan, void *ptr, return -ENOMEM; } + nvbo->pending_refcnt++; + if (flags & NOUVEAU_BO_VRAM) domains |= NOUVEAU_GEM_DOMAIN_VRAM; if (flags & NOUVEAU_BO_GART) @@ -95,7 +98,7 @@ nouveau_pushbuf_emit_reloc(struct nouveau_channel *chan, void *ptr, } if (flags & NOUVEAU_BO_WR) { pbbo->write_domains |= domains; - nouveau_bo(bo)->write_marker = 1; + nvbo->write_marker = 1; } r = nvpb->relocs + nvpb->nr_relocs++; @@ -322,18 +325,25 @@ restart_push: /* Update presumed offset/domain for any buffers that moved. * Dereference all buffers on validate list */ - for (i = 0; i < nvpb->nr_buffers; i++) { - struct drm_nouveau_gem_pushbuf_bo *pbbo = &nvpb->buffers[i]; + for (i = 0; i < nvpb->nr_relocs; i++) { + struct drm_nouveau_gem_pushbuf_reloc *r = &nvpb->relocs[i]; + struct drm_nouveau_gem_pushbuf_bo *pbbo = + &nvpb->buffers[r->bo_index]; struct nouveau_bo *bo = (void *)(unsigned long)pbbo->user_priv; + struct nouveau_bo_priv *nvbo = nouveau_bo(bo); + + if (--nvbo->pending_refcnt) + continue; if (pbbo->presumed_ok == 0) { - nouveau_bo(bo)->domain = pbbo->presumed_domain; - nouveau_bo(bo)->offset = pbbo->presumed_offset; + nvbo->domain = pbbo->presumed_domain; + nvbo->offset = pbbo->presumed_offset; } - nouveau_bo(bo)->pending = NULL; + nvbo->pending = NULL; nouveau_bo_ref(NULL, &bo); } + nvpb->nr_buffers = 0; nvpb->nr_relocs = 0; |
From: <al...@ke...> - 2010-01-17 03:38:33
|
configure.ac | 7 +++++++ intel/intel_atomic.h | 15 +++++++++++++++ intel/intel_bufmgr_fake.c | 5 +++++ tests/drmstat.c | 10 ++++++++++ 4 files changed, 37 insertions(+) New commits: commit dc1ed9952e639f3d5fb41401598d28c4a97f5a1c Author: Alan Coopersmith <ala...@su...> Date: Sat Jan 16 19:34:13 2010 -0800 Support gcc's __FUNCTION__ for people using other compilers Signed-off-by: Alan Coopersmith <ala...@su...> diff --git a/intel/intel_bufmgr_fake.c b/intel/intel_bufmgr_fake.c index 54b3cb8..9914952 100644 --- a/intel/intel_bufmgr_fake.c +++ b/intel/intel_bufmgr_fake.c @@ -51,6 +51,11 @@ #include "mm.h" #include "libdrm_lists.h" +/* Support gcc's __FUNCTION__ for people using other compilers */ +#if !defined(__GNUC__) && !defined(__FUNCTION__) +# define __FUNCTION__ __func__ /* C99 */ +#endif + #define DBG(...) do { \ if (bufmgr_fake->bufmgr.debug) \ drmMsg(__VA_ARGS__); \ diff --git a/tests/drmstat.c b/tests/drmstat.c index e2e7523..345b8d2 100644 --- a/tests/drmstat.c +++ b/tests/drmstat.c @@ -46,6 +46,11 @@ #endif #include "xf86drm.h" +/* Support gcc's __FUNCTION__ for people using other compilers */ +#if !defined(__GNUC__) && !defined(__FUNCTION__) +# define __FUNCTION__ __func__ /* C99 */ +#endif + int sigio_fd; static double usec(struct timeval *end, struct timeval *start) commit b1ce1e6bfbb65cca3230762cf99d4c0775561781 Author: Alan Coopersmith <ala...@su...> Date: Sat Jan 16 19:28:50 2010 -0800 Add support for Solaris libc atomic operations Signed-off-by: Alan Coopersmith <ala...@su...> diff --git a/configure.ac b/configure.ac index b257ccf..49e193e 100644 --- a/configure.ac +++ b/configure.ac @@ -186,6 +186,12 @@ if test "x$INTEL" != "xno"; then AC_CHECK_HEADER([atomic_ops.h], drm_cv_atomic_primitives="libatomic-ops") fi + # atomic functions defined in <atomic.h> & libc on Solaris + if test "x$drm_cv_atomic_primitives" = "xnone"; then + AC_CHECK_FUNC([atomic_cas_uint], + drm_cv_atomic_primitives="Solaris") + fi + ]) if test "x$drm_cv_atomic_primitives" = xIntel; then AC_DEFINE(HAVE_INTEL_ATOMIC_PRIMITIVES, 1, diff --git a/intel/intel_atomic.h b/intel/intel_atomic.h index e725c4a..12bb96b 100644 --- a/intel/intel_atomic.h +++ b/intel/intel_atomic.h @@ -71,6 +71,21 @@ typedef struct { #endif +#if defined(__sun) && !defined(HAS_ATOMIC_OPS) /* Solaris & OpenSolaris */ + +#include <sys/atomic.h> +#define HAS_ATOMIC_OPS 1 + +typedef struct { uint_t atomic; } atomic_t; + +# define atomic_read(x) (int) ((x)->atomic) +# define atomic_set(x, val) ((x)->atomic = (uint_t)(val)) +# define atomic_inc(x) (atomic_inc_uint (&(x)->atomic)) +# define atomic_dec_and_test(x) (atomic_dec_uint_nv(&(x)->atomic) == 1) +# define atomic_cmpxchg(x, oldv, newv) atomic_cas_uint (&(x)->atomic, oldv, newv) + +#endif + #if ! HAS_ATOMIC_OPS #error libdrm-intel requires atomic operations, please define them for your CPU/compiler. #endif commit fe7b93fb493b76ade13ad74438acbc4d34d2f3bd Author: Alan Coopersmith <ala...@su...> Date: Wed Dec 16 15:03:58 2009 -0800 Include alloca.h in tests/drmstat.c when configure detects it Signed-off-by: Alan Coopersmith <ala...@su...> diff --git a/configure.ac b/configure.ac index d3dc154..b257ccf 100644 --- a/configure.ac +++ b/configure.ac @@ -32,6 +32,7 @@ AC_PROG_CC AC_HEADER_STDC AC_SYS_LARGEFILE +AC_FUNC_ALLOCA PKG_CHECK_MODULES(PTHREADSTUBS, pthread-stubs) AC_SUBST(PTHREADSTUBS_CFLAGS) diff --git a/tests/drmstat.c b/tests/drmstat.c index ed2aeb6..e2e7523 100644 --- a/tests/drmstat.c +++ b/tests/drmstat.c @@ -28,6 +28,8 @@ * */ +#include "config.h" + #include <stdio.h> #include <stdlib.h> #include <unistd.h> @@ -39,6 +41,9 @@ #include <errno.h> #include <signal.h> #include <fcntl.h> +#ifdef HAVE_ALLOCA_H +# include <alloca.h> +#endif #include "xf86drm.h" int sigio_fd; |
From: <wal...@ke...> - 2010-02-18 14:01:08
|
configure.ac | 6 ++-- include/drm/vmwgfx_drm.h | 63 ++++++++++++----------------------------------- libkms/Makefile.am | 1 3 files changed, 21 insertions(+), 49 deletions(-) New commits: commit 97003c53f9d9ce8b13f6bde28eeb255c35f0c3bc Author: Jakob Bornecrantz <ja...@vm...> Date: Thu Feb 18 13:27:29 2010 +0100 libkms: Enable by default diff --git a/configure.ac b/configure.ac index f152f24..ef7700f 100644 --- a/configure.ac +++ b/configure.ac @@ -45,9 +45,9 @@ AC_ARG_ENABLE(udev, AS_HELP_STRING([--enable-udev], [UDEV=$enableval], [UDEV=no]) AC_ARG_ENABLE(libkms, - AS_HELP_STRING([--enable-libkms], - [Enable KMS mm abstraction library (default: disabled)]), - [LIBKMS=$enableval], [LIBKMS=no]) + AS_HELP_STRING([--disable-libkms], + [Disable KMS mm abstraction library (default: enabled)]), + [LIBKMS=$enableval], [LIBKMS=yes]) AC_ARG_ENABLE(intel, AS_HELP_STRING([--disable-intel], commit 25c0c638c417ec0d7130b06b39af89c264b89983 Author: Jakob Bornecrantz <ja...@vm...> Date: Thu Feb 18 13:14:07 2010 +0100 libkms: Add missing include file to libkms source diff --git a/libkms/Makefile.am b/libkms/Makefile.am index 293045c..e84deb1 100644 --- a/libkms/Makefile.am +++ b/libkms/Makefile.am @@ -12,6 +12,7 @@ libkms_la_LIBADD = #endif libkms_la_SOURCES = \ + internal.h \ linux.c \ intel.c \ api.c commit c9cfe749f7c0a83f3ca00ab2a9aeb4afeee400db Author: Jakob Bornecrantz <ja...@vm...> Date: Thu Feb 18 13:27:59 2010 +0100 vmwgfx: Update kernel header diff --git a/include/drm/vmwgfx_drm.h b/include/drm/vmwgfx_drm.h index 2be7e12..47914bd 100644 --- a/include/drm/vmwgfx_drm.h +++ b/include/drm/vmwgfx_drm.h @@ -68,7 +68,8 @@ #define DRM_VMW_PARAM_NUM_FREE_STREAMS 1 #define DRM_VMW_PARAM_3D 2 #define DRM_VMW_PARAM_FIFO_OFFSET 3 - +#define DRM_VMW_PARAM_HW_CAPS 4 +#define DRM_VMW_PARAM_FIFO_CAPS 5 /** * struct drm_vmw_getparam_arg @@ -87,49 +88,6 @@ struct drm_vmw_getparam_arg { /*************************************************************************/ /** - * DRM_VMW_EXTENSION - Query device extensions. - */ - -/** - * struct drm_vmw_extension_rep - * - * @exists: The queried extension exists. - * @driver_ioctl_offset: Ioctl number of the first ioctl in the extension. - * @driver_sarea_offset: Offset to any space in the DRI SAREA - * used by the extension. - * @major: Major version number of the extension. - * @minor: Minor version number of the extension. - * @pl: Patch level version number of the extension. - * - * Output argument to the DRM_VMW_EXTENSION Ioctl. - */ - -struct drm_vmw_extension_rep { - int32_t exists; - uint32_t driver_ioctl_offset; - uint32_t driver_sarea_offset; - uint32_t major; - uint32_t minor; - uint32_t pl; - uint32_t pad64; -}; - -/** - * union drm_vmw_extension_arg - * - * @extension - Ascii name of the extension to be queried. //In - * @rep - Reply as defined above. //Out - * - * Argument to the DRM_VMW_EXTENSION Ioctl. - */ - -union drm_vmw_extension_arg { - char extension[DRM_VMW_EXT_NAME_LEN]; - struct drm_vmw_extension_rep rep; -}; - -/*************************************************************************/ -/** * DRM_VMW_CREATE_CONTEXT - Create a host context. * * Allocates a device unique context id, and queues a create context command @@ -181,6 +139,8 @@ struct drm_vmw_context_arg { * The size of the array should equal the total number of mipmap levels. * @shareable: Boolean whether other clients (as identified by file descriptors) * may reference this surface. + * @scanout: Boolean whether the surface is intended to be used as a + * scanout. * * Input data to the DRM_VMW_CREATE_SURFACE Ioctl. * Output data from the DRM_VMW_REF_SURFACE Ioctl. @@ -192,7 +152,7 @@ struct drm_vmw_surface_create_req { uint32_t mip_levels[DRM_VMW_MAX_SURFACE_FACES]; uint64_t size_addr; int32_t shareable; - uint32_t pad64; + int32_t scanout; }; /** @@ -295,17 +255,28 @@ union drm_vmw_surface_reference_arg { * * @commands: User-space address of a command buffer cast to an uint64_t. * @command-size: Size in bytes of the command buffer. + * @throttle-us: Sleep until software is less than @throttle_us + * microseconds ahead of hardware. The driver may round this value + * to the nearest kernel tick. * @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an * uint64_t. + * @version: Allows expanding the execbuf ioctl parameters without breaking + * backwards compatibility, since user-space will always tell the kernel + * which version it uses. + * @flags: Execbuf flags. None currently. * * Argument to the DRM_VMW_EXECBUF Ioctl. */ +#define DRM_VMW_EXECBUF_VERSION 0 + struct drm_vmw_execbuf_arg { uint64_t commands; uint32_t command_size; - uint32_t pad64; + uint32_t throttle_us; uint64_t fence_rep; + uint32_t version; + uint32_t flags; }; /** |
From: <dar...@ke...> - 2010-03-19 00:22:29
|
nouveau/nouveau_bo.c | 2 +- nouveau/nouveau_channel.c | 2 +- nouveau/nouveau_private.h | 1 - 3 files changed, 2 insertions(+), 3 deletions(-) New commits: commit c1c8bbf80b1f734e23996bf805dc78f32ebaf56f Author: Ben Skeggs <bs...@re...> Date: Fri Mar 19 10:20:09 2010 +1000 nouveau: fix annoying compiler warning diff --git a/nouveau/nouveau_channel.c b/nouveau/nouveau_channel.c index 5622c1d..40a0b34 100644 --- a/nouveau/nouveau_channel.c +++ b/nouveau/nouveau_channel.c @@ -106,7 +106,7 @@ nouveau_channel_free(struct nouveau_channel **chan) struct nouveau_channel_priv *nvchan; struct nouveau_device_priv *nvdev; struct drm_nouveau_channel_free cf; - int i; + unsigned i; if (!chan || !*chan) return; commit df32c307e8f81b46ee8aa4dd7222fc18f175bbb3 Author: Ben Skeggs <bs...@re...> Date: Fri Mar 19 10:17:19 2010 +1000 nouveau: fix segfault in nouveau_bo_new_tile() failure path diff --git a/nouveau/nouveau_bo.c b/nouveau/nouveau_bo.c index 4973636..32b23b6 100644 --- a/nouveau/nouveau_bo.c +++ b/nouveau/nouveau_bo.c @@ -198,7 +198,7 @@ nouveau_bo_new_tile(struct nouveau_device *dev, uint32_t flags, int align, if (flags & (NOUVEAU_BO_VRAM | NOUVEAU_BO_GART)) { ret = nouveau_bo_kalloc(nvbo, NULL); if (ret) { - nouveau_bo_ref(NULL, (void *)nvbo); + nouveau_bo_ref(NULL, (void *)&nvbo); return ret; } } commit a247fca8ba5759979607a514dbda4e4a63676889 Author: Ben Skeggs <bs...@re...> Date: Mon Feb 22 16:22:51 2010 +1000 nouveau: remove unused field from nouveau_bo diff --git a/nouveau/nouveau_private.h b/nouveau/nouveau_private.h index c08fa38..5a952f7 100644 --- a/nouveau/nouveau_private.h +++ b/nouveau/nouveau_private.h @@ -118,7 +118,6 @@ struct nouveau_bo_priv { void *map; /* Last known information from kernel on buffer status */ - int pinned; uint64_t offset; uint32_t domain; }; |
From: <ic...@ke...> - 2011-12-13 11:06:06
|
configure.ac | 2 +- intel/intel_bufmgr_gem.c | 20 ++++++++++++++------ 2 files changed, 15 insertions(+), 7 deletions(-) New commits: commit 7fd1678110b78d9324723a54dfd5049496b9e3cf Author: Chris Wilson <ch...@ch...> Date: Mon Dec 5 23:09:20 2011 +0000 configure: Bump version for 2.4.29 Yet another release required for new API diff --git a/configure.ac b/configure.ac index 829e8d2..5f144bc 100644 --- a/configure.ac +++ b/configure.ac @@ -20,7 +20,7 @@ AC_PREREQ([2.63]) AC_INIT([libdrm], - [2.4.28], + [2.4.29], [https://bugs.freedesktop.org/enter_bug.cgi?product=DRI], [libdrm]) commit 015286f03e871ccf49af9f2ceef7f5e04c8d61ca Author: Chris Wilson <ch...@ch...> Date: Sun Dec 11 17:35:06 2011 +0000 intel: Remove the fresh assertions used to debug the vma cacheing Hopefully all the bugs in the callers have been found, so time to handle the failures "gracefully" again. Signed-off-by: Chris Wilson <ch...@ch...> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index bb096de..19441f3 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -1098,8 +1098,8 @@ static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable) if (!bo_gem->mem_virtual) { struct drm_i915_gem_mmap mmap_arg; - DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name); - assert(bo_gem->map_count == 1); + DBG("bo_map: %d (%s), map_count=%d\n", + bo_gem->gem_handle, bo_gem->name, bo_gem->map_count); memset(&mmap_arg, 0, sizeof(mmap_arg)); mmap_arg.handle = bo_gem->gem_handle; @@ -1163,9 +1163,8 @@ int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo) if (bo_gem->gtt_virtual == NULL) { struct drm_i915_gem_mmap_gtt mmap_arg; - DBG("bo_map_gtt: mmap %d (%s)\n", bo_gem->gem_handle, - bo_gem->name); - assert(bo_gem->map_count == 1); + DBG("bo_map_gtt: mmap %d (%s), map_count=%d\n", + bo_gem->gem_handle, bo_gem->name, bo_gem->map_count); memset(&mmap_arg, 0, sizeof(mmap_arg)); mmap_arg.handle = bo_gem->gem_handle; @@ -1239,7 +1238,14 @@ static int drm_intel_gem_bo_unmap(drm_intel_bo *bo) pthread_mutex_lock(&bufmgr_gem->lock); - assert(bo_gem->map_count > 0); + if (bo_gem->map_count <= 0) { + DBG("attempted to unmap an unmapped bo\n"); + pthread_mutex_unlock(&bufmgr_gem->lock); + /* Preserve the old behaviour of just treating this as a + * no-op rather than reporting the error. + */ + return 0; + } if (bo_gem->mapped_cpu_write) { /* Cause a flush to happen if the buffer's pinned for commit c5f0ed1d296f11367febd0e1b7dce8789308bf35 Author: Chris Wilson <ch...@ch...> Date: Tue Dec 13 10:30:54 2011 +0000 intel: Update map-count for an early error return during mapping Signed-off-by: Chris Wilson <ch...@ch...> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 55ff5ab..bb096de 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -1180,6 +1180,8 @@ int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo) __FILE__, __LINE__, bo_gem->gem_handle, bo_gem->name, strerror(errno)); + if (--bo_gem->map_count == 0) + drm_intel_gem_bo_close_vma(bufmgr_gem, bo_gem); pthread_mutex_unlock(&bufmgr_gem->lock); return ret; } |
From: <an...@ke...> - 2012-01-04 22:51:16
|
configure.ac | 2 intel/.gitignore | 1 intel/Makefile.am | 22 intel/intel_bufmgr.h | 2 intel/intel_decode.c | 14 intel/test_decode.c | 191 +++++ intel/tests/.gitignore | 1 intel/tests/gen4-3d.batch |binary intel/tests/gen4-3d.batch-ref.txt | 488 +++++++++++++ intel/tests/gen4-3d.batch.sh | 1 intel/tests/gen5-3d.batch |binary intel/tests/gen5-3d.batch-ref.txt | 512 ++++++++++++++ intel/tests/gen5-3d.batch.sh | 1 intel/tests/gen6-3d.batch |binary intel/tests/gen6-3d.batch-ref.txt | 990 +++++++++++++++++++++++++++ intel/tests/gen6-3d.batch.sh | 1 intel/tests/gen7-3d.batch |binary intel/tests/gen7-3d.batch-ref.txt | 1350 ++++++++++++++++++++++++++++++++++++++ intel/tests/gen7-3d.batch.sh | 1 intel/tests/gm45-3d.batch |binary intel/tests/gm45-3d.batch-ref.txt | 488 +++++++++++++ intel/tests/gm45-3d.batch.sh | 1 intel/tests/test-batch.sh | 20 23 files changed, 4084 insertions(+), 2 deletions(-) New commits: commit 683855f65523c978562ead56f9d68f50ffdca1a2 Author: Eric Anholt <er...@an...> Date: Tue Jan 3 14:32:18 2012 -0800 intel: Add regression tests for batch decode. The .batch was generated using the dump-a-batch branch of git://people.freedesktop.org/~anholt/mesa using glxgears on gen7 hardware, using INTEL_DEVID_OVERRIDE for non-gen7 (this means that offsets in the buffers for non-gen7 are 0!). The .ref was generated by: ./test_decode tests/gen7-3d.batch -dump. The .sh exists because you can't supply arguments to tests using the simple automake tests driver. Something reasonable could be done using automake's parallel-tests driver (in fact, a previous version of the patch did that), but I was concerned that: 1) The parallel-tests driver is documented to be unstable -- they may change interfaces on us later. 2) The parallel-tests driver hides the output of tests in .log files scattered all over the tree, which was ugly and more painful to work with. v2: Actually add the batch files, add a .gitignore for the *-new.txt files added after failures, and fix failure mode for undetected chipset name. Reviewed-by: Daniel Vetter <dan...@ff...> (v1) diff --git a/intel/Makefile.am b/intel/Makefile.am index 2d3d8c4..581c8c0 100644 --- a/intel/Makefile.am +++ b/intel/Makefile.am @@ -57,6 +57,23 @@ libdrm_intelinclude_HEADERS = intel_bufmgr.h \ # This may be interesting even outside of "make check", due to the -dump option. noinst_PROGRAMS = test_decode +BATCHES = \ + tests/gen4-3d.batch \ + tests/gm45-3d.batch \ + tests/gen5-3d.batch \ + tests/gen6-3d.batch \ + tests/gen7-3d.batch + +TESTS = \ + $(BATCHES:.batch=.batch.sh) + +EXTRA_DIST = \ + $(BATCHES) \ + $(BATCHES:.batch=.batch.sh) \ + $(BATCHES:.batch=.batch-ref.txt) \ + $(BATCHES:.batch=.batch-ref.txt) \ + tests/test-batch.sh + test_decode_LDADD = libdrm_intel.la pkgconfig_DATA = libdrm_intel.pc diff --git a/intel/test_decode.c b/intel/test_decode.c index d41b0b2..c9ab7ad 100644 --- a/intel/test_decode.c +++ b/intel/test_decode.c @@ -144,6 +144,7 @@ infer_devid(const char *batch_filename) { "gen5", PCI_CHIP_ILD_G }, { "gen6", PCI_CHIP_SANDYBRIDGE_GT2 }, { "gen7", PCI_CHIP_IVYBRIDGE_GT2 }, + { NULL, 0 }, }; int i; diff --git a/intel/tests/.gitignore b/intel/tests/.gitignore new file mode 100644 index 0000000..e9d01ec --- /dev/null +++ b/intel/tests/.gitignore @@ -0,0 +1 @@ +*-new.txt diff --git a/intel/tests/gen4-3d.batch b/intel/tests/gen4-3d.batch new file mode 100644 index 0000000..e6911a4 Binary files /dev/null and b/intel/tests/gen4-3d.batch differ diff --git a/intel/tests/gen4-3d.batch-ref.txt b/intel/tests/gen4-3d.batch-ref.txt new file mode 100644 index 0000000..20aa1d4 --- /dev/null +++ b/intel/tests/gen4-3d.batch-ref.txt @@ -0,0 +1,488 @@ +0x12300000: 0x61040000: 3DSTATE_PIPELINE_SELECT +0x12300004: 0x79090000: 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP +0x12300008: 0x00000000: dword 1 +0x1230000c: 0x61020000: STATE_SIP +0x12300010: 0x00000000: dword 1 +0x12300014: 0x780b0000: 3DSTATE_VF_STATISTICS +0x12300018: 0x61010004: STATE_BASE_ADDRESS +0x1230001c: 0x00000001: general state base address 0x00000000 +0x12300020: 0x00000001: surface state base address 0x00000000 +0x12300024: 0x00000001: indirect state base address 0x00000000 +0x12300028: 0x00000001: general state upper bound disabled +0x1230002c: 0x00000001: indirect state upper bound disabled +0x12300030: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS +0x12300034: 0x00007e20: VS binding table +0x12300038: 0x00000000: GS binding table +0x1230003c: 0x00000000: Clip binding table +0x12300040: 0x00000000: SF binding table +0x12300044: 0x00007e20: WM binding table +0x12300048: 0x79010003: 3DSTATE_CONSTANT_COLOR +0x1230004c: 0x00000000: dword 1 +0x12300050: 0x00000000: dword 2 +0x12300054: 0x00000000: dword 3 +0x12300058: 0x00000000: dword 4 +0x1230005c: 0x79050003: 3DSTATE_DEPTH_BUFFER +0x12300060: 0x2c0805ff: 2D, z24s8, pitch = 1536 bytes, tiled +0x12300064: 0x00000000: depth offset +0x12300068: 0x09584ac0: 300x300 +0x1230006c: 0x00000000: volume depth +0x12300070: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300074: 0x00007d60: VS state +0x12300078: 0x00000000: GS state +0x1230007c: 0x00007d21: Clip state +0x12300080: 0x00007d80: SF state +0x12300084: 0x00007de0: WM state +0x12300088: 0x00007fc0: CC state +0x1230008c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300090: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300094: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x12300098: 0x60010000: CS_URB_STATE +0x1230009c: 0x00000024: entry_size: 2 [192 bytes], n_entries: 4 +0x123000a0: 0x79000002: 3DSTATE_DRAWING_RECTANGLE +0x123000a4: 0x00000000: top left: 0,0 +0x123000a8: 0x012b012b: bottom right: 299,299 +0x123000ac: 0x00000000: origin: 0,0 +0x123000b0: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x123000b4: 0x0000000c: buffer 0: sequential, pitch 12b +0x123000b8: 0x00000000: buffer address +0x123000bc: 0x00000000: max index +0x123000c0: 0x00000000: mbz +0x123000c4: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x123000c8: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123000cc: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123000d0: 0x60020100: CONSTANT_BUFFER: valid +0x123000d4: 0x00000001: offset: 0x00000000, length: 128 bytes +0x123000d8: 0x7b001804: 3DPRIMITIVE: tri fan sequential +0x123000dc: 0x00000004: vertex count +0x123000e0: 0x00000000: start vertex +0x123000e4: 0x00000001: instance count +0x123000e8: 0x00000000: start instance +0x123000ec: 0x00000000: index bias +0x123000f0: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS +0x123000f4: 0x00007b40: VS binding table +0x123000f8: 0x00000000: GS binding table +0x123000fc: 0x00000000: Clip binding table +0x12300100: 0x00000000: SF binding table +0x12300104: 0x00007b40: WM binding table +0x12300108: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x1230010c: 0x00007aa0: VS state +0x12300110: 0x00007a41: GS state +0x12300114: 0x00007a61: Clip state +0x12300118: 0x00007ac0: SF state +0x1230011c: 0x00007b00: WM state +0x12300120: 0x00007cc0: CC state +0x12300124: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300128: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x1230012c: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x12300130: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300134: 0x0000000c: buffer 0: sequential, pitch 12b +0x12300138: 0x00000000: buffer address +0x1230013c: 0x00000000: max index +0x12300140: 0x00000000: mbz +0x12300144: 0x60020100: CONSTANT_BUFFER: valid +0x12300148: 0x00000082: offset: 0x00000080, length: 192 bytes +0x1230014c: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300150: 0x00000052: vertex count +0x12300154: 0x00000000: start vertex +0x12300158: 0x00000001: instance count +0x1230015c: 0x00000000: start instance +0x12300160: 0x00000000: index bias +0x12300164: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300168: 0x00007aa0: VS state +0x1230016c: 0x00007a21: GS state +0x12300170: 0x00007a61: Clip state +0x12300174: 0x00007ac0: SF state +0x12300178: 0x00007b00: WM state +0x1230017c: 0x00007cc0: CC state +0x12300180: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300184: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300188: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230018c: 0x60020100: CONSTANT_BUFFER: valid +0x12300190: 0x00000082: offset: 0x00000080, length: 192 bytes +0x12300194: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300198: 0x00000050: vertex count +0x1230019c: 0x00000052: start vertex +0x123001a0: 0x00000001: instance count +0x123001a4: 0x00000000: start instance +0x123001a8: 0x00000000: index bias +0x123001ac: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123001b0: 0x00007aa0: VS state +0x123001b4: 0x00007a01: GS state +0x123001b8: 0x00007a61: Clip state +0x123001bc: 0x00007ac0: SF state +0x123001c0: 0x00007b00: WM state +0x123001c4: 0x00007cc0: CC state +0x123001c8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123001cc: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x123001d0: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x123001d4: 0x60020100: CONSTANT_BUFFER: valid +0x123001d8: 0x00000142: offset: 0x00000140, length: 192 bytes +0x123001dc: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x123001e0: 0x00000052: vertex count +0x123001e4: 0x000000a2: start vertex +0x123001e8: 0x00000001: instance count +0x123001ec: 0x00000000: start instance +0x123001f0: 0x00000000: index bias +0x123001f4: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123001f8: 0x00007aa0: VS state +0x123001fc: 0x000079e1: GS state +0x12300200: 0x00007a61: Clip state +0x12300204: 0x00007ac0: SF state +0x12300208: 0x00007b00: WM state +0x1230020c: 0x00007cc0: CC state +0x12300210: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300214: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300218: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230021c: 0x60020100: CONSTANT_BUFFER: valid +0x12300220: 0x00000142: offset: 0x00000140, length: 192 bytes +0x12300224: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300228: 0x00000050: vertex count +0x1230022c: 0x000000f4: start vertex +0x12300230: 0x00000001: instance count +0x12300234: 0x00000000: start instance +0x12300238: 0x00000000: index bias +0x1230023c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300240: 0x00007aa0: VS state +0x12300244: 0x000079c1: GS state +0x12300248: 0x00007a61: Clip state +0x1230024c: 0x00007ac0: SF state +0x12300250: 0x00007b00: WM state +0x12300254: 0x00007cc0: CC state +0x12300258: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230025c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300260: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x12300264: 0x60020100: CONSTANT_BUFFER: valid +0x12300268: 0x00000142: offset: 0x00000140, length: 192 bytes +0x1230026c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300270: 0x000079a0: VS state +0x12300274: 0x000079c1: GS state +0x12300278: 0x00007a61: Clip state +0x1230027c: 0x00007ac0: SF state +0x12300280: 0x00007b00: WM state +0x12300284: 0x00007cc0: CC state +0x12300288: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230028c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300290: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x12300294: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300298: 0x00000018: buffer 0: sequential, pitch 24b +0x1230029c: 0x00000f48: buffer address +0x123002a0: 0x00000000: max index +0x123002a4: 0x00000000: mbz +0x123002a8: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x123002ac: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123002b0: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123002b4: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x123002b8: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes +0x123002bc: 0x60020100: CONSTANT_BUFFER: valid +0x123002c0: 0x00000202: offset: 0x00000200, length: 192 bytes +0x123002c4: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x123002c8: 0x000000a2: vertex count +0x123002cc: 0x00000000: start vertex +0x123002d0: 0x00000001: instance count +0x123002d4: 0x00000000: start instance +0x123002d8: 0x00000000: index bias +0x123002dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123002e0: 0x000079a0: VS state +0x123002e4: 0x00000000: GS state +0x123002e8: 0x00007901: Clip state +0x123002ec: 0x00007940: SF state +0x123002f0: 0x00007960: WM state +0x123002f4: 0x00007cc0: CC state +0x123002f8: 0x00000000: MI_NOOP +0x123002fc: 0x00000000: MI_NOOP +0x12300300: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300304: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300308: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230030c: 0x60020100: CONSTANT_BUFFER: valid +0x12300310: 0x00000202: offset: 0x00000200, length: 192 bytes +0x12300314: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x12300318: 0x0000002a: vertex count +0x1230031c: 0x000000a2: start vertex +0x12300320: 0x00000001: instance count +0x12300324: 0x00000000: start instance +0x12300328: 0x00000000: index bias +0x1230032c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300330: 0x00007860: VS state +0x12300334: 0x00007801: GS state +0x12300338: 0x00007821: Clip state +0x1230033c: 0x00007880: SF state +0x12300340: 0x000078a0: WM state +0x12300344: 0x00007cc0: CC state +0x12300348: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230034c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300350: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x12300354: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300358: 0x0000000c: buffer 0: sequential, pitch 12b +0x1230035c: 0x00002268: buffer address +0x12300360: 0x00000000: max index +0x12300364: 0x00000000: mbz +0x12300368: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x1230036c: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x12300370: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x12300374: 0x60020100: CONSTANT_BUFFER: valid +0x12300378: 0x000002c2: offset: 0x000002c0, length: 192 bytes +0x1230037c: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300380: 0x0000002a: vertex count +0x12300384: 0x00000000: start vertex +0x12300388: 0x00000001: instance count +0x1230038c: 0x00000000: start instance +0x12300390: 0x00000000: index bias +0x12300394: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300398: 0x00007860: VS state +0x1230039c: 0x000077e1: GS state +0x123003a0: 0x00007821: Clip state +0x123003a4: 0x00007880: SF state +0x123003a8: 0x000078a0: WM state +0x123003ac: 0x00007cc0: CC state +0x123003b0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123003b4: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x123003b8: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x123003bc: 0x60020100: CONSTANT_BUFFER: valid +0x123003c0: 0x000002c2: offset: 0x000002c0, length: 192 bytes +0x123003c4: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x123003c8: 0x00000028: vertex count +0x123003cc: 0x0000002a: start vertex +0x123003d0: 0x00000001: instance count +0x123003d4: 0x00000000: start instance +0x123003d8: 0x00000000: index bias +0x123003dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123003e0: 0x00007860: VS state +0x123003e4: 0x000077c1: GS state +0x123003e8: 0x00007821: Clip state +0x123003ec: 0x00007880: SF state +0x123003f0: 0x000078a0: WM state +0x123003f4: 0x00007cc0: CC state +0x123003f8: 0x00000000: MI_NOOP +0x123003fc: 0x00000000: MI_NOOP +0x12300400: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300404: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300408: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230040c: 0x60020100: CONSTANT_BUFFER: valid +0x12300410: 0x00000382: offset: 0x00000380, length: 192 bytes +0x12300414: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300418: 0x0000002a: vertex count +0x1230041c: 0x00000052: start vertex +0x12300420: 0x00000001: instance count +0x12300424: 0x00000000: start instance +0x12300428: 0x00000000: index bias +0x1230042c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300430: 0x00007860: VS state +0x12300434: 0x000077a1: GS state +0x12300438: 0x00007821: Clip state +0x1230043c: 0x00007880: SF state +0x12300440: 0x000078a0: WM state +0x12300444: 0x00007cc0: CC state +0x12300448: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230044c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300450: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x12300454: 0x60020100: CONSTANT_BUFFER: valid +0x12300458: 0x00000382: offset: 0x00000380, length: 192 bytes +0x1230045c: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300460: 0x00000028: vertex count +0x12300464: 0x0000007c: start vertex +0x12300468: 0x00000001: instance count +0x1230046c: 0x00000000: start instance +0x12300470: 0x00000000: index bias +0x12300474: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300478: 0x00007860: VS state +0x1230047c: 0x00007781: GS state +0x12300480: 0x00007821: Clip state +0x12300484: 0x00007880: SF state +0x12300488: 0x000078a0: WM state +0x1230048c: 0x00007cc0: CC state +0x12300490: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300494: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300498: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230049c: 0x60020100: CONSTANT_BUFFER: valid +0x123004a0: 0x00000382: offset: 0x00000380, length: 192 bytes +0x123004a4: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123004a8: 0x00007760: VS state +0x123004ac: 0x00007781: GS state +0x123004b0: 0x00007821: Clip state +0x123004b4: 0x00007880: SF state +0x123004b8: 0x000078a0: WM state +0x123004bc: 0x00007cc0: CC state +0x123004c0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123004c4: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x123004c8: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x123004cc: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x123004d0: 0x00000018: buffer 0: sequential, pitch 24b +0x123004d4: 0x00002a30: buffer address +0x123004d8: 0x00000000: max index +0x123004dc: 0x00000000: mbz +0x123004e0: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x123004e4: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123004e8: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123004ec: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x123004f0: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes +0x123004f4: 0x60020100: CONSTANT_BUFFER: valid +0x123004f8: 0x00000442: offset: 0x00000440, length: 192 bytes +0x123004fc: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300500: 0x00000052: vertex count +0x12300504: 0x00000000: start vertex +0x12300508: 0x00000001: instance count +0x1230050c: 0x00000000: start instance +0x12300510: 0x00000000: index bias +0x12300514: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300518: 0x00007760: VS state +0x1230051c: 0x00000000: GS state +0x12300520: 0x000076c1: Clip state +0x12300524: 0x00007700: SF state +0x12300528: 0x00007720: WM state +0x1230052c: 0x00007cc0: CC state +0x12300530: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300534: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300538: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230053c: 0x60020100: CONSTANT_BUFFER: valid +0x12300540: 0x00000442: offset: 0x00000440, length: 192 bytes +0x12300544: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x12300548: 0x00000016: vertex count +0x1230054c: 0x00000052: start vertex +0x12300550: 0x00000001: instance count +0x12300554: 0x00000000: start instance +0x12300558: 0x00000000: index bias +0x1230055c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300560: 0x00007620: VS state +0x12300564: 0x000075c1: GS state +0x12300568: 0x000075e1: Clip state +0x1230056c: 0x00007640: SF state +0x12300570: 0x00007660: WM state +0x12300574: 0x00007cc0: CC state +0x12300578: 0x00000000: MI_NOOP +0x1230057c: 0x00000000: MI_NOOP +0x12300580: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300584: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300588: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230058c: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300590: 0x0000000c: buffer 0: sequential, pitch 12b +0x12300594: 0x000033f0: buffer address +0x12300598: 0x00000000: max index +0x1230059c: 0x00000000: mbz +0x123005a0: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x123005a4: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123005a8: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123005ac: 0x60020100: CONSTANT_BUFFER: valid +0x123005b0: 0x00000502: offset: 0x00000500, length: 192 bytes +0x123005b4: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x123005b8: 0x0000002a: vertex count +0x123005bc: 0x00000000: start vertex +0x123005c0: 0x00000001: instance count +0x123005c4: 0x00000000: start instance +0x123005c8: 0x00000000: index bias +0x123005cc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123005d0: 0x00007620: VS state +0x123005d4: 0x000075a1: GS state +0x123005d8: 0x000075e1: Clip state +0x123005dc: 0x00007640: SF state +0x123005e0: 0x00007660: WM state +0x123005e4: 0x00007cc0: CC state +0x123005e8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123005ec: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x123005f0: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x123005f4: 0x60020100: CONSTANT_BUFFER: valid +0x123005f8: 0x00000502: offset: 0x00000500, length: 192 bytes +0x123005fc: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300600: 0x00000028: vertex count +0x12300604: 0x0000002a: start vertex +0x12300608: 0x00000001: instance count +0x1230060c: 0x00000000: start instance +0x12300610: 0x00000000: index bias +0x12300614: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300618: 0x00007620: VS state +0x1230061c: 0x00007581: GS state +0x12300620: 0x000075e1: Clip state +0x12300624: 0x00007640: SF state +0x12300628: 0x00007660: WM state +0x1230062c: 0x00007cc0: CC state +0x12300630: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300634: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300638: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230063c: 0x60020100: CONSTANT_BUFFER: valid +0x12300640: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x12300644: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300648: 0x0000002a: vertex count +0x1230064c: 0x00000052: start vertex +0x12300650: 0x00000001: instance count +0x12300654: 0x00000000: start instance +0x12300658: 0x00000000: index bias +0x1230065c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300660: 0x00007620: VS state +0x12300664: 0x00007561: GS state +0x12300668: 0x000075e1: Clip state +0x1230066c: 0x00007640: SF state +0x12300670: 0x00007660: WM state +0x12300674: 0x00007cc0: CC state +0x12300678: 0x00000000: MI_NOOP +0x1230067c: 0x00000000: MI_NOOP +0x12300680: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300684: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300688: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230068c: 0x60020100: CONSTANT_BUFFER: valid +0x12300690: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x12300694: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300698: 0x00000028: vertex count +0x1230069c: 0x0000007c: start vertex +0x123006a0: 0x00000001: instance count +0x123006a4: 0x00000000: start instance +0x123006a8: 0x00000000: index bias +0x123006ac: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123006b0: 0x00007620: VS state +0x123006b4: 0x00007541: GS state +0x123006b8: 0x000075e1: Clip state +0x123006bc: 0x00007640: SF state +0x123006c0: 0x00007660: WM state +0x123006c4: 0x00007cc0: CC state +0x123006c8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123006cc: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x123006d0: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x123006d4: 0x60020100: CONSTANT_BUFFER: valid +0x123006d8: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x123006dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123006e0: 0x00007520: VS state +0x123006e4: 0x00007541: GS state +0x123006e8: 0x000075e1: Clip state +0x123006ec: 0x00007640: SF state +0x123006f0: 0x00007660: WM state +0x123006f4: 0x00007cc0: CC state +0x123006f8: 0x00000000: MI_NOOP +0x123006fc: 0x00000000: MI_NOOP +0x12300700: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300704: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300708: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230070c: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300710: 0x00000018: buffer 0: sequential, pitch 24b +0x12300714: 0x00003bb8: buffer address +0x12300718: 0x00000000: max index +0x1230071c: 0x00000000: mbz +0x12300720: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x12300724: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x12300728: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x1230072c: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x12300730: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes +0x12300734: 0x60020100: CONSTANT_BUFFER: valid +0x12300738: 0x00000682: offset: 0x00000680, length: 192 bytes +0x1230073c: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300740: 0x00000052: vertex count +0x12300744: 0x00000000: start vertex +0x12300748: 0x00000001: instance count +0x1230074c: 0x00000000: start instance +0x12300750: 0x00000000: index bias +0x12300754: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300758: 0x00007520: VS state +0x1230075c: 0x00000000: GS state +0x12300760: 0x00007481: Clip state +0x12300764: 0x000074c0: SF state +0x12300768: 0x000074e0: WM state +0x1230076c: 0x00007cc0: CC state +0x12300770: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300774: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 +0x12300778: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 +0x1230077c: 0x60020100: CONSTANT_BUFFER: valid +0x12300780: 0x00000682: offset: 0x00000680, length: 192 bytes +0x12300784: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x12300788: 0x00000016: vertex count +0x1230078c: 0x00000052: start vertex +0x12300790: 0x00000001: instance count +0x12300794: 0x00000000: start instance +0x12300798: 0x00000000: index bias +0x1230079c: 0x05000000: MI_BATCH_BUFFER_END diff --git a/intel/tests/gen4-3d.batch.sh b/intel/tests/gen4-3d.batch.sh new file mode 120000 index 0000000..796ca5f --- /dev/null +++ b/intel/tests/gen4-3d.batch.sh @@ -0,0 +1 @@ +test-batch.sh \ No newline at end of file diff --git a/intel/tests/gen5-3d.batch b/intel/tests/gen5-3d.batch new file mode 100644 index 0000000..cf9d8d8 Binary files /dev/null and b/intel/tests/gen5-3d.batch differ diff --git a/intel/tests/gen5-3d.batch-ref.txt b/intel/tests/gen5-3d.batch-ref.txt new file mode 100644 index 0000000..a0271ab --- /dev/null +++ b/intel/tests/gen5-3d.batch-ref.txt @@ -0,0 +1,512 @@ +0x12300000: 0x69040000: 3DSTATE_PIPELINE_SELECT +0x12300004: 0x79090000: 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP +0x12300008: 0x00000000: dword 1 +0x1230000c: 0x61020000: STATE_SIP +0x12300010: 0x00000000: dword 1 +0x12300014: 0x680b0000: 3DSTATE_VF_STATISTICS +0x12300018: 0x61010006: STATE_BASE_ADDRESS +0x1230001c: 0x00000001: general state base address 0x00000000 +0x12300020: 0x00000001: surface state base address 0x00000000 +0x12300024: 0x00000001: indirect state base address 0x00000000 +0x12300028: 0x00000001: instruction state base address 0x00000000 +0x1230002c: 0x00000001: general state upper bound disabled +0x12300030: 0x00000001: indirect state upper bound disabled +0x12300034: 0x00000001: instruction state upper bound disabled +0x12300038: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS +0x1230003c: 0x00007e20: VS binding table +0x12300040: 0x00000000: GS binding table +0x12300044: 0x00000000: Clip binding table +0x12300048: 0x00000000: SF binding table +0x1230004c: 0x00007e20: WM binding table +0x12300050: 0x79010003: 3DSTATE_CONSTANT_COLOR +0x12300054: 0x00000000: dword 1 +0x12300058: 0x00000000: dword 2 +0x1230005c: 0x00000000: dword 3 +0x12300060: 0x00000000: dword 4 +0x12300064: 0x79050004: 3DSTATE_DEPTH_BUFFER +0x12300068: 0x2c0805ff: 2D, z24s8, pitch = 1536 bytes, tiled, HiZ 0, Seperate Stencil 0 +0x1230006c: 0x00000000: depth offset +0x12300070: 0x09584ac0: 300x300 +0x12300074: 0x00000000: volume depth +0x12300078: 0x00000000: +0x1230007c: 0x02000000: MI_FLUSH +0x12300080: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300084: 0x00007d60: VS state +0x12300088: 0x00000000: GS state +0x1230008c: 0x00007d21: Clip state +0x12300090: 0x00007d80: SF state +0x12300094: 0x00007de0: WM state +0x12300098: 0x00007fc0: CC state +0x1230009c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123000a0: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123000a4: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123000a8: 0x60010000: CS_URB_STATE +0x123000ac: 0x00000024: entry_size: 2 [192 bytes], n_entries: 4 +0x123000b0: 0x79000002: 3DSTATE_DRAWING_RECTANGLE +0x123000b4: 0x00000000: top left: 0,0 +0x123000b8: 0x012b012b: bottom right: 299,299 +0x123000bc: 0x00000000: origin: 0,0 +0x123000c0: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x123000c4: 0x0000000c: buffer 0: sequential, pitch 12b +0x123000c8: 0x00000000: buffer address +0x123000cc: 0x0000ffff: max index +0x123000d0: 0x00000000: mbz +0x123000d4: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x123000d8: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123000dc: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123000e0: 0x60020100: CONSTANT_BUFFER: valid +0x123000e4: 0x00000001: offset: 0x00000000, length: 128 bytes +0x123000e8: 0x7b001804: 3DPRIMITIVE: tri fan sequential +0x123000ec: 0x00000004: vertex count +0x123000f0: 0x00000000: start vertex +0x123000f4: 0x00000001: instance count +0x123000f8: 0x00000000: start instance +0x123000fc: 0x00000000: index bias +0x12300100: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS +0x12300104: 0x00007b40: VS binding table +0x12300108: 0x00000000: GS binding table +0x1230010c: 0x00000000: Clip binding table +0x12300110: 0x00000000: SF binding table +0x12300114: 0x00007b40: WM binding table +0x12300118: 0x02000000: MI_FLUSH +0x1230011c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300120: 0x00007aa0: VS state +0x12300124: 0x00007a41: GS state +0x12300128: 0x00007a61: Clip state +0x1230012c: 0x00007ac0: SF state +0x12300130: 0x00007b00: WM state +0x12300134: 0x00007cc0: CC state +0x12300138: 0x00000000: MI_NOOP +0x1230013c: 0x00000000: MI_NOOP +0x12300140: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300144: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300148: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x1230014c: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300150: 0x0000000c: buffer 0: sequential, pitch 12b +0x12300154: 0x00000000: buffer address +0x12300158: 0x00007fff: max index +0x1230015c: 0x00000000: mbz +0x12300160: 0x60020100: CONSTANT_BUFFER: valid +0x12300164: 0x00000082: offset: 0x00000080, length: 192 bytes +0x12300168: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x1230016c: 0x00000052: vertex count +0x12300170: 0x00000000: start vertex +0x12300174: 0x00000001: instance count +0x12300178: 0x00000000: start instance +0x1230017c: 0x00000000: index bias +0x12300180: 0x02000000: MI_FLUSH +0x12300184: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300188: 0x00007aa0: VS state +0x1230018c: 0x00007a21: GS state +0x12300190: 0x00007a61: Clip state +0x12300194: 0x00007ac0: SF state +0x12300198: 0x00007b00: WM state +0x1230019c: 0x00007cc0: CC state +0x123001a0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123001a4: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123001a8: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123001ac: 0x60020100: CONSTANT_BUFFER: valid +0x123001b0: 0x00000082: offset: 0x00000080, length: 192 bytes +0x123001b4: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x123001b8: 0x00000050: vertex count +0x123001bc: 0x00000052: start vertex +0x123001c0: 0x00000001: instance count +0x123001c4: 0x00000000: start instance +0x123001c8: 0x00000000: index bias +0x123001cc: 0x02000000: MI_FLUSH +0x123001d0: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123001d4: 0x00007aa0: VS state +0x123001d8: 0x00007a01: GS state +0x123001dc: 0x00007a61: Clip state +0x123001e0: 0x00007ac0: SF state +0x123001e4: 0x00007b00: WM state +0x123001e8: 0x00007cc0: CC state +0x123001ec: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123001f0: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123001f4: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123001f8: 0x60020100: CONSTANT_BUFFER: valid +0x123001fc: 0x00000142: offset: 0x00000140, length: 192 bytes +0x12300200: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300204: 0x00000052: vertex count +0x12300208: 0x000000a2: start vertex +0x1230020c: 0x00000001: instance count +0x12300210: 0x00000000: start instance +0x12300214: 0x00000000: index bias +0x12300218: 0x02000000: MI_FLUSH +0x1230021c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300220: 0x00007aa0: VS state +0x12300224: 0x000079e1: GS state +0x12300228: 0x00007a61: Clip state +0x1230022c: 0x00007ac0: SF state +0x12300230: 0x00007b00: WM state +0x12300234: 0x00007cc0: CC state +0x12300238: 0x00000000: MI_NOOP +0x1230023c: 0x00000000: MI_NOOP +0x12300240: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300244: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300248: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x1230024c: 0x60020100: CONSTANT_BUFFER: valid +0x12300250: 0x00000142: offset: 0x00000140, length: 192 bytes +0x12300254: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300258: 0x00000050: vertex count +0x1230025c: 0x000000f4: start vertex +0x12300260: 0x00000001: instance count +0x12300264: 0x00000000: start instance +0x12300268: 0x00000000: index bias +0x1230026c: 0x02000000: MI_FLUSH +0x12300270: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300274: 0x00007aa0: VS state +0x12300278: 0x000079c1: GS state +0x1230027c: 0x00007a61: Clip state +0x12300280: 0x00007ac0: SF state +0x12300284: 0x00007b00: WM state +0x12300288: 0x00007cc0: CC state +0x1230028c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300290: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300294: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300298: 0x60020100: CONSTANT_BUFFER: valid +0x1230029c: 0x00000142: offset: 0x00000140, length: 192 bytes +0x123002a0: 0x02000000: MI_FLUSH +0x123002a4: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123002a8: 0x000079a0: VS state +0x123002ac: 0x000079c1: GS state +0x123002b0: 0x00007a61: Clip state +0x123002b4: 0x00007ac0: SF state +0x123002b8: 0x00007b00: WM state +0x123002bc: 0x00007cc0: CC state +0x123002c0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123002c4: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123002c8: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123002cc: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x123002d0: 0x00000018: buffer 0: sequential, pitch 24b +0x123002d4: 0x00000f48: buffer address +0x123002d8: 0x00007fff: max index +0x123002dc: 0x00000000: mbz +0x123002e0: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x123002e4: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123002e8: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123002ec: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x123002f0: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123002f4: 0x60020100: CONSTANT_BUFFER: valid +0x123002f8: 0x00000202: offset: 0x00000200, length: 192 bytes +0x123002fc: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300300: 0x000000a2: vertex count +0x12300304: 0x00000000: start vertex +0x12300308: 0x00000001: instance count +0x1230030c: 0x00000000: start instance +0x12300310: 0x00000000: index bias +0x12300314: 0x02000000: MI_FLUSH +0x12300318: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x1230031c: 0x000079a0: VS state +0x12300320: 0x00000000: GS state +0x12300324: 0x00007901: Clip state +0x12300328: 0x00007940: SF state +0x1230032c: 0x00007960: WM state +0x12300330: 0x00007cc0: CC state +0x12300334: 0x00000000: MI_NOOP +0x12300338: 0x00000000: MI_NOOP +0x1230033c: 0x00000000: MI_NOOP +0x12300340: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300344: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300348: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x1230034c: 0x60020100: CONSTANT_BUFFER: valid +0x12300350: 0x00000202: offset: 0x00000200, length: 192 bytes +0x12300354: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x12300358: 0x0000002a: vertex count +0x1230035c: 0x000000a2: start vertex +0x12300360: 0x00000001: instance count +0x12300364: 0x00000000: start instance +0x12300368: 0x00000000: index bias +0x1230036c: 0x02000000: MI_FLUSH +0x12300370: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300374: 0x00007860: VS state +0x12300378: 0x00007801: GS state +0x1230037c: 0x00007821: Clip state +0x12300380: 0x00007880: SF state +0x12300384: 0x000078a0: WM state +0x12300388: 0x00007cc0: CC state +0x1230038c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300390: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300394: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300398: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x1230039c: 0x0000000c: buffer 0: sequential, pitch 12b +0x123003a0: 0x00002268: buffer address +0x123003a4: 0x00007fff: max index +0x123003a8: 0x00000000: mbz +0x123003ac: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x123003b0: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x123003b4: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x123003b8: 0x60020100: CONSTANT_BUFFER: valid +0x123003bc: 0x000002c2: offset: 0x000002c0, length: 192 bytes +0x123003c0: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x123003c4: 0x0000002a: vertex count +0x123003c8: 0x00000000: start vertex +0x123003cc: 0x00000001: instance count +0x123003d0: 0x00000000: start instance +0x123003d4: 0x00000000: index bias +0x123003d8: 0x02000000: MI_FLUSH +0x123003dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123003e0: 0x00007860: VS state +0x123003e4: 0x000077e1: GS state +0x123003e8: 0x00007821: Clip state +0x123003ec: 0x00007880: SF state +0x123003f0: 0x000078a0: WM state +0x123003f4: 0x00007cc0: CC state +0x123003f8: 0x00000000: MI_NOOP +0x123003fc: 0x00000000: MI_NOOP +0x12300400: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300404: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300408: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x1230040c: 0x60020100: CONSTANT_BUFFER: valid +0x12300410: 0x000002c2: offset: 0x000002c0, length: 192 bytes +0x12300414: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x12300418: 0x00000028: vertex count +0x1230041c: 0x0000002a: start vertex +0x12300420: 0x00000001: instance count +0x12300424: 0x00000000: start instance +0x12300428: 0x00000000: index bias +0x1230042c: 0x02000000: MI_FLUSH +0x12300430: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300434: 0x00007860: VS state +0x12300438: 0x000077c1: GS state +0x1230043c: 0x00007821: Clip state +0x12300440: 0x00007880: SF state +0x12300444: 0x000078a0: WM state +0x12300448: 0x00007cc0: CC state +0x1230044c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300450: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300454: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300458: 0x60020100: CONSTANT_BUFFER: valid +0x1230045c: 0x00000382: offset: 0x00000380, length: 192 bytes +0x12300460: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300464: 0x0000002a: vertex count +0x12300468: 0x00000052: start vertex +0x1230046c: 0x00000001: instance count +0x12300470: 0x00000000: start instance +0x12300474: 0x00000000: index bias +0x12300478: 0x02000000: MI_FLUSH +0x1230047c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300480: 0x00007860: VS state +0x12300484: 0x000077a1: GS state +0x12300488: 0x00007821: Clip state +0x1230048c: 0x00007880: SF state +0x12300490: 0x000078a0: WM state +0x12300494: 0x00007cc0: CC state +0x12300498: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230049c: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123004a0: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123004a4: 0x60020100: CONSTANT_BUFFER: valid +0x123004a8: 0x00000382: offset: 0x00000380, length: 192 bytes +0x123004ac: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x123004b0: 0x00000028: vertex count +0x123004b4: 0x0000007c: start vertex +0x123004b8: 0x00000001: instance count +0x123004bc: 0x00000000: start instance +0x123004c0: 0x00000000: index bias +0x123004c4: 0x02000000: MI_FLUSH +0x123004c8: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123004cc: 0x00007860: VS state +0x123004d0: 0x00007781: GS state +0x123004d4: 0x00007821: Clip state +0x123004d8: 0x00007880: SF state +0x123004dc: 0x000078a0: WM state +0x123004e0: 0x00007cc0: CC state +0x123004e4: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123004e8: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123004ec: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123004f0: 0x60020100: CONSTANT_BUFFER: valid +0x123004f4: 0x00000382: offset: 0x00000380, length: 192 bytes +0x123004f8: 0x02000000: MI_FLUSH +0x123004fc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300500: 0x00007760: VS state +0x12300504: 0x00007781: GS state +0x12300508: 0x00007821: Clip state +0x1230050c: 0x00007880: SF state +0x12300510: 0x000078a0: WM state +0x12300514: 0x00007cc0: CC state +0x12300518: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230051c: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300520: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300524: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x12300528: 0x00000018: buffer 0: sequential, pitch 24b +0x1230052c: 0x00002a30: buffer address +0x12300530: 0x00007fff: max index +0x12300534: 0x00000000: mbz +0x12300538: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x1230053c: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x12300540: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x12300544: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x12300548: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x1230054c: 0x60020100: CONSTANT_BUFFER: valid +0x12300550: 0x00000442: offset: 0x00000440, length: 192 bytes +0x12300554: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300558: 0x00000052: vertex count +0x1230055c: 0x00000000: start vertex +0x12300560: 0x00000001: instance count +0x12300564: 0x00000000: start instance +0x12300568: 0x00000000: index bias +0x1230056c: 0x02000000: MI_FLUSH +0x12300570: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300574: 0x00007760: VS state +0x12300578: 0x00000000: GS state +0x1230057c: 0x000076c1: Clip state +0x12300580: 0x00007700: SF state +0x12300584: 0x00007720: WM state +0x12300588: 0x00007cc0: CC state +0x1230058c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300590: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300594: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300598: 0x60020100: CONSTANT_BUFFER: valid +0x1230059c: 0x00000442: offset: 0x00000440, length: 192 bytes +0x123005a0: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x123005a4: 0x00000016: vertex count +0x123005a8: 0x00000052: start vertex +0x123005ac: 0x00000001: instance count +0x123005b0: 0x00000000: start instance +0x123005b4: 0x00000000: index bias +0x123005b8: 0x02000000: MI_FLUSH +0x123005bc: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123005c0: 0x00007620: VS state +0x123005c4: 0x000075c1: GS state +0x123005c8: 0x000075e1: Clip state +0x123005cc: 0x00007640: SF state +0x123005d0: 0x00007660: WM state +0x123005d4: 0x00007cc0: CC state +0x123005d8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123005dc: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123005e0: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123005e4: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x123005e8: 0x0000000c: buffer 0: sequential, pitch 12b +0x123005ec: 0x000033f0: buffer address +0x123005f0: 0x00007fff: max index +0x123005f4: 0x00000000: mbz +0x123005f8: 0x78090001: 3DSTATE_VERTEX_ELEMENTS +0x123005fc: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x12300600: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x12300604: 0x60020100: CONSTANT_BUFFER: valid +0x12300608: 0x00000502: offset: 0x00000500, length: 192 bytes +0x1230060c: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x12300610: 0x0000002a: vertex count +0x12300614: 0x00000000: start vertex +0x12300618: 0x00000001: instance count +0x1230061c: 0x00000000: start instance +0x12300620: 0x00000000: index bias +0x12300624: 0x02000000: MI_FLUSH +0x12300628: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x1230062c: 0x00007620: VS state +0x12300630: 0x000075a1: GS state +0x12300634: 0x000075e1: Clip state +0x12300638: 0x00007640: SF state +0x1230063c: 0x00007660: WM state +0x12300640: 0x00007cc0: CC state +0x12300644: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300648: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x1230064c: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300650: 0x60020100: CONSTANT_BUFFER: valid +0x12300654: 0x00000502: offset: 0x00000500, length: 192 bytes +0x12300658: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x1230065c: 0x00000028: vertex count +0x12300660: 0x0000002a: start vertex +0x12300664: 0x00000001: instance count +0x12300668: 0x00000000: start instance +0x1230066c: 0x00000000: index bias +0x12300670: 0x02000000: MI_FLUSH +0x12300674: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300678: 0x00007620: VS state +0x1230067c: 0x00007581: GS state +0x12300680: 0x000075e1: Clip state +0x12300684: 0x00007640: SF state +0x12300688: 0x00007660: WM state +0x1230068c: 0x00007cc0: CC state +0x12300690: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300694: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300698: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x1230069c: 0x60020100: CONSTANT_BUFFER: valid +0x123006a0: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x123006a4: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x123006a8: 0x0000002a: vertex count +0x123006ac: 0x00000052: start vertex +0x123006b0: 0x00000001: instance count +0x123006b4: 0x00000000: start instance +0x123006b8: 0x00000000: index bias +0x123006bc: 0x02000000: MI_FLUSH +0x123006c0: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123006c4: 0x00007620: VS state +0x123006c8: 0x00007561: GS state +0x123006cc: 0x000075e1: Clip state +0x123006d0: 0x00007640: SF state +0x123006d4: 0x00007660: WM state +0x123006d8: 0x00007cc0: CC state +0x123006dc: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123006e0: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123006e4: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123006e8: 0x60020100: CONSTANT_BUFFER: valid +0x123006ec: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x123006f0: 0x7b001c04: 3DPRIMITIVE: quad list sequential +0x123006f4: 0x00000028: vertex count +0x123006f8: 0x0000007c: start vertex +0x123006fc: 0x00000001: instance count +0x12300700: 0x00000000: start instance +0x12300704: 0x00000000: index bias +0x12300708: 0x02000000: MI_FLUSH +0x1230070c: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300710: 0x00007620: VS state +0x12300714: 0x00007541: GS state +0x12300718: 0x000075e1: Clip state +0x1230071c: 0x00007640: SF state +0x12300720: 0x00007660: WM state +0x12300724: 0x00007cc0: CC state +0x12300728: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x1230072c: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300730: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300734: 0x60020100: CONSTANT_BUFFER: valid +0x12300738: 0x000005c2: offset: 0x000005c0, length: 192 bytes +0x1230073c: 0x02000000: MI_FLUSH +0x12300740: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x12300744: 0x00007520: VS state +0x12300748: 0x00007541: GS state +0x1230074c: 0x000075e1: Clip state +0x12300750: 0x00007640: SF state +0x12300754: 0x00007660: WM state +0x12300758: 0x00007cc0: CC state +0x1230075c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x12300760: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x12300764: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x12300768: 0x78080003: 3DSTATE_VERTEX_BUFFERS +0x1230076c: 0x00000018: buffer 0: sequential, pitch 24b +0x12300770: 0x00003bb8: buffer address +0x12300774: 0x00007fff: max index +0x12300778: 0x00000000: mbz +0x1230077c: 0x78090003: 3DSTATE_VERTEX_ELEMENTS +0x12300780: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes +0x12300784: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x12300788: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes +0x1230078c: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes +0x12300790: 0x60020100: CONSTANT_BUFFER: valid +0x12300794: 0x00000682: offset: 0x00000680, length: 192 bytes +0x12300798: 0x7b002004: 3DPRIMITIVE: quad strip sequential +0x1230079c: 0x00000052: vertex count +0x123007a0: 0x00000000: start vertex +0x123007a4: 0x00000001: instance count +0x123007a8: 0x00000000: start instance +0x123007ac: 0x00000000: index bias +0x123007b0: 0x02000000: MI_FLUSH +0x123007b4: 0x78000005: 3DSTATE_PIPELINED_POINTERS +0x123007b8: 0x00007520: VS state +0x123007bc: 0x00000000: GS state +0x123007c0: 0x00007481: Clip state +0x123007c4: 0x000074c0: SF state +0x123007c8: 0x000074e0: WM state +0x123007cc: 0x00007cc0: CC state +0x123007d0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs +0x123007d4: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 +0x123007d8: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 +0x123007dc: 0x60020100: CONSTANT_BUFFER: valid +0x123007e0: 0x00000682: offset: 0x00000680, length: 192 bytes +0x123007e4: 0x7b001404: 3DPRIMITIVE: tri strip sequential +0x123007e8: 0x00000016: vertex count +0x123007ec: 0x00000052: start vertex +0x123007f0: 0x00000001: instance count +0x123007f4: 0x00000000: start instance +0x123007f8: 0x00000000: index bias +0x123007fc: 0x05000000: MI_BATCH_BUFFER_END diff --git a/intel/tests/gen5-3d.batch.sh b/intel/tests/gen5-3d.batch.sh new file mode 120000 index 0000000..796ca5f --- /dev/null +++ b/intel/tests/gen5-3d.batch.sh @@ -0,0 +1 @@ +test-batch.sh \ No newline at end of file diff --git a/intel/tests/gen6-3d.batch b/intel/tests/gen6-3d.batch new file mode 100644 index 0000000..d57147e Binary files /dev/null and b/intel/tests/gen6-3d.batch differ diff --git a/intel/tests/gen6-3d.batch-ref.txt b/intel/tests/gen6-3d.batch-ref.txt new file mode 100644 index 0000000..9499ed1 --- /dev/null +++ b/intel/tests/gen6-3d.batch-ref.txt @@ -0,0 +1,990 @@ +0x12300000: 0x7a000002: PIPE_CONTROL +0x12300004: 0x00100002: no write, cs stall, stall at scoreboard, +0x12300008: 0x00000000: +0x1230000c: 0x00000000: +0x12300010: 0x7a000002: PIPE_CONTROL +0x12300014: 0x00004000: qword write, +0x12300018: 0x00000000: +0x1230001c: 0x00000000: +0x12300020: 0x69040000: 3DSTATE_PIPELINE_SELECT +0x12300024: 0x790d0001: 3DSTATE_MULTISAMPLE +0x12300028: 0x00000000: dword 1 +0x1230002c: 0x00000000: dword 2 +0x12300030: 0x78180000: 3DSTATE_SAMPLE_MASK +0x12300034: 0x00000001: dword 1 +0x12300038: 0x790b0002: 3DSTATE_GS_SVB_INDEX +0x1230003c: 0x00000000: dword 1 +0x12300040: 0x00000000: dword 2 +0x12300044: 0xffffffff: dword 3 +0x12300048: 0x790b0002: 3DSTATE_GS_SVB_INDEX +0x1230004c: 0x20000000: dword 1 +0x12300050: 0x00000000: dword 2 +0x12300054: 0xffffffff: dword 3 +0x12300058: 0x790b0002: 3DSTATE_GS_SVB_INDEX +0x1230005c: 0x40000000: dword 1 +0x12300060: 0x00000000: dword 2 +0x12300064: 0xffffffff: dword 3 +0x12300068: 0x790b0002: 3DSTATE_GS_SVB_INDEX +0x1230006c: 0x60000000: dword 1 +0x12300070: 0x00000000: dword 2 +0x12300074: 0xffffffff: dword 3 +0x12300078: 0x61020000: STATE_SIP +0x1230007c: 0x00000000: dword 1 +0x12300080: 0x680b0000: 3DSTATE_VF_STATISTICS +0x12300084: 0x61010008: STATE_BASE_ADDRESS +0x12300088: 0x00000001: general state base address 0x00000000 +0x1230008c: 0x00000001: surface state base address 0x00000000 +0x12300090: 0x00000001: dynamic state base address 0x00000000 +0x12300094: 0x00000001: indirect state base address 0x00000000 +0x12300098: 0x00000001: instruction state base address 0x00000000 +0x1230009c: 0x00000001: general state upper bound disabled +0x123000a0: 0x00000001: dynamic state upper bound disabled +0x123000a4: 0x00000001: indirect state upper bound disabled +0x123000a8: 0x00000001: instruction state upper bound disabled +0x123000ac: 0x780d1c02: 3DSTATE_VIEWPORT_STATE_POINTERS +0x123000b0: 0x00007fe0: clip +0x123000b4: 0x00007fc0: sf +0x123000b8: 0x00007fa0: cc +0x123000bc: 0x78050001: 3DSTATE_URB +0x123000c0: 0x00000100: VS entries 256, alloc size 1 (1024bit row) +0x123000c4: 0x00000000: GS entries 0, alloc si... [truncated message content] |
From: <gl...@ke...> - 2012-02-02 19:55:18
|
xf86drmMode.c | 21 ++++++++++++++++++--- xf86drmMode.h | 1 + 2 files changed, 19 insertions(+), 3 deletions(-) New commits: commit 76b4a69aab7cbfb4a087194b6d6ee182c1d5dd7e Author: Ville Syrjälä <ville.syrjala at linux.intel.com> Date: Thu Feb 2 14:53:43 2012 -0500 Using sizeof() on a function parameter with an array type does not work. sizeof() treats such parameters as pointers. Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com> diff --git a/xf86drmMode.c b/xf86drmMode.c index 473e734..c809c44 100644 --- a/xf86drmMode.c +++ b/xf86drmMode.c @@ -271,9 +271,9 @@ int drmModeAddFB2(int fd, uint32_t width, uint32_t height, f.height = height; f.pixel_format = pixel_format; f.flags = flags; - memcpy(f.handles, bo_handles, sizeof(bo_handles)); - memcpy(f.pitches, pitches, sizeof(pitches)); - memcpy(f.offsets, offsets, sizeof(offsets)); + memcpy(f.handles, bo_handles, 4 * sizeof(bo_handles[0])); + memcpy(f.pitches, pitches, 4 * sizeof(pitches[0])); + memcpy(f.offsets, offsets, 4 * sizeof(offsets[0])); if ((ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_ADDFB2, &f))) return ret; commit a14c3dd0f9c468d5dba86df5ffa786aea77068a9 Author: Ville Syrjälä <ville.syrjala at linux.intel.com> Date: Thu Feb 2 14:53:41 2012 -0500 This function was missing. Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com> diff --git a/xf86drmMode.c b/xf86drmMode.c index e67ed4a..473e734 100644 --- a/xf86drmMode.c +++ b/xf86drmMode.c @@ -965,3 +965,12 @@ err_allocs: return r; } + +void drmModeFreePlaneResources(drmModePlaneResPtr ptr) +{ + if (!ptr) + return; + + drmFree(ptr->planes); + drmFree(ptr); +} diff --git a/xf86drmMode.h b/xf86drmMode.h index c0fc2ef..34f5fb1 100644 --- a/xf86drmMode.h +++ b/xf86drmMode.h @@ -305,6 +305,7 @@ extern void drmModeFreeCrtc( drmModeCrtcPtr ptr ); extern void drmModeFreeConnector( drmModeConnectorPtr ptr ); extern void drmModeFreeEncoder( drmModeEncoderPtr ptr ); extern void drmModeFreePlane( drmModePlanePtr ptr ); +extern void drmModeFreePlaneResources(drmModePlaneResPtr ptr); /** * Retrives all of the resources associated with a card. commit df497e9281036ca9397bc5a08a82fdf44dbc12b2 Author: Ville Syrjälä <ville.syrjala at linux.intel.com> Date: Thu Feb 2 14:53:39 2012 -0500 drmModeFreeResources() always leaked some memory. drmModeGetPlaneResources() and drmModeGetPlane() leaked in one error path. Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com> diff --git a/xf86drmMode.c b/xf86drmMode.c index da7b462..e67ed4a 100644 --- a/xf86drmMode.c +++ b/xf86drmMode.c @@ -96,6 +96,10 @@ void drmModeFreeResources(drmModeResPtr ptr) if (!ptr) return; + drmFree(ptr->fbs); + drmFree(ptr->crtcs); + drmFree(ptr->connectors); + drmFree(ptr->encoders); drmFree(ptr); } @@ -898,6 +902,7 @@ retry: ovr.count_format_types, sizeof(uint32_t)); if (ovr.count_format_types && !r->formats) { drmFree(r->formats); + drmFree(r); r = 0; } @@ -951,6 +956,7 @@ retry: res.count_planes, sizeof(uint32_t)); if (res.count_planes && !r->planes) { drmFree(r->planes); + drmFree(r); r = 0; } |
From: <an...@ke...> - 2012-03-10 00:34:52
|
intel/Makefile.am | 1 intel/intel_aub.h | 123 +++++++++++++++ intel/intel_bufmgr.h | 17 ++ intel/intel_bufmgr_gem.c | 363 +++++++++++++++++++++++++++++++++++++++++++++-- 4 files changed, 493 insertions(+), 11 deletions(-) New commits: commit c9ce2edfc8d33e760667529250e86e93ff656c3d Author: Eric Anholt <er...@an...> Date: Fri Mar 9 16:08:23 2012 -0800 intel: Bump the copyright dates on the bufmgr files. We've been hacking these constantly. diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h index fa6f2b8..a8062c5 100644 --- a/intel/intel_bufmgr.h +++ b/intel/intel_bufmgr.h @@ -1,5 +1,5 @@ /* - * Copyright © 2008 Intel Corporation + * Copyright © 2008-2012 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index d56593a..e87690d 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -1,7 +1,7 @@ /************************************************************************** * * Copyright © 2007 Red Hat Inc. - * Copyright © 2007 Intel Corporation + * Copyright © 2007-2012 Intel Corporation * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA * All Rights Reserved. * commit 4db16a9480af2c4f36eb8023193cd54545efbe54 Author: Eric Anholt <er...@an...> Date: Tue Oct 11 15:59:03 2011 -0700 intel: Add .aub file output support. This will allow the driver to capture all of its execution state to a file for later debugging. intel_gpu_dump is limited in that it only captures batchbuffers, and Mesa's captures, while more complete, still capture only a portion of the state involved in execution. This is a squash commit of a long series of hacking as we tried to get the resulting traces to work in the internal simulator. It contains contributions by Yuanhan Liu and Kenneth Graunke. v2: Drop the MI_FLUSH_ENABLE setup. Reviewed-by: Kenneth Graunke <ke...@wh...> Signed-off-by: Eric Anholt <er...@an...> Signed-off-by: Yuanhan Liu <yua...@li...> Signed-off-by: Kenneth Graunke <ke...@wh...> diff --git a/intel/Makefile.am b/intel/Makefile.am index 06362b6..dc01a96 100644 --- a/intel/Makefile.am +++ b/intel/Makefile.am @@ -53,6 +53,7 @@ intel_bufmgr_gem_o_CFLAGS = $(AM_CFLAGS) -c99 libdrm_intelincludedir = ${includedir}/libdrm libdrm_intelinclude_HEADERS = intel_bufmgr.h \ + intel_aub.h \ intel_debug.h # This may be interesting even outside of "make check", due to the -dump option. diff --git a/intel/intel_aub.h b/intel/intel_aub.h new file mode 100644 index 0000000..a36fd53 --- /dev/null +++ b/intel/intel_aub.h @@ -0,0 +1,123 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt <er...@an...> + * + */ + +/** @file intel_aub.h + * + * The AUB file is a file format used by Intel's internal simulation + * and other validation tools. It can be used at various levels by a + * driver to input state to the simulated hardware or a replaying + * debugger. + * + * We choose to dump AUB files using the trace block format for ease + * of implementation -- dump out the blocks of memory as plain blobs + * and insert ring commands to execute the batchbuffer blob. + */ + +#ifndef _INTEL_AUB_H +#define _INTEL_AUB_H + +#define AUB_MI_NOOP (0) +#define AUB_MI_BATCH_BUFFER_START (0x31 << 23) +#define AUB_PIPE_CONTROL (0x7a000002) + +/* DW0: instruction type. */ + +#define CMD_AUB (7 << 29) + +#define CMD_AUB_HEADER (CMD_AUB | (1 << 23) | (0x05 << 16)) +/* DW1 */ +# define AUB_HEADER_MAJOR_SHIFT 24 +# define AUB_HEADER_MINOR_SHIFT 16 + +#define CMD_AUB_TRACE_HEADER_BLOCK (CMD_AUB | (1 << 23) | (0x41 << 16)) +#define CMD_AUB_DUMP_BMP (CMD_AUB | (1 << 23) | (0x9e << 16)) + +/* DW1 */ +#define AUB_TRACE_OPERATION_MASK 0x000000ff +#define AUB_TRACE_OP_COMMENT 0x00000000 +#define AUB_TRACE_OP_DATA_WRITE 0x00000001 +#define AUB_TRACE_OP_COMMAND_WRITE 0x00000002 +#define AUB_TRACE_OP_MMIO_WRITE 0x00000003 +// operation = TRACE_DATA_WRITE, Type +#define AUB_TRACE_TYPE_MASK 0x0000ff00 +#define AUB_TRACE_TYPE_NOTYPE (0 << 8) +#define AUB_TRACE_TYPE_BATCH (1 << 8) +#define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8) +#define AUB_TRACE_TYPE_2D_MAP (6 << 8) +#define AUB_TRACE_TYPE_CUBE_MAP (7 << 8) +#define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8) +#define AUB_TRACE_TYPE_1D_MAP (10 << 8) +#define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8) +#define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8) +#define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8) +#define AUB_TRACE_TYPE_GENERAL (14 << 8) +#define AUB_TRACE_TYPE_SURFACE (15 << 8) + + +// operation = TRACE_COMMAND_WRITE, Type = +#define AUB_TRACE_TYPE_RING_HWB (1 << 8) +#define AUB_TRACE_TYPE_RING_PRB0 (2 << 8) +#define AUB_TRACE_TYPE_RING_PRB1 (3 << 8) +#define AUB_TRACE_TYPE_RING_PRB2 (4 << 8) + +// Address space +#define AUB_TRACE_ADDRESS_SPACE_MASK 0x00ff0000 +#define AUB_TRACE_MEMTYPE_GTT (0 << 16) +#define AUB_TRACE_MEMTYPE_LOCAL (1 << 16) +#define AUB_TRACE_MEMTYPE_NONLOCAL (2 << 16) +#define AUB_TRACE_MEMTYPE_PCI (3 << 16) +#define AUB_TRACE_MEMTYPE_GTT_ENTRY (4 << 16) + +/* DW2 */ +// operation = TRACE_DATA_WRITE, Type = TRACE_DATA_WRITE_GENERAL_STATE +#define AUB_TRACE_GENERAL_STATE_MASK 0x000000ff + +#define AUB_TRACE_VS_STATE 0x00000001 +#define AUB_TRACE_GS_STATE 0x00000002 +#define AUB_TRACE_CL_STATE 0x00000003 +#define AUB_TRACE_SF_STATE 0x00000004 +#define AUB_TRACE_WM_STATE 0x00000005 +#define AUB_TRACE_CC_STATE 0x00000006 +#define AUB_TRACE_CL_VP 0x00000007 +#define AUB_TRACE_SF_VP 0x00000008 +#define AUB_TRACE_CC_VP 0x00000009 +#define AUB_TRACE_SAMPLER_STATE 0x0000000a +#define AUB_TRACE_KERNEL 0x0000000b +#define AUB_TRACE_SCRATCH 0x0000000c +#define AUB_TRACE_SDC 0x0000000d +#define AUB_TRACE_BLEND_STATE 0x00000016 +#define AUB_TRACE_DEPTH_STENCIL_STATE 0x00000017 + +// operation = TRACE_DATA_WRITE, Type = TRACE_DATA_WRITE_SURFACE_STATE +#define AUB_TRACE_SURFACE_STATE_MASK 0x00000ff00 +#define AUB_TRACE_BINDING_TABLE 0x000000100 +#define AUB_TRACE_SURFACE_STATE 0x000000200 + +/* DW3: address */ +/* DW4: len */ + +#endif /* _INTEL_AUB_H */ diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h index 8036031..fa6f2b8 100644 --- a/intel/intel_bufmgr.h +++ b/intel/intel_bufmgr.h @@ -36,6 +36,7 @@ #include <stdio.h> #include <stdint.h> +#include <stdio.h> struct drm_clip_rect; @@ -84,6 +85,13 @@ struct _drm_intel_bo { int handle; }; +enum aub_dump_bmp_format { + AUB_DUMP_BMP_FORMAT_8BIT = 1, + AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4, + AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6, + AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7, +}; + #define BO_ALLOC_FOR_RENDER (1<<0) drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name, @@ -154,6 +162,12 @@ int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo); void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start); void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable); +void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable); +void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo, + int x1, int y1, int width, int height, + enum aub_dump_bmp_format format, + int pitch, int offset); + int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id); int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total); diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index ba38e50..d56593a 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -58,6 +58,7 @@ #include "intel_bufmgr.h" #include "intel_bufmgr_priv.h" #include "intel_chipset.h" +#include "intel_aub.h" #include "string.h" #include "i915_drm.h" @@ -121,6 +122,9 @@ typedef struct _drm_intel_bufmgr_gem { unsigned int bo_reuse : 1; unsigned int no_exec : 1; bool fenced_relocs; + + FILE *aub_file; + uint32_t aub_offset; } drm_intel_bufmgr_gem; #define DRM_INTEL_RELOC_FENCE (1<<0) @@ -215,6 +219,8 @@ struct _drm_intel_bo_gem { /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */ bool mapped_cpu_write; + + uint32_t aub_offset; }; static unsigned int @@ -1715,6 +1721,247 @@ drm_intel_update_buffer_offsets2 (drm_intel_bufmgr_gem *bufmgr_gem) } } +static void +aub_out(drm_intel_bufmgr_gem *bufmgr_gem, uint32_t data) +{ + fwrite(&data, 1, 4, bufmgr_gem->aub_file); +} + +static void +aub_out_data(drm_intel_bufmgr_gem *bufmgr_gem, void *data, size_t size) +{ + fwrite(data, 1, size, bufmgr_gem->aub_file); +} + +static void +aub_write_bo_data(drm_intel_bo *bo, uint32_t offset, uint32_t size) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + uint32_t *data; + unsigned int i; + + data = malloc(bo->size); + drm_intel_bo_get_subdata(bo, offset, size, data); + + /* Easy mode: write out bo with no relocations */ + if (!bo_gem->reloc_count) { + aub_out_data(bufmgr_gem, data, size); + free(data); + return; + } + + /* Otherwise, handle the relocations while writing. */ + for (i = 0; i < size / 4; i++) { + int r; + for (r = 0; r < bo_gem->reloc_count; r++) { + struct drm_i915_gem_relocation_entry *reloc; + drm_intel_reloc_target *info; + + reloc = &bo_gem->relocs[r]; + info = &bo_gem->reloc_target_info[r]; + + if (reloc->offset == offset + i * 4) { + drm_intel_bo_gem *target_gem; + uint32_t val; + + target_gem = (drm_intel_bo_gem *)info->bo; + + val = reloc->delta; + val += target_gem->aub_offset; + + aub_out(bufmgr_gem, val); + data[i] = val; + break; + } + } + if (r == bo_gem->reloc_count) { + /* no relocation, just the data */ + aub_out(bufmgr_gem, data[i]); + } + } + + free(data); +} + +static void +aub_bo_get_address(drm_intel_bo *bo) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + /* Give the object a graphics address in the AUB file. We + * don't just use the GEM object address because we do AUB + * dumping before execution -- we want to successfully log + * when the hardware might hang, and we might even want to aub + * capture for a driver trying to execute on a different + * generation of hardware by disabling the actual kernel exec + * call. + */ + bo_gem->aub_offset = bufmgr_gem->aub_offset; + bufmgr_gem->aub_offset += bo->size; + /* XXX: Handle aperture overflow. */ + assert(bufmgr_gem->aub_offset < 256 * 1024 * 1024); +} + +static void +aub_write_trace_block(drm_intel_bo *bo, uint32_t type, uint32_t subtype, + uint32_t offset, uint32_t size) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + aub_out(bufmgr_gem, + CMD_AUB_TRACE_HEADER_BLOCK | + (5 - 2)); + aub_out(bufmgr_gem, + AUB_TRACE_MEMTYPE_GTT | type | AUB_TRACE_OP_DATA_WRITE); + aub_out(bufmgr_gem, subtype); + aub_out(bufmgr_gem, bo_gem->aub_offset + offset); + aub_out(bufmgr_gem, size); + aub_write_bo_data(bo, offset, size); +} + +static void +aub_write_bo(drm_intel_bo *bo) +{ + uint32_t block_size; + uint32_t offset; + + aub_bo_get_address(bo); + + /* Break up large objects into multiple writes. Otherwise a + * 128kb VBO would overflow the 16 bits of size field in the + * packet header and everything goes badly after that. + */ + for (offset = 0; offset < bo->size; offset += block_size) { + block_size = bo->size - offset; + + if (block_size > 8 * 4096) + block_size = 8 * 4096; + + aub_write_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0, + offset, block_size); + } +} + +/* + * Make a ringbuffer on fly and dump it + */ +static void +aub_build_dump_ringbuffer(drm_intel_bufmgr_gem *bufmgr_gem, + uint32_t batch_buffer, int ring_flag) +{ + uint32_t ringbuffer[4096]; + int ring = AUB_TRACE_TYPE_RING_PRB0; /* The default ring */ + int ring_count = 0; + + if (ring_flag == I915_EXEC_BSD) + ring = AUB_TRACE_TYPE_RING_PRB1; + + /* Make a ring buffer to execute our batchbuffer. */ + memset(ringbuffer, 0, sizeof(ringbuffer)); + ringbuffer[ring_count++] = AUB_MI_BATCH_BUFFER_START; + ringbuffer[ring_count++] = batch_buffer; + + /* Write out the ring. This appears to trigger execution of + * the ring in the simulator. + */ + aub_out(bufmgr_gem, + CMD_AUB_TRACE_HEADER_BLOCK | + (5 - 2)); + aub_out(bufmgr_gem, + AUB_TRACE_MEMTYPE_GTT | ring | AUB_TRACE_OP_COMMAND_WRITE); + aub_out(bufmgr_gem, 0); /* general/surface subtype */ + aub_out(bufmgr_gem, bufmgr_gem->aub_offset); + aub_out(bufmgr_gem, ring_count * 4); + + /* FIXME: Need some flush operations here? */ + aub_out_data(bufmgr_gem, ringbuffer, ring_count * 4); + + /* Update offset pointer */ + bufmgr_gem->aub_offset += 4096; +} + +void +drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo, + int x1, int y1, int width, int height, + enum aub_dump_bmp_format format, + int pitch, int offset) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo; + uint32_t cpp; + + switch (format) { + case AUB_DUMP_BMP_FORMAT_8BIT: + cpp = 1; + break; + case AUB_DUMP_BMP_FORMAT_ARGB_4444: + cpp = 2; + break; + case AUB_DUMP_BMP_FORMAT_ARGB_0888: + case AUB_DUMP_BMP_FORMAT_ARGB_8888: + cpp = 4; + break; + default: + printf("Unknown AUB dump format %d\n", format); + return; + } + + if (!bufmgr_gem->aub_file) + return; + + aub_out(bufmgr_gem, CMD_AUB_DUMP_BMP | 4); + aub_out(bufmgr_gem, (y1 << 16) | x1); + aub_out(bufmgr_gem, + (format << 24) | + (cpp << 19) | + pitch / 4); + aub_out(bufmgr_gem, (height << 16) | width); + aub_out(bufmgr_gem, bo_gem->aub_offset + offset); + aub_out(bufmgr_gem, + ((bo_gem->tiling_mode != I915_TILING_NONE) ? (1 << 2) : 0) | + ((bo_gem->tiling_mode == I915_TILING_Y) ? (1 << 3) : 0)); +} + +static void +aub_exec(drm_intel_bo *bo, int ring_flag, int used) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + int i; + + if (!bufmgr_gem->aub_file) + return; + + /* Write out all but the batchbuffer to AUB memory */ + for (i = 0; i < bufmgr_gem->exec_count - 1; i++) { + if (bufmgr_gem->exec_bos[i] != bo) + aub_write_bo(bufmgr_gem->exec_bos[i]); + } + + aub_bo_get_address(bo); + + /* Dump the batchbuffer. */ + aub_write_trace_block(bo, AUB_TRACE_TYPE_BATCH, 0, + 0, used); + aub_write_trace_block(bo, AUB_TRACE_TYPE_NOTYPE, 0, + used, bo->size - used); + + /* Dump ring buffer */ + aub_build_dump_ringbuffer(bufmgr_gem, bo_gem->aub_offset, ring_flag); + + fflush(bufmgr_gem->aub_file); + + /* + * One frame has been dumped. So reset the aub_offset for the next frame. + * + * FIXME: Can we do this? + */ + bufmgr_gem->aub_offset = 0x10000; +} + static int drm_intel_gem_bo_exec(drm_intel_bo *bo, int used, drm_clip_rect_t * cliprects, int num_cliprects, int DR4) @@ -1830,6 +2077,8 @@ drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used, execbuf.rsvd1 = 0; execbuf.rsvd2 = 0; + aub_exec(bo, flags, used); + if (bufmgr_gem->no_exec) goto skip_execution; @@ -2360,6 +2609,62 @@ drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr) } /** + * Sets up AUB dumping. + * + * This is a trace file format that can be used with the simulator. + * Packets are emitted in a format somewhat like GPU command packets. + * You can set up a GTT and upload your objects into the referenced + * space, then send off batchbuffers and get BMPs out the other end. + */ +void +drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; + int entry = 0x200003; + int i; + int gtt_size = 0x10000; + + if (!enable) { + if (bufmgr_gem->aub_file) { + fclose(bufmgr_gem->aub_file); + bufmgr_gem->aub_file = NULL; + } + } + + if (geteuid() != getuid()) + return; + + bufmgr_gem->aub_file = fopen("intel.aub", "w+"); + if (!bufmgr_gem->aub_file) + return; + + /* Start allocating objects from just after the GTT. */ + bufmgr_gem->aub_offset = gtt_size; + + /* Start with a (required) version packet. */ + aub_out(bufmgr_gem, CMD_AUB_HEADER | (13 - 2)); + aub_out(bufmgr_gem, + (4 << AUB_HEADER_MAJOR_SHIFT) | + (0 << AUB_HEADER_MINOR_SHIFT)); + for (i = 0; i < 8; i++) { + aub_out(bufmgr_gem, 0); /* app name */ + } + aub_out(bufmgr_gem, 0); /* timestamp */ + aub_out(bufmgr_gem, 0); /* timestamp */ + aub_out(bufmgr_gem, 0); /* comment len */ + + /* Set up the GTT. The max we can handle is 256M */ + aub_out(bufmgr_gem, CMD_AUB_TRACE_HEADER_BLOCK | (5 - 2)); + aub_out(bufmgr_gem, AUB_TRACE_MEMTYPE_NONLOCAL | 0 | AUB_TRACE_OP_DATA_WRITE); + aub_out(bufmgr_gem, 0); /* subtype */ + aub_out(bufmgr_gem, 0); /* offset */ + aub_out(bufmgr_gem, gtt_size); /* size */ + for (i = 0x000; i < gtt_size; i += 4, entry += 0x1000) { + aub_out(bufmgr_gem, entry); + } +} + +/** * Initializes the GEM buffer manager, which uses the kernel to allocate, map, * and manage map buffer objections. * commit 6e642db7f4a5628ed63ca3c479f06bd6f2ca3893 Author: Kenneth Graunke <ke...@wh...> Date: Tue Oct 11 14:38:34 2011 -0700 intel: Add support for overriding the PCI ID via an environment variable For example: export INTEL_DEVID_OVERRIDE=0x162 If this variable is set, don't actually submit the batchbuffer to the GPU, it probably contains commands for the wrong generation of hardware. v2: Introduce a getter for the overridden devid, and avoid getenv per exec. Reviewed-by: Yuanhan Liu <yua...@li...> Signed-off-by: Kenneth Graunke <ke...@wh...> Signed-off-by: Eric Anholt <er...@an...> diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h index 85da8b9..8036031 100644 --- a/intel/intel_bufmgr.h +++ b/intel/intel_bufmgr.h @@ -157,6 +157,7 @@ void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable); int drm_intel_get_pipe_from_crtc_id(drm_intel_bufmgr *bufmgr, int crtc_id); int drm_intel_get_aperture_sizes(int fd, size_t *mappable, size_t *total); +int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr); /* drm_intel_bufmgr_fake.c */ drm_intel_bufmgr *drm_intel_bufmgr_fake_init(int fd, diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 0f33b71..ba38e50 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -119,6 +119,7 @@ typedef struct _drm_intel_bufmgr_gem { unsigned int has_relaxed_fencing : 1; unsigned int has_llc : 1; unsigned int bo_reuse : 1; + unsigned int no_exec : 1; bool fenced_relocs; } drm_intel_bufmgr_gem; @@ -1788,7 +1789,8 @@ drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used, { drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr; struct drm_i915_gem_execbuffer2 execbuf; - int ret, i; + int ret = 0; + int i; switch (flags & 0x7) { default: @@ -1828,6 +1830,9 @@ drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used, execbuf.rsvd1 = 0; execbuf.rsvd2 = 0; + if (bufmgr_gem->no_exec) + goto skip_execution; + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf); @@ -1845,6 +1850,7 @@ drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used, } drm_intel_update_buffer_offsets2(bufmgr_gem); +skip_execution: if (bufmgr_gem->bufmgr.debug) drm_intel_gem_dump_validation_list(bufmgr_gem); @@ -2315,6 +2321,45 @@ drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr, int limit) } /** + * Get the PCI ID for the device. This can be overridden by setting the + * INTEL_DEVID_OVERRIDE environment variable to the desired ID. + */ +static int +get_pci_device_id(drm_intel_bufmgr_gem *bufmgr_gem) +{ + char *devid_override; + int devid; + int ret; + drm_i915_getparam_t gp; + + if (geteuid() == getuid()) { + devid_override = getenv("INTEL_DEVID_OVERRIDE"); + if (devid_override) { + bufmgr_gem->no_exec = true; + return strtod(devid_override, NULL); + } + } + + VG_CLEAR(gp); + gp.param = I915_PARAM_CHIPSET_ID; + gp.value = &devid; + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); + if (ret) { + fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno); + fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value); + } + return devid; +} + +int +drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; + + return bufmgr_gem->pci_device; +} + +/** * Initializes the GEM buffer manager, which uses the kernel to allocate, map, * and manage map buffer objections. * @@ -2356,14 +2401,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) (int)bufmgr_gem->gtt_size / 1024); } - VG_CLEAR(gp); - gp.param = I915_PARAM_CHIPSET_ID; - gp.value = &bufmgr_gem->pci_device; - ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp); - if (ret) { - fprintf(stderr, "get chip id failed: %d [%d]\n", ret, errno); - fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value); - } + bufmgr_gem->pci_device = get_pci_device_id(bufmgr_gem); if (IS_GEN2(bufmgr_gem->pci_device)) bufmgr_gem->gen = 2; |
From: <rob...@ke...> - 2012-04-11 14:58:40
|
include/drm/drm.h | 14 ++++++++++++++ omap/omap_drm.c | 21 +++++++++++++++++++++ omap/omap_drmif.h | 1 + tests/modetest/modetest.c | 2 +- 4 files changed, 37 insertions(+), 1 deletion(-) New commits: commit f00efc7ab442f106d3ac7699e80f1f7aee8451f4 Author: Rob Clark <ro...@ti...> Date: Wed Apr 11 09:51:36 2012 -0500 omap: add dmabuf support Signed-off-by: Rob Clark <ro...@ti...> diff --git a/omap/omap_drm.c b/omap/omap_drm.c index 96e1871..336da11 100644 --- a/omap/omap_drm.c +++ b/omap/omap_drm.c @@ -34,6 +34,7 @@ #include <linux/stddef.h> #include <errno.h> #include <sys/mman.h> +#include <fcntl.h> #include <xf86drm.h> @@ -56,6 +57,7 @@ struct omap_bo { uint32_t handle; uint32_t name; /* flink global handle (DRI2 name) */ uint64_t offset; /* offset to mmap() */ + int fd; /* dmabuf handle */ }; struct omap_device * omap_device_new(int fd) @@ -264,6 +266,25 @@ uint32_t omap_bo_handle(struct omap_bo *bo) return bo->handle; } +int omap_bo_dmabuf(struct omap_bo *bo) +{ + if (!bo->fd) { + struct drm_prime_handle req = { + .handle = bo->handle, + .flags = DRM_CLOEXEC, + }; + int ret; + + ret = drmIoctl(bo->dev->fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &req); + if (ret) { + return ret; + } + + bo->fd = req.fd; + } + return bo->fd; +} + uint32_t omap_bo_size(struct omap_bo *bo) { if (!bo->size) { diff --git a/omap/omap_drmif.h b/omap/omap_drmif.h index eb75a80..1e03eee 100644 --- a/omap/omap_drmif.h +++ b/omap/omap_drmif.h @@ -53,6 +53,7 @@ struct omap_bo * omap_bo_from_name(struct omap_device *dev, uint32_t name); void omap_bo_del(struct omap_bo *bo); int omap_bo_get_name(struct omap_bo *bo, uint32_t *name); uint32_t omap_bo_handle(struct omap_bo *bo); +int omap_bo_dmabuf(struct omap_bo *bo); uint32_t omap_bo_size(struct omap_bo *bo); void * omap_bo_map(struct omap_bo *bo); int omap_bo_cpu_prep(struct omap_bo *bo, enum omap_gem_op op); commit 9b893e4a429d58bf0954ffc09b18890fcfe92941 Author: Rob Clark <ro...@ti...> Date: Wed Apr 11 09:44:35 2012 -0500 libdrm: update drm headers from kernel for prime/dmabuf Sync drm.h with from kernel headers for the new PRIME_HANDLE_TO_FD and PRIME_FD_TO_HANDLE ioctls from Dave Airlie's "drm: base prime/ dma-buf support (v5)" kernel patch. Signed-off-by: Rob Clark <ro...@ti...> diff --git a/include/drm/drm.h b/include/drm/drm.h index 8adb9d5..753d2fc 100644 --- a/include/drm/drm.h +++ b/include/drm/drm.h @@ -618,6 +618,17 @@ struct drm_get_cap { __u64 value; }; +#define DRM_CLOEXEC O_CLOEXEC +struct drm_prime_handle { + __u32 handle; + + /** Flags.. only applicable for handle->fd */ + __u32 flags; + + /** Returned dmabuf file descriptor */ + __s32 fd; +}; + #include "drm_mode.h" #define DRM_IOCTL_BASE 'd' @@ -686,6 +697,9 @@ struct drm_get_cap { #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) +#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) +#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) + #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) commit 67fd052c013a493cd644d2e3495fab8b5823b330 Author: Rob Clark <ro...@ti...> Date: Tue Apr 10 10:23:50 2012 -0500 modetest: fix typo Reported-by: Ville Syrjälä <vil...@li...> Signed-off-by: Rob Clark <ro...@ti...> diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c index 819724a..223adc4 100644 --- a/tests/modetest/modetest.c +++ b/tests/modetest/modetest.c @@ -770,7 +770,7 @@ set_plane(struct kms_driver *kms, struct connector *c, struct plane *p) kms_bo_get_prop(plane_bo, KMS_HANDLE, &handles[1]); pitches[2] = p->w / 2; offsets[2] = offsets[1] + (p->w * p->h) / 4; - kms_bo_get_prop(plane_bo, KMS_HANDLE, &handles[1]); + kms_bo_get_prop(plane_bo, KMS_HANDLE, &handles[2]); fill420(virtual, virtual+offsets[1], virtual+offsets[2], 1, 0, p->w, p->h, pitches[0]); |
From: <rob...@ke...> - 2012-07-13 21:19:44
|
configure.ac | 2 omap/omap_drm.c | 176 ++++++++++++++++++++++++++++++++++++++++++++++++------ omap/omap_drmif.h | 3 3 files changed, 161 insertions(+), 20 deletions(-) New commits: commit 22574aa887efa879519328acc09cb01d03374bf4 Author: Rob Clark <ro...@ti...> Date: Fri Jul 13 16:18:25 2012 -0500 omap: add refcnting and handle tracking There can be scenarios, especially when re-importing an existing buffer, where you end up with multiple 'struct omap_bo's wrapping a single GEM object handle. Which causes badness when the first of the evil-clones is omap_bo_del()'d. To do this, introduce reference counting and a hashtable to track the handles per fd. First, to avoid bo's slipping through the crack if multiple 'struct omap_device's are created for one drm fd, a hashtable mapping drm fd to omap_device, and the omap_device itself is reference counted. Per omap_device, we keep a handle_table mapping GEM handle to omap_bo. When buffers are imported from flink name or dmabuf fd, the handle table is consulted, and if an omap_bo already exists, it's refcnt is incremented and it is returned. For good measure, to avoid the handle_table being deleted before the omap_bo is freed, the omap_bo holds a reference to the omap_device. TODO: check the overhead of the hashtable. If too much we could maybe get away with only tracking exported and imported bo's in the table. TODO: all the import/export flink/dmabuf operations are generic DRM ioctls. Really all this functionality could be handled by a generic drm_bo and drm_device "base class" that could be extended by omap, exynos, etc. That would also allow more common userspace code by avoiding artificial libdrm_omap dependencies. Signed-off-by: Rob Clark <ro...@ti...> diff --git a/configure.ac b/configure.ac index a1c8c69..09fed53 100644 --- a/configure.ac +++ b/configure.ac @@ -214,7 +214,7 @@ if test "x$HAVE_LIBUDEV" = xyes; then fi AM_CONDITIONAL(HAVE_LIBUDEV, [test "x$HAVE_LIBUDEV" = xyes]) -if test "x$INTEL" != "xno" -o "x$RADEON" != "xno" -o "x$NOUVEAU" != "xno"; then +if test "x$INTEL" != "xno" -o "x$RADEON" != "xno" -o "x$NOUVEAU" != "xno" -o "x$OMAP" != "xno"; then # Check for atomic intrinsics AC_CACHE_CHECK([for native atomic primitives], drm_cv_atomic_primitives, [ diff --git a/omap/omap_drm.c b/omap/omap_drm.c index 1d37e45..cd8e8bc 100644 --- a/omap/omap_drm.c +++ b/omap/omap_drm.c @@ -32,12 +32,15 @@ #include <stdlib.h> #include <linux/stddef.h> +#include <linux/types.h> #include <errno.h> #include <sys/mman.h> #include <fcntl.h> #include <unistd.h> +#include <pthread.h> #include <xf86drm.h> +#include <xf86atomic.h> #include "omap_drm.h" #include "omap_drmif.h" @@ -46,8 +49,23 @@ #define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1) #define PAGE_SIZE 4096 +static pthread_mutex_t table_lock = PTHREAD_MUTEX_INITIALIZER; +static void * dev_table; + struct omap_device { int fd; + atomic_t refcnt; + + /* The handle_table is used to track GEM bo handles associated w/ + * this fd. This is needed, in particular, when importing + * dmabuf's because we don't want multiple 'struct omap_bo's + * floating around with the same handle. Otherwise, when the + * first one is omap_bo_del()'d the handle becomes no longer + * valid, and the remaining 'struct omap_bo's are left pointing + * to an invalid handle (and possible a GEM bo that is already + * free'd). + */ + void *handle_table; }; /* a GEM buffer object allocated from the DRM device */ @@ -59,19 +77,57 @@ struct omap_bo { uint32_t name; /* flink global handle (DRI2 name) */ uint64_t offset; /* offset to mmap() */ int fd; /* dmabuf handle */ + atomic_t refcnt; }; -struct omap_device * omap_device_new(int fd) +static struct omap_device * omap_device_new_impl(int fd) { struct omap_device *dev = calloc(sizeof(*dev), 1); if (!dev) return NULL; dev->fd = fd; + atomic_set(&dev->refcnt, 1); + dev->handle_table = drmHashCreate(); + return dev; +} + +struct omap_device * omap_device_new(int fd) +{ + struct omap_device *dev = NULL; + + pthread_mutex_lock(&table_lock); + + if (!dev_table) + dev_table = drmHashCreate(); + + if (drmHashLookup(dev_table, fd, (void **)&dev)) { + /* not found, create new device */ + dev = omap_device_new_impl(fd); + drmHashInsert(dev_table, fd, dev); + } else { + /* found, just incr refcnt */ + dev = omap_device_ref(dev); + } + + pthread_mutex_unlock(&table_lock); + + return dev; +} + +struct omap_device * omap_device_ref(struct omap_device *dev) +{ + atomic_inc(&dev->refcnt); return dev; } void omap_device_del(struct omap_device *dev) { + if (!atomic_dec_and_test(&dev->refcnt)) + return; + pthread_mutex_lock(&table_lock); + drmHashDestroy(dev->handle_table); + drmHashDelete(dev_table, dev->fd); + pthread_mutex_unlock(&table_lock); free(dev); } @@ -101,6 +157,38 @@ int omap_set_param(struct omap_device *dev, uint64_t param, uint64_t value) return drmCommandWrite(dev->fd, DRM_OMAP_SET_PARAM, &req, sizeof(req)); } +/* lookup a buffer from it's handle, call w/ table_lock held: */ +static struct omap_bo * lookup_bo(struct omap_device *dev, + uint32_t handle) +{ + struct omap_bo *bo = NULL; + if (!drmHashLookup(dev->handle_table, handle, (void **)&bo)) { + /* found, incr refcnt and return: */ + bo = omap_bo_ref(bo); + } + return bo; +} + +/* allocate a new buffer object, call w/ table_lock held */ +static struct omap_bo * bo_from_handle(struct omap_device *dev, + uint32_t handle) +{ + struct omap_bo *bo = calloc(sizeof(*bo), 1); + if (!bo) { + struct drm_gem_close req = { + .handle = handle, + }; + drmIoctl(dev->fd, DRM_IOCTL_GEM_CLOSE, &req); + return NULL; + } + bo->dev = omap_device_ref(dev); + bo->handle = handle; + atomic_set(&bo->refcnt, 1); + /* add ourselves to the handle table: */ + drmHashInsert(dev->handle_table, handle, bo); + return bo; +} + /* allocate a new buffer object */ static struct omap_bo * omap_bo_new_impl(struct omap_device *dev, union omap_gem_size size, uint32_t flags) @@ -115,12 +203,13 @@ static struct omap_bo * omap_bo_new_impl(struct omap_device *dev, goto fail; } - bo = calloc(sizeof(*bo), 1); - if (!bo) { + if (drmCommandWriteRead(dev->fd, DRM_OMAP_GEM_NEW, &req, sizeof(req))) { goto fail; } - bo->dev = dev; + pthread_mutex_lock(&table_lock); + bo = bo_from_handle(dev, req.handle); + pthread_mutex_unlock(&table_lock); if (flags & OMAP_BO_TILED) { bo->size = round_up(size.tiled.width, PAGE_SIZE) * size.tiled.height; @@ -128,12 +217,6 @@ static struct omap_bo * omap_bo_new_impl(struct omap_device *dev, bo->size = size.bytes; } - if (drmCommandWriteRead(dev->fd, DRM_OMAP_GEM_NEW, &req, sizeof(req))) { - goto fail; - } - - bo->handle = req.handle; - return bo; fail: @@ -171,6 +254,12 @@ struct omap_bo * omap_bo_new_tiled(struct omap_device *dev, return omap_bo_new_impl(dev, gsize, flags); } +struct omap_bo * omap_bo_ref(struct omap_bo *bo) +{ + atomic_inc(&bo->refcnt); + return bo; +} + /* get buffer info */ static int get_buffer_info(struct omap_bo *bo) { @@ -193,23 +282,24 @@ static int get_buffer_info(struct omap_bo *bo) /* import a buffer object from DRI2 name */ struct omap_bo * omap_bo_from_name(struct omap_device *dev, uint32_t name) { - struct omap_bo *bo; + struct omap_bo *bo = NULL; struct drm_gem_open req = { .name = name, }; - bo = calloc(sizeof(*bo), 1); - if (!bo) { - goto fail; - } + pthread_mutex_lock(&table_lock); if (drmIoctl(dev->fd, DRM_IOCTL_GEM_OPEN, &req)) { goto fail; } - bo->dev = dev; - bo->name = name; - bo->handle = req.handle; + bo = lookup_bo(dev, req.handle); + if (!bo) { + bo = bo_from_handle(dev, req.handle); + bo->name = name; + } + + pthread_mutex_unlock(&table_lock); return bo; @@ -224,24 +314,25 @@ fail: */ struct omap_bo * omap_bo_from_dmabuf(struct omap_device *dev, int fd) { - struct omap_bo *bo; + struct omap_bo *bo = NULL; struct drm_prime_handle req = { .fd = fd, }; int ret; - bo = calloc(sizeof(*bo), 1); - if (!bo) { - goto fail; - } + pthread_mutex_lock(&table_lock); ret = drmIoctl(dev->fd, DRM_IOCTL_PRIME_FD_TO_HANDLE, &req); if (ret) { goto fail; } - bo->dev = dev; - bo->handle = req.handle; + bo = lookup_bo(dev, req.handle); + if (!bo) { + bo = bo_from_handle(dev, req.handle); + } + + pthread_mutex_unlock(&table_lock); return bo; @@ -257,6 +348,9 @@ void omap_bo_del(struct omap_bo *bo) return; } + if (!atomic_dec_and_test(&bo->refcnt)) + return; + if (bo->map) { munmap(bo->map, bo->size); } @@ -269,10 +363,14 @@ void omap_bo_del(struct omap_bo *bo) struct drm_gem_close req = { .handle = bo->handle, }; - + pthread_mutex_lock(&table_lock); + drmHashDelete(bo->dev->handle_table, bo->handle); drmIoctl(bo->dev->fd, DRM_IOCTL_GEM_CLOSE, &req); + pthread_mutex_unlock(&table_lock); } + omap_device_del(bo->dev); + free(bo); } diff --git a/omap/omap_drmif.h b/omap/omap_drmif.h index 284b9cc..e62d127 100644 --- a/omap/omap_drmif.h +++ b/omap/omap_drmif.h @@ -38,6 +38,7 @@ struct omap_device; */ struct omap_device * omap_device_new(int fd); +struct omap_device * omap_device_ref(struct omap_device *dev); void omap_device_del(struct omap_device *dev); int omap_get_param(struct omap_device *dev, uint64_t param, uint64_t *value); int omap_set_param(struct omap_device *dev, uint64_t param, uint64_t value); @@ -49,6 +50,7 @@ struct omap_bo * omap_bo_new(struct omap_device *dev, uint32_t size, uint32_t flags); struct omap_bo * omap_bo_new_tiled(struct omap_device *dev, uint32_t width, uint32_t height, uint32_t flags); +struct omap_bo * omap_bo_ref(struct omap_bo *bo); struct omap_bo * omap_bo_from_name(struct omap_device *dev, uint32_t name); struct omap_bo * omap_bo_from_dmabuf(struct omap_device *dev, int fd); void omap_bo_del(struct omap_bo *bo); commit 42f8a68e19ba48a25f5eca2778d997f3d1ad094d Author: Rob Clark <ro...@ti...> Date: Mon Jun 11 17:17:17 2012 -0500 omap: add API to import bo's from dmabuf fd's Signed-off-by: Rob Clark <ro...@ti...> diff --git a/omap/omap_drm.c b/omap/omap_drm.c index 464dea9..1d37e45 100644 --- a/omap/omap_drm.c +++ b/omap/omap_drm.c @@ -218,6 +218,38 @@ fail: return NULL; } +/* import a buffer from dmabuf fd, does not take ownership of the + * fd so caller should close() the fd when it is otherwise done + * with it (even if it is still using the 'struct omap_bo *') + */ +struct omap_bo * omap_bo_from_dmabuf(struct omap_device *dev, int fd) +{ + struct omap_bo *bo; + struct drm_prime_handle req = { + .fd = fd, + }; + int ret; + + bo = calloc(sizeof(*bo), 1); + if (!bo) { + goto fail; + } + + ret = drmIoctl(dev->fd, DRM_IOCTL_PRIME_FD_TO_HANDLE, &req); + if (ret) { + goto fail; + } + + bo->dev = dev; + bo->handle = req.handle; + + return bo; + +fail: + free(bo); + return NULL; +} + /* destroy a buffer object */ void omap_bo_del(struct omap_bo *bo) { diff --git a/omap/omap_drmif.h b/omap/omap_drmif.h index 1e03eee..284b9cc 100644 --- a/omap/omap_drmif.h +++ b/omap/omap_drmif.h @@ -50,6 +50,7 @@ struct omap_bo * omap_bo_new(struct omap_device *dev, struct omap_bo * omap_bo_new_tiled(struct omap_device *dev, uint32_t width, uint32_t height, uint32_t flags); struct omap_bo * omap_bo_from_name(struct omap_device *dev, uint32_t name); +struct omap_bo * omap_bo_from_dmabuf(struct omap_device *dev, int fd); void omap_bo_del(struct omap_bo *bo); int omap_bo_get_name(struct omap_bo *bo, uint32_t *name); uint32_t omap_bo_handle(struct omap_bo *bo); commit 8116a32df613df4433aa1b128c58bf2c18479824 Author: Rob Clark <ro...@ti...> Date: Mon Jun 11 08:52:24 2012 -0500 omap: clarify dmabuf file descriptor ownership Signed-off-by: Rob Clark <ro...@ti...> diff --git a/omap/omap_drm.c b/omap/omap_drm.c index 336da11..464dea9 100644 --- a/omap/omap_drm.c +++ b/omap/omap_drm.c @@ -35,6 +35,7 @@ #include <errno.h> #include <sys/mman.h> #include <fcntl.h> +#include <unistd.h> #include <xf86drm.h> @@ -228,6 +229,10 @@ void omap_bo_del(struct omap_bo *bo) munmap(bo->map, bo->size); } + if (bo->fd) { + close(bo->fd); + } + if (bo->handle) { struct drm_gem_close req = { .handle = bo->handle, @@ -266,6 +271,9 @@ uint32_t omap_bo_handle(struct omap_bo *bo) return bo->handle; } +/* caller owns the dmabuf fd that is returned and is responsible + * to close() it when done + */ int omap_bo_dmabuf(struct omap_bo *bo) { if (!bo->fd) { @@ -282,7 +290,7 @@ int omap_bo_dmabuf(struct omap_bo *bo) bo->fd = req.fd; } - return bo->fd; + return dup(bo->fd); } uint32_t omap_bo_size(struct omap_bo *bo) |
From: <an...@ke...> - 2012-08-10 16:49:40
|
configure.ac | 2 +- include/drm/i915_drm.h | 33 ++++++++++++++++++++++++++++++++- intel/intel_bufmgr.h | 3 +++ intel/intel_bufmgr_gem.c | 18 ++++++++++++++++++ 4 files changed, 54 insertions(+), 2 deletions(-) New commits: commit 2607dad20b8dffce96608103def75d26ea0e42b2 Author: Eric Anholt <er...@an...> Date: Wed Aug 1 16:43:16 2012 -0700 intel: Add a function for the new register read ioctl. Reviewed-by: Ben Widawsky <be...@bw...> diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h index 2167e43..8d7f239 100644 --- a/intel/intel_bufmgr.h +++ b/intel/intel_bufmgr.h @@ -241,6 +241,9 @@ void drm_intel_decode_set_head_tail(struct drm_intel_decode *ctx, void drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out); void drm_intel_decode(struct drm_intel_decode *ctx); +int drm_intel_reg_read(drm_intel_bufmgr *bufmgr, + uint32_t offset, + uint64_t *result); /** @{ Compatibility defines to keep old code building despite the symbol rename * from dri_* to drm_intel_* diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index ec64e0a..0ea6260 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -2947,6 +2947,24 @@ drm_intel_gem_context_destroy(drm_intel_context *ctx) free(ctx); } +int +drm_intel_reg_read(drm_intel_bufmgr *bufmgr, + uint32_t offset, + uint64_t *result) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; + struct drm_i915_reg_read reg_read; + int ret; + + VG_CLEAR(reg_read); + reg_read.offset = offset; + + ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read); + + *result = reg_read.val; + return ret; +} + /** * Annotate the given bo for use in aub dumping. commit 934ea3b32127ea2a4ba5bf14228af6c60d3437b6 Author: Eric Anholt <er...@an...> Date: Wed Aug 1 16:38:19 2012 -0700 intel: Import updated i915_drm.h. Reviewed-by: Ben Widawsky <be...@bw...> diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h index 5c8fabe..7e9e9bd 100644 --- a/include/drm/i915_drm.h +++ b/include/drm/i915_drm.h @@ -195,6 +195,9 @@ typedef struct _drm_i915_sarea { #define DRM_I915_GEM_WAIT 0x2c #define DRM_I915_GEM_CONTEXT_CREATE 0x2d #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e +#define DRM_I915_GEM_SET_CACHEING 0x2f +#define DRM_I915_GEM_GET_CACHEING 0x30 +#define DRM_I915_REG_READ 0x31 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) @@ -219,6 +222,8 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) +#define DRM_IOCTL_I915_GEM_SET_CACHEING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct drm_i915_gem_cacheing) +#define DRM_IOCTL_I915_GEM_GET_CACHEING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct drm_i915_gem_cacheing) #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) @@ -241,6 +246,7 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) +#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. @@ -690,10 +696,31 @@ struct drm_i915_gem_busy { /** Handle of the buffer to check for busy */ __u32 handle; - /** Return busy status (1 if busy, 0 if idle) */ + /** Return busy status (1 if busy, 0 if idle). + * The high word is used to indicate on which rings the object + * currently resides: + * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc) + */ __u32 busy; }; +#define I915_CACHEING_NONE 0 +#define I915_CACHEING_CACHED 1 + +struct drm_i915_gem_cacheing { + /** + * Handle of the buffer to set/get the cacheing level of. */ + __u32 handle; + + /** + * Cacheing level to apply or return value + * + * bits0-15 are for generic cacheing control (i.e. the above defined + * values). bits16-31 are reserved for platform-specific variations + * (e.g. l3$ caching on gen7). */ + __u32 cacheing; +}; + #define I915_TILING_NONE 0 #define I915_TILING_X 1 #define I915_TILING_Y 2 @@ -910,4 +937,8 @@ struct drm_i915_gem_context_destroy { __u32 pad; }; +struct drm_i915_reg_read { + __u64 offset; + __u64 val; /* Return value */ +}; #endif /* _I915_DRM_H_ */ commit 71ebcf4ea372927ba8af425a229c4fa75dc45dd1 Author: Eric Anholt <er...@an...> Date: Thu Aug 2 11:25:57 2012 -0700 Drop "-Wunsafe-loop-optimizations". It warns about totally sensible things done in intel_decode.c. I've never seen this warn do anything useful, and apparently I was the one to introduce it when I added the giant pile of warning flags back in 2008. Reviewed-by: Ben Widawsky <be...@bw...> diff --git a/configure.ac b/configure.ac index 09fed53..3eaec74 100644 --- a/configure.ac +++ b/configure.ac @@ -133,7 +133,7 @@ MAYBE_WARN="-Wall -Wextra \ -Wpointer-arith -Wwrite-strings -Wstrict-prototypes \ -Wmissing-prototypes -Wmissing-declarations -Wnested-externs \ -Wpacked -Wswitch-enum -Wmissing-format-attribute \ --Wstrict-aliasing=2 -Winit-self -Wunsafe-loop-optimizations \ +-Wstrict-aliasing=2 -Winit-self \ -Wdeclaration-after-statement -Wold-style-definition \ -Wno-missing-field-initializers -Wno-unused-parameter \ -Wno-attributes -Wno-long-long -Winline" |
From: <da...@ke...> - 2012-09-06 13:37:22
|
radeon/radeon_surface.c | 136 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 135 insertions(+), 1 deletion(-) New commits: commit b925022a3e4616665b388a78abab4e3270b4b4ec Author: Michel Dänzer <mic...@am...> Date: Wed Sep 5 18:44:45 2012 +0200 radeon: Sampling pitch for non-mipmaps seems padded to slice alignment on SI. Another corner case that isn't well-explained yet. Signed-off-by: Michel Dänzer <mic...@am...> Reviewed-by: Christian König <chr...@am...> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 98faa0b..80b1505 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -974,10 +974,15 @@ static void si_surf_minify_linear_aligned(struct radeon_surface *surf, surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; } - /* XXX: Second smallest level uses larger pitch, not sure of the real reason, - * my best guess so far: rows evenly distributed across slice + /* XXX: Texture sampling uses unexpectedly large pitches in some cases, + * these are just guesses for the rules behind those */ - xalign = MAX2(xalign, slice_align / surf->bpe / surf->level[level].npix_y); + if (level == 0 && surf->last_level == 0) + /* Non-mipmap pitch padded to slice alignment */ + xalign = MAX2(xalign, slice_align / surf->bpe); + else + /* Small rows evenly distributed across slice */ + xalign = MAX2(xalign, slice_align / surf->bpe / surf->level[level].npix_y); surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, xalign); surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, yalign); commit 45083e6d36125c64267c917da3d81e1e144ed33d Author: Michel Dänzer <mic...@am...> Date: Tue Sep 4 18:53:55 2012 +0200 radeon: Memory footprint of SI mipmap base level is padded to powers of two. Signed-off-by: Michel Dänzer <mic...@am...> Reviewed-by: Christian König <chr...@am...> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 593c51c..98faa0b 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -963,9 +963,16 @@ static void si_surf_minify_linear_aligned(struct radeon_surface *surf, surf->level[level].npix_x = mip_minify(surf->npix_x, level); surf->level[level].npix_y = mip_minify(surf->npix_y, level); surf->level[level].npix_z = mip_minify(surf->npix_z, level); - surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; - surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; - surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; + + if (level == 0 && surf->last_level > 0) { + surf->level[level].nblk_x = (next_power_of_two(surf->level[level].npix_x) + surf->blk_w - 1) / surf->blk_w; + surf->level[level].nblk_y = (next_power_of_two(surf->level[level].npix_y) + surf->blk_h - 1) / surf->blk_h; + surf->level[level].nblk_z = (next_power_of_two(surf->level[level].npix_z) + surf->blk_d - 1) / surf->blk_d; + } else { + surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; + surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; + surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; + } /* XXX: Second smallest level uses larger pitch, not sure of the real reason, * my best guess so far: rows evenly distributed across slice commit 8572444fd0cda3e7b9557c09d2d0f7a9e049a2e7 Author: Michel Dänzer <mic...@am...> Date: Fri Aug 31 19:29:33 2012 +0200 radeon: Fix layout of linear aligned mipmaps on SI. Signed-off-by: Michel Dänzer <mic...@am...> Reviewed-by: Christian König <chr...@am...> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c index 4118a37..593c51c 100644 --- a/radeon/radeon_surface.c +++ b/radeon/radeon_surface.c @@ -952,6 +952,124 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man, /* =========================================================================== + * Southern Islands family + */ + +static void si_surf_minify_linear_aligned(struct radeon_surface *surf, + unsigned level, + uint32_t xalign, uint32_t yalign, uint32_t zalign, uint32_t slice_align, + unsigned offset) +{ + surf->level[level].npix_x = mip_minify(surf->npix_x, level); + surf->level[level].npix_y = mip_minify(surf->npix_y, level); + surf->level[level].npix_z = mip_minify(surf->npix_z, level); + surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1) / surf->blk_w; + surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1) / surf->blk_h; + surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1) / surf->blk_d; + + /* XXX: Second smallest level uses larger pitch, not sure of the real reason, + * my best guess so far: rows evenly distributed across slice + */ + xalign = MAX2(xalign, slice_align / surf->bpe / surf->level[level].npix_y); + + surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, xalign); + surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, yalign); + surf->level[level].nblk_z = ALIGN(surf->level[level].nblk_z, zalign); + + surf->level[level].offset = offset; + surf->level[level].pitch_bytes = surf->level[level].nblk_x * surf->bpe * surf->nsamples; + surf->level[level].slice_size = ALIGN(surf->level[level].pitch_bytes * surf->level[level].nblk_y, slice_align); + + surf->bo_size = offset + surf->level[level].slice_size * surf->level[level].nblk_z * surf->array_size; +} + +static int si_surface_init_linear_aligned(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf, + uint64_t offset, unsigned start_level) +{ + uint32_t xalign, yalign, zalign, slice_align; + unsigned i; + + /* compute alignment */ + if (!start_level) { + surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); + } + xalign = MAX2(8, 64 / surf->bpe); + yalign = 1; + zalign = 1; + slice_align = MAX2(64 * surf->bpe, surf_man->hw_info.group_bytes); + + /* build mipmap tree */ + for (i = start_level; i <= surf->last_level; i++) { + surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED; + si_surf_minify_linear_aligned(surf, i, xalign, yalign, zalign, slice_align, offset); + /* level0 and first mipmap need to have alignment */ + offset = surf->bo_size; + if ((i == 0)) { + offset = ALIGN(offset, surf->bo_alignment); + } + } + return 0; +} + +static int si_surface_init(struct radeon_surface_manager *surf_man, + struct radeon_surface *surf) +{ + unsigned mode; + int r; + + /* MSAA surfaces support the 2D mode only. */ + if (surf->nsamples > 1) { + surf->flags = RADEON_SURF_CLR(surf->flags, MODE); + surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); + } + + /* tiling mode */ + mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; + + if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { + /* zbuffer only support 1D or 2D tiled surface */ + switch (mode) { + case RADEON_SURF_MODE_1D: + case RADEON_SURF_MODE_2D: + break; + default: + mode = RADEON_SURF_MODE_1D; + surf->flags = RADEON_SURF_CLR(surf->flags, MODE); + surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); + break; + } + } + + r = eg_surface_sanity(surf_man, surf, mode); + if (r) { + return r; + } + + surf->stencil_offset = 0; + surf->stencil_tile_split = 0; + + /* check tiling mode */ + switch (mode) { + case RADEON_SURF_MODE_LINEAR: + r = r6_surface_init_linear(surf_man, surf, 0, 0); + break; + case RADEON_SURF_MODE_LINEAR_ALIGNED: + r = si_surface_init_linear_aligned(surf_man, surf, 0, 0); + break; + case RADEON_SURF_MODE_1D: + r = eg_surface_init_1d(surf_man, surf, 0, 0); + break; + case RADEON_SURF_MODE_2D: + r = eg_surface_init_2d(surf_man, surf, 0, 0); + break; + default: + return -EINVAL; + } + return r; +} + +/* =========================================================================== * public API */ struct radeon_surface_manager *radeon_surface_manager_new(int fd) @@ -980,7 +1098,11 @@ struct radeon_surface_manager *radeon_surface_manager_new(int fd) if (eg_init_hw_info(surf_man)) { goto out_err; } - surf_man->surface_init = &eg_surface_init; + if (surf_man->family <= CHIP_ARUBA) { + surf_man->surface_init = &eg_surface_init; + } else { + surf_man->surface_init = &si_surface_init; + } surf_man->surface_best = &eg_surface_best; } |
From: <ic...@ke...> - 2012-10-07 09:10:41
|
intel/intel_bufmgr_gem.c | 3 +-- intel/intel_decode.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) New commits: commit a83444c925b18b3db431336360d6915aaf21f727 Author: Chris Wilson <ch...@ch...> Date: Sun Oct 7 10:08:46 2012 +0100 intel: Silence a trivial compiler warning intel_bufmgr_gem.c: In function 'drm_intel_bo_gem_export_to_prime': intel_bufmgr_gem.c:2477:6: warning: unused variable 'ret' [-Wunused-variable] Signed-off-by: Chris Wilson <ch...@ch...> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 3f7424c..8d45839 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -2472,7 +2472,6 @@ drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd) { drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; - int ret; if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle, DRM_CLOEXEC, prime_fd) != 0) commit 8cf3475eb5d887c361db372a644d0d1a11e137f8 Author: Chris Wilson <ch...@ch...> Date: Sun Oct 7 10:07:23 2012 +0100 intel: Correct the word decoding for gen2 3DSTATE_LOAD_STATE_IMMEDIATE_1 Signed-off-by: Chris Wilson <ch...@ch...> diff --git a/intel/intel_decode.c b/intel/intel_decode.c index 19a8d36..a4b045a 100644 --- a/intel/intel_decode.c +++ b/intel/intel_decode.c @@ -1714,7 +1714,7 @@ decode_3d_1d(struct drm_intel_decode *ctx) } } else { instr_out(ctx, i, - "S%d: 0x%08x\n", i, data[i]); + "S%d: 0x%08x\n", word, data[i]); } i++; } commit 75830a0d2cbb614ecc3f7e6b516ec595bb41d6a3 Author: Chris Wilson <ch...@ch...> Date: Sun Oct 7 10:05:19 2012 +0100 intel: Fix "properly test for HAS_LLC" commit 92fd0ce4f659d7b0680543e9e5b96a3c7737a5f3 Author: Daniel Vetter <dan...@ff...> Date: Fri Aug 31 11:16:53 2012 +0200 intel: properly test for HAS_LLC missed slightly and in effect had no effect on the outcome of checking whether the kernel/chipset supported LLC. Signed-off-by: Chris Wilson <ch...@ch...> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 898008d..3f7424c 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -3119,7 +3119,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size) bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) | IS_GEN7(bufmgr_gem->pci_device)); } else - bufmgr_gem->has_llc = gp.value; + bufmgr_gem->has_llc = *gp.value; if (bufmgr_gem->gen < 4) { gp.param = I915_PARAM_NUM_FENCES_AVAIL; |
From: <da...@ke...> - 2013-06-25 22:37:37
|
intel/intel_aub.h | 76 ++++++++++++++++++++++++++++++++--------------- intel/intel_bufmgr.h | 3 + intel/intel_bufmgr_gem.c | 27 ++++++++++++++++ 3 files changed, 82 insertions(+), 24 deletions(-) New commits: commit fbd106ad76b0ee33814f6a5b94efaa0b067ec2af Author: Damien Lespiau <dam...@in...> Date: Wed Feb 20 12:11:49 2013 +0000 intel/aub: Implement a way to specify the output .aub filename Signed-off-by: Damien Lespiau <dam...@in...> Reviewed-by: Kenneth Graunke <ke...@wh...> diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h index 8d7f239..15f818e 100644 --- a/intel/intel_bufmgr.h +++ b/intel/intel_bufmgr.h @@ -171,6 +171,9 @@ int drm_intel_gem_bo_get_reloc_count(drm_intel_bo *bo); void drm_intel_gem_bo_clear_relocs(drm_intel_bo *bo, int start); void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable); +void +drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr, + const char *filename); void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable); void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo, int x1, int y1, int width, int height, diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 7b1ecf1..a51e3f3 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -128,6 +128,7 @@ typedef struct _drm_intel_bufmgr_gem { unsigned int has_vebox : 1; bool fenced_relocs; + char *aub_filename; FILE *aub_file; uint32_t aub_offset; } drm_intel_bufmgr_gem; @@ -1574,6 +1575,7 @@ drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr) free(bufmgr_gem->exec2_objects); free(bufmgr_gem->exec_objects); free(bufmgr_gem->exec_bos); + free(bufmgr_gem->aub_filename); pthread_mutex_destroy(&bufmgr_gem->lock); @@ -2865,6 +2867,23 @@ drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr) } /** + * Sets the AUB filename. + * + * This function has to be called before drm_intel_bufmgr_gem_set_aub_dump() + * for it to have any effect. + */ +void +drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr, + const char *filename) +{ + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; + + free(bufmgr_gem->aub_filename); + if (filename) + bufmgr_gem->aub_filename = strdup(filename); +} + +/** * Sets up AUB dumping. * * This is a trace file format that can be used with the simulator. @@ -2879,6 +2898,7 @@ drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable) int entry = 0x200003; int i; int gtt_size = 0x10000; + const char *filename; if (!enable) { if (bufmgr_gem->aub_file) { @@ -2891,7 +2911,11 @@ drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable) if (geteuid() != getuid()) return; - bufmgr_gem->aub_file = fopen("intel.aub", "w+"); + if (bufmgr_gem->aub_filename) + filename = bufmgr_gem->aub_filename; + else + filename = "intel.aub"; + bufmgr_gem->aub_file = fopen(filename, "w+"); if (!bufmgr_gem->aub_file) return; commit 1e4f63bbc8e9a23c90745e10027e2772bab15038 Author: Damien Lespiau <dam...@in...> Date: Wed Feb 20 12:11:50 2013 +0000 intel/aub: Return early if we disable aub dumps No need to prepare the .aub header and dump in that case, it'll be done with the next call with true. Signed-off-by: Damien Lespiau <dam...@in...> Reviewed-by: Kenneth Graunke <ke...@wh...> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 3c73068..7b1ecf1 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -2885,6 +2885,7 @@ drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable) fclose(bufmgr_gem->aub_file); bufmgr_gem->aub_file = NULL; } + return; } if (geteuid() != getuid()) commit 59257580666cf5f5916bf989d94bace774030bd5 Author: Damien Lespiau <dam...@in...> Date: Wed Feb 20 12:11:48 2013 +0000 intel/aub: Sync the AUB defines with mesa's Signed-off-by: Damien Lespiau <dam...@in...> Reviewed-by: Kenneth Graunke <ke...@wh...> diff --git a/intel/intel_aub.h b/intel/intel_aub.h index a36fd53..5f0aba8 100644 --- a/intel/intel_aub.h +++ b/intel/intel_aub.h @@ -93,29 +93,59 @@ #define AUB_TRACE_MEMTYPE_GTT_ENTRY (4 << 16) /* DW2 */ -// operation = TRACE_DATA_WRITE, Type = TRACE_DATA_WRITE_GENERAL_STATE -#define AUB_TRACE_GENERAL_STATE_MASK 0x000000ff - -#define AUB_TRACE_VS_STATE 0x00000001 -#define AUB_TRACE_GS_STATE 0x00000002 -#define AUB_TRACE_CL_STATE 0x00000003 -#define AUB_TRACE_SF_STATE 0x00000004 -#define AUB_TRACE_WM_STATE 0x00000005 -#define AUB_TRACE_CC_STATE 0x00000006 -#define AUB_TRACE_CL_VP 0x00000007 -#define AUB_TRACE_SF_VP 0x00000008 -#define AUB_TRACE_CC_VP 0x00000009 -#define AUB_TRACE_SAMPLER_STATE 0x0000000a -#define AUB_TRACE_KERNEL 0x0000000b -#define AUB_TRACE_SCRATCH 0x0000000c -#define AUB_TRACE_SDC 0x0000000d -#define AUB_TRACE_BLEND_STATE 0x00000016 -#define AUB_TRACE_DEPTH_STENCIL_STATE 0x00000017 - -// operation = TRACE_DATA_WRITE, Type = TRACE_DATA_WRITE_SURFACE_STATE -#define AUB_TRACE_SURFACE_STATE_MASK 0x00000ff00 -#define AUB_TRACE_BINDING_TABLE 0x000000100 -#define AUB_TRACE_SURFACE_STATE 0x000000200 + +/** + * aub_state_struct_type enum values are encoded with the top 16 bits + * representing the type to be delivered to the .aub file, and the bottom 16 + * bits representing the subtype. This macro performs the encoding. + */ +#define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype)) + +enum aub_state_struct_type { + AUB_TRACE_VS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 1), + AUB_TRACE_GS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 2), + AUB_TRACE_CLIP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 3), + AUB_TRACE_SF_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 4), + AUB_TRACE_WM_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 5), + AUB_TRACE_CC_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 6), + AUB_TRACE_CLIP_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 7), + AUB_TRACE_SF_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 8), + AUB_TRACE_CC_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x9), + AUB_TRACE_SAMPLER_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xa), + AUB_TRACE_KERNEL_INSTRUCTIONS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xb), + AUB_TRACE_SCRATCH_SPACE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xc), + AUB_TRACE_SAMPLER_DEFAULT_COLOR = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xd), + + AUB_TRACE_SCISSOR_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x15), + AUB_TRACE_BLEND_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x16), + AUB_TRACE_DEPTH_STENCIL_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x17), + + AUB_TRACE_VERTEX_BUFFER = ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER, 0), + AUB_TRACE_BINDING_TABLE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x100), + AUB_TRACE_SURFACE_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x200), + AUB_TRACE_VS_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 0), + AUB_TRACE_WM_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 1), +}; + +#undef ENCODE_SS_TYPE + +/** + * Decode a aub_state_struct_type value to determine the type that should be + * stored in the .aub file. + */ +static inline uint32_t AUB_TRACE_TYPE(enum aub_state_struct_type ss_type) +{ + return (ss_type & 0xFFFF0000) >> 16; +} + +/** + * Decode a state_struct_type value to determine the subtype that should be + * stored in the .aub file. + */ +static inline uint32_t AUB_TRACE_SUBTYPE(enum aub_state_struct_type ss_type) +{ + return ss_type & 0xFFFF; +} /* DW3: address */ /* DW4: len */ |