[Dpcl-develop] ia64 'check_lock'

[Steve C. <sl...@sg...>]

   The 'cmpxchg4' on ia64 requires that a specific applications register
 (ar.ccv) be loaded prior to the actual compare. That said, I think that
 the routine '_check_lock' will look something like the following. Note
 that the GCC assembler interface allows for 'named' (.vs. 'numbered')
 operands with release 3.3.1 or later. Thus for the 'mov' instruction
 below the 'named' version of the single input operand can be '%[old]'
 versus (e.g.) '%1'. Using gcc 2.96 and numbered operands is causing
 me grief with operand alignments and I can't get things to work with
 2.9.6. So, I'm in hot pursuit of gcc 3.3.1 on ia64 so I can try the
 'named' operand assembler version (shown below). 

                                                  SteveC

int
_check_lock
(atomic_p addr, int old_val, int new_val)
{
    long result = 1;
    long interim_val = 1;

     __asm__ __volatile__ ( "mf"); /* memory fence */
     __asm__ __volatile__ (
                "mov ar.ccv = %[old]"
                : "=r"(interim_val) : [old] "r"(old_val));
     __asm__ __volatile__ (
                "cmpxchg4.acq %[interim] =%[mem],%[new],ar.ccv"
                : [interim] "=r" (interim_val)
                : [mem] "r" (addr), [new] "r" (new_val));
     __asm__ __volatile__ ( "mf"); /* memory fence */

    if(*(int *)(addr) == new_val) {
       /* lock memory value  was old_val */
       /* exchange to new_val done - new lock in place */
       result = 0; /* false */
    }
    else {
       /* lock memory value  was NOT old_val */
       /* locked exchange failed */
       result = 1; /* true */
    }
    return result;
}