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From: Masami H. <mhi...@re...> - 2009-10-17 00:07:19
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Add AMD prefetch and 3DNow! opcode including FEMMS. Since 3DNow! uses the last immediate byte as an opcode extension byte, x86 insn just treats the extenstion byte as an immediate byte instead of a part of opcode (insn_get_opcode() decodes first "0x0f 0x0f" bytes.) Users who are interested in analyzing 3DNow! opcode still can decode it by analyzing the immediate byte. Signed-off-by: Masami Hiramatsu <mhi...@re...> Cc: H. Peter Anvin <hp...@zy...> Cc: Frederic Weisbecker <fwe...@gm...> Cc: Ingo Molnar <mi...@el...> Cc: Thomas Gleixner <tg...@li...> Cc: Arnaldo Carvalho de Melo <ac...@re...> Cc: Steven Rostedt <ro...@go...> Cc: Mike Galbraith <ef...@gm...> Cc: Paul Mackerras <pa...@sa...> Cc: Peter Zijlstra <a.p...@ch...> Cc: Christoph Hellwig <hc...@in...> Cc: Ananth N Mavinakayanahalli <an...@in...> Cc: Jim Keniston <jke...@us...> Cc: Frank Ch. Eigler <fc...@re...> --- arch/x86/lib/x86-opcode-map.txt | 13 ++++++++++--- 1 files changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt index e7285d8..894497f 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -306,9 +306,10 @@ Referrer: 2-byte escape 0a: 0b: UD2 (1B) 0c: -0d: NOP Ev -0e: -0f: +0d: NOP Ev | GrpP +0e: FEMMS +# 3DNow! uses the last imm byte as opcode extension. +0f: 3DNow! Pq,Qq,Ib # 0x0f 0x10-0x1f 10: movups Vps,Wps | movss Vss,Wss (F3) | movupd Vpd,Wpd (66) | movsd Vsd,Wsd (F2) 11: movups Wps,Vps | movss Wss,Vss (F3) | movupd Wpd,Vpd (66) | movsd Wsd,Vsd (F2) @@ -813,6 +814,12 @@ GrpTable: Grp16 3: prefetch T2 EndTable +# AMD's Prefetch Group +GrpTable: GrpP +0: PREFETCH +1: PREFETCHW +EndTable + GrpTable: GrpPDLK 0: MONTMUL 1: XSHA1 -- Masami Hiramatsu Software Engineer Hitachi Computer Products (America), Inc. Software Solutions Division e-mail: mhi...@re... |