#3 Clock gating not supported

[Gavin J Stark]

CDL does not support clock gating

A clock gate should be instantiatable with:

clock_gate <gated clock name> clock <clock name> enable <signal> [override <signal>]

The override signal is required for test

The verilog output should instantiate a cell given by a standard template.

The C model must evaluate the enable and override prior to calling the preclock function; note that any C model will have a clock/preclock that the gated clocks depend upon anyhow.

[Gavin J Stark]

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Feature request for v1.1.0

Clock gating can be inferred by the synthesis tool if correct coding style is used - bulk clock gating like this may be permissible, but is not required at present