#13 Clocked outputs require clock/reset early in ports

[Gavin J Stark]

module a (output bit b, clock c, input bit rst)
{
clocked clock c reset rst bit b=0;
{ b<=1; }
}

Will fail as the clock or reset are defined in the port list after the output bit, which is then shadowed as a clock.

[Gavin J Stark]

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