#7 covered creates signal vectors with negative width

[Anonymous]

Hello Trevor,

I am sorry to open two support requests in such a short time. I was trying to score a design that pads a signal of variable datawidth like so:

assign pc_dout       = (DATAWIDTH >= 16) ? {{(DATAWIDTH-16){1'b0}}, pc_dout_unpadded} : pc_dout_unpadded[DATAWIDTH-1:0];

This statement is obviously reduced during synthesis, the default parameter DATAWIDTH being 8.

When covered evaluates the first conditional of the expression, it creates a vector with unsigned width (8-16 = 4294967288).

print *vec
$1 = {width = 4294967288, suppl = {all = 18 '\022', part = {type = 2 '\002', data_type = 0 '\000', owns_data = 1 '\001', is_signed = 0 '\000', 
  is_2state = 0 '\000', set = 0 '\000'}}, value = {ul = 0x0, r64 = 0x0, r32 = 0x0}}

The result is an errant behavior in void vector_db_write in expr.c. The following loop is trying to execute 4294967287 times:

ulong        hmask  = UL_HMASK( vec->width - 1 );
for( i=0; i<(UL_SIZE(vec->width) - 1); i++ ) {
  fprintf( file, " %lx", (write_data && (vec->value.ul != NULL)) ? vec->value.ul[i][VTYPE_INDEX_VAL_VALL] : dflt_l );
  fprintf( file, " %lx", (write_data && (vec->value.ul != NULL)) ? vec->value.ul[i][VTYPE_INDEX_VAL_VALH] : dflt_h );
  ...
}

I am not sure how to handle this error correctly. I would suggest checking for negative signal/expression widths when creating a vector an eliminating such signals from the coverage test?

Kind regards,

Chris