#4 covered score segmentation fault

[Anonymous]

Hi Trevor,

I've a segFault issue with the command :
covered score -v bench.v -i "top.Dut" -vpi -t myDut
corresponding to following line
filelist_curr = curr->next;
in lexer.c (l 1025) because curr->next is Null
The use Os is RHEl 7.x with gcc 4.8.5

I don't understand whythe parsing is done multiple time :
Reading design...
Parsing file 'bench.v'
Parsing file 'bench.v'
Parsing file 'bench.v'
Parsing file 'bench.v'
Parsing file 'bench.v'
Parsing file 'bench.v'
And the error occurs only at the 6th time, is it normal ?

I'm sure that my verilog code is syntaxically and functionnaly correct (compiled and simulated with Nc and/or Cvc). File is about 20k verilog lines
Do you've an idea on how I can debug that ?

Regards,

Sylvain

[Trevor Williams]

Without doing some debug of my own with your Verilog, I'm not sure that I could tell you what the issue is. I would say that seeing the same file parsed over and over is not what I would expect; however, it has been a long time since I have worked on Covered, so I cannot say whether this behavior is correct or not.

I thought that there was a global verbosity flag that you can pass to any function that might provide more insight into what is going on behind the scenes. I think that the documentation should provide you some clues in terms of debugging options.

I no longer actively work on this project so I'm going to punt on digging deep into this problem.

[Anonymous]

Hi Trevor,
Thanks for your answer. I've already enable debug option but that not help me a lot.
If I send you the verilog file do you think you can have look on that issue or it's a too old project ?

[Trevor Williams]

I am going to pass on looking into this issue more deeply.

[Anonymous]

Original issue seems linked to long module name. Unfortunatly I can attach the testcase as is and when I replace module name, command works.

[Anonymous]

Hi Trevor,
The root cause of the segFault is linked to a preprocessing directive for module declaration as:
ifndef SIM_GATERCELLdefine SIM_GATERCELL
module GaterCell ( CLKIN , CLKOUT , EN , RSTN , TE );
input CLKIN ;
output CLKOUT ;
input EN ;
input RSTN ;
input TE ;
lib_ClkEn_R uClkEn( .En( EN | TE | ~ RSTN ) , .I( CLKIN ) , .O( CLKOUT ) );
endmodule
`endif
Regards
Sylvain

[Anonymous]

I've reduce the issue to a simple test case (attachement)