#37 Verilog 2001 style for tasks

[Iztok Jeras]

Tasks written in Verilog 2001 style report an error during parsing. An error is reported for the '(' in the first line

task avalon_cycle (
input r_w, // 0-read or 1-write cycle
input [AAW-1:0] adr,
input [ABW-1:0] ben,
input [ADW-1:0] wdt,
output [ADW-1:0] rdt
);
begin
...
end
endtask

Constants with undefined width are also not recognized properly. Example:
address = 'dx;
261: unmatched character (')

Regards,
Iztok Jeras