Add *FLAGS for some build targets
Fix build failure with gcc-15
Fix implicit declarations
Fix spelling mistakes
Hi Trevor, Thanks for your answer. I've already enable debug option but that not help me a lot. If I send you the verilog file do you think you can have look on that issue or it's a too old project ?
Original issue seems linked to long module name. Unfortunatly I can attach the testcase as is and when I replace module name, command works.
Hi Trevor, The root cause of the segFault is linked to a preprocessing directive for module declaration as: ifndef SIM_GATERCELLdefine SIM_GATERCELL module GaterCell ( CLKIN , CLKOUT , EN , RSTN , TE ); input CLKIN ; output CLKOUT ; input EN ; input RSTN ; input TE ; lib_ClkEn_R uClkEn( .En( EN | TE | ~ RSTN ) , .I( CLKIN ) , .O( CLKOUT ) ); endmodule `endif Regards Sylvain
I've reduce the issue to a simple test case (attachement)
I am going to pass on looking into this issue more deeply.
Without doing some debug of my own with your Verilog, I'm not sure that I could tell you what the issue is. I would say that seeing the same file parsed over and over is not what I would expect; however, it has been a long time since I have worked on Covered, so I cannot say whether this behavior is correct or not. I thought that there was a global verbosity flag that you can pass to any function that might provide more insight into what is going on behind the scenes. I think that the documentation...
covered score segmentation fault
Thank you for submitting this patch. With the permission of @phase1geo I have created a covered repository in github. Your patch is added to this new repository. Please find the new repository at https://github.com/chiphackers/covered
Upgrade to Tcl/Tk 8.6
Updated patch to fix FTBFS with GCC 5, that is achieved by marking inline function...