#60 Transistor circuit with feedback fails to work

[Daniel Quinz]

Logisim 2.7.0

Attempting to create a set/reset flip-flop using the transistor library fails to work. Upon simulation reset, all wires are blue. Trying to assert set or reset then leads to red wires indicating invalid logic levels or conflict.

I have created the identical circuit using built-in 2-input NAND gates as a reference and this one works correctly. After the initial error level, a set or reset resolves the wire leve and the circuit works correctly.

Note too that in the 2-input NAND transistor circuit, a pull-up resistor is required or the circuit fails to operate.

I have tried placing a built-in non-inverting driver in the feedback path of the transistor circuit to now avail. Additional pull up/down resistors also make no difference.

As the transistor library is new, I am not sure if the issue is the library or how I am using it.

Attached is a circuit that shows all of the above and can reproduce the behavior.

[Daniel Quinz]

Example transistor FF circuit and reference circuits

[Daniel Quinz]

Added 2-NOR FF with same problem

[Carl Burch]

Added a D latch built using 8 transistors

[Carl Burch]

Fascinating! Thanks for bringing up this issue. As you say, the transistor is very new, and it may well be misdesigned on this point.

I can remove the need for pull-up resistors by changing it so that the transistor transmits floating values rather than "converting" them to error values. That *may* be the right way to design this; I'll have to check.

However, this isn't the issue with the 2-NAND latch built with transistors. Here, the problem is one of timing, which you can see if you disable simulation and then use Ctrl+I to go through the simulation step by step: Essentially, you have a signal reaching the two P-type transistors in parallel at the same time as the signal reaches the N-type transistor that is closer to ground. The P-type transistors cut off sending anything to the "NAND gate" output immediately, while the N-type transistor takes an extra step to affect the "NAND gate" output (since there's another N-type transistor that the signal must travel through). As a result, for a quick instant the "NAND gate" is floating, which then proceeds to mess up the transistors in the other "NAND gate."

I don't immediately see how to repair this directly, and right now I'm wondering whether the two-NAND latch could be a convenient fiction propagated by textbooks even though it doesn't actually work - in which case I shouldn't expect Logisim to handle it when it's built using transistors. I need to check into that further.

In the meantime, I did a bit of searching on the Web and found a D latch built using eight transistors (or four transistors and two transmission gates) that *does* work in Logisim:

http://www.ece.rice.edu/Courses/422/1997/shion/VLSI/logic.html

I've attached a file including my implementation of this. Note that I routed the "store" input so that it reaches a buffer and a NOT gate in parallel, each of which is then sent to the different ends of the transmission gates. This is so that a change to the "store" input will reach both ends of the transmission gate simultaneously.

I've attached a file where I've added this implementation

[Ilia Lilov]

Danielq, may be you will be interested: I implemented 14 gates (CMOS and NMOS logic) and 12 flip-flops using them using transistors. 3 of 12 flip-flops work fine. Project file with all these circuits is here: http://lilpm32.sourceforge.net/transistors-gates_flipflops_v01.circ

[Carl Burch]

I've done some comparison with Verilog and found that Verilog transistors transmit floating values as floating values. Also, I found that they transmit floating values regardless of gate - even if gate is error, floating is still sent through the transistor.

I've just uploaded a fragile release (2.7.1.237) that implements this concept. Using it, you shouldn't have to use the pull resistors that you were using previously.

However, your latch circuit still doesn't work in this new version. Comparison with Verilog reveals the reason why: When the gate is floating or error in Verilog, and the source is 1 (or 0), the drain is H (or L). Logisim doesn't (yet) support values other than 0, 1, floating, and error, so it can't really handle H and L properly. For now, the fragile releases uses the error value instead.

On a lark, I tried making it so Logisim transistors output 1 (or 0) in this situation. This actually allows your latch circuit to work. But it is hopelessly confusing: Essentially, this is saying that when the transistor's gate input is floating or X, the transistor just goes ahead and assumes it's being told to transmit the value. I'm not currently inclined to worry about the latch circuit so much as to give the transistor this unexpected behavior.

Anyway, the appropriate solution to this issue (as far as I can tell) is for Logisim to support H and L logic values. That's a more sweeping change to Logisim than just a bug. I'm going to reclass this report, therefore, as a feature request.

However, the first issue you mentioned, with the pull resistors, was indeed a bug. That has been repaired, and it will appear in version 2.7.1, which I'm hoping will be out later this week or early next week. Or you could download the latest fragile release. Thanks again for the report!

[Daniel Quinz]

re: H/L output levels.

I understand.

re: Example circuits

Thanks Lilovip, I will take a look at the circuits you referene.

Cheers!

Dan