Unexpected overwrite of register contents
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Very small circuit exhibiting the bug
It isn't Logisim bug; on the contrary, it's completely right behavior. Let's look what is happening:
When we have 03 on the out and clock is 0, one input of AND has 1. The next tick T flip-flop and other AND's input get 1 form clock.T flip-flop has latency, so FIRST AND get 1 on both inputs, and LATER T flip-flop flips. This interval very small, so you can't see it as light-green wire on AND's out, but it is enough long to trigger register.
Thanks for distilling this into such a small circuit that really gets the point across. Ilia is right: Logisim is simulating the circuit correctly - it's just that your elegantly constructed example displays a race condition. This race condition will result in the AND gate briefly emitting a 1.
Let me try to explain it in different words than Ilia's in case that helps explain further. Suppose the clock is 0 and the T flip-flop is 1. Of course, the AND gate sees both of these and emits a 1. Now suppose the clock flips to 1. That clock signal reaches the AND gate immediately, so the AND gate sees a 1 from the clock and a 1 from the T flip-flop - so the AND gate's output changes to 1. Of course, at the same time as the AND gate receives the clock's 1, so does the T flip-flop - but Logisim simulates a delay (since that's what would happen in a real circuit), so a bit of time elapses before the flip-flop reaches 0. (For that matter, there's a small delay between the AND gate seeing two 1 inputs and its output changing to 1 - though it's not important here.)
As Ilia says, all this happens so quickly that you can't observe it in real time - in fact, you probably don't even see it appear on screen since the output likely flips back to 0 before Logisim gets a chance to repaint the window. Unfortunately, Logisim doesn't have good support yet for tracing this out.
Thanks both for the quick reply and the excellent explanation. You guys rock!