As described in RM0008 Reference manual Cls 18.4.2
Bit 3 RSF:Registers synchronized flag
This bit is set by hardware at each time the RTC_CNT and RTC_DIV registers are updated
and cleared by software. Before any read operation after an APB1 reset or an APB1 clock
stop, this bit must be cleared by software, and the user application must wait until it is set to
be sure that the RTC_CNT, RTC_ALR orRTC_PRL registers are synchronized.
There is no software resetting of that bit in Chibios.
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