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#1308 ARM Cortex M0 SystemHandler IDs
Hi,
I think there might be a bug regarding the SystemHandler IDs for ARM Cortex M0 MCUs.
I'm running ChibiOS (and ChibiOS-contrib) on SonixQMK on an SN32F268.
ChibiOS is latest qmk-master branch (21.11.4 i think).
I know, this is an obscure processor but I think this bug affects all Arm CM0 devices.
Background:
In an effort to prevent ISR nesting I tried to set all IRQs/SystemHandlers to the same priority.
This seems to work for IRQs, as these are defined in the MCU-specific includes.
For the SystemHandlers, this seems to be different:
They are defined in /os/hal/ports/common/ARMCMx/nvic.h
Looking at the ARM documentation, the vector numbers definede there (also used to set the bits in the priority registers of SCB) seem to be different, at least for M0-cores.
https://developer.arm.com/documentation/dui0497/a/cortex-m0-peripherals/system-control-block/system-handler-priority-registers?lang=en
For example, HANDLER_SYSTICK is defined as 11, but in the ARM docs it's PRI_15 (PRI_11 is SVCall).
Calling nvicSetSystemHandlerPriority(15, prio) instead of nvicSetSystemHandlerPriority(HANDLER_SYSTICK, prio) also sets the Interrupt priority of the SysTick correctly.
The macros used for generating the bit pattern and selecting the priority registers of the SCB seem correct to me though.
As I'm not really familiar with thie ChibiOS or QMK codebase I might very well be wrong here and misunderstand something.
Also that's why I didn't just wanto create a PR and rather start a "discussion" here.
Thanks!
Hi, we opened a PR here: https://github.com/chibios-upstream/chibios/pull/34
A fix has already been proposed if you want to give it a try. If you have a github account you may participate there too.