[Bochs-cvs] CVS: bochs/cpu paging.cc,1.25,1.26

[Kevin P L. <kev...@us...>]

Update of /cvsroot/bochs/bochs/cpu
In directory usw-pr-cvs1:/tmp/cvs-serv20672/cpu

Modified Files:
	paging.cc 
Log Message:
Added a configure option, "--enable-pae".  The x86-64 enhancements
already had Physical Address Extensions support - we can now
compile for PAE support for x86-32 mode as well.


Index: paging.cc
===================================================================
RCS file: /cvsroot/bochs/bochs/cpu/paging.cc,v
retrieving revision 1.25
retrieving revision 1.26
diff -u -d -r1.25 -r1.26
--- paging.cc	16 Sep 2002 21:10:31 -0000	1.25
+++ paging.cc	16 Sep 2002 21:55:57 -0000	1.26
@@ -571,7 +571,7 @@
   InstrTLB_Increment(tlbLookups);
   InstrTLB_Stats();
 
-#if BX_SUPPORT_X86_64
+#if BX_SupportPAE
   if (BX_CPU_THIS_PTR cr4.get_PAE()) {
     Bit32u   pdp, pdp_addr;
 
@@ -601,6 +601,7 @@
     //  note - we assume physical memory < 4gig so for brevity & speed, we'll use
     //  32 bit entries although cr3 is expanded to 64 bits.
 
+#if BX_SUPPORT_X86_64
     if (BX_CPU_THIS_PTR msr.lma) {
       Bit32u   pml4, pml4_addr;
       // Get PML4 entry
@@ -621,7 +622,9 @@
       pdp_addr =  (pml4 & 0xfffff000) |
                   ((laddr & BX_CONST64(0x0000007fc0000000)) >> 27);
       }
-    else {
+    else
+#endif
+      {
       pdp_addr = (BX_CPU_THIS_PTR cr3 & 0xfffff000) |
                ((laddr & 0xc0000000) >> 27);
       }
@@ -769,10 +772,10 @@
 
     return(paddress);
     }
-#endif  // #if BX_SUPPORT_X86_64
+#endif  // #if BX_SupportPAE
 
 
-  // {CR4.PAE==0, MSR.LMA==0}
+  // CR4.PAE==0 (and MSR.LMA==0)
 
   lpf       = laddr & 0xfffff000; // linear page frame
   poffset   = laddr & 0x00000fff; // physical offset