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[Bochs-cvs] [11857] trunk/bochs
|
From: <ssh...@us...> - 2013-10-06 18:38:02
|
Revision: 11857
Author: sshwarts
Date: 2013-10-06 18:37:56 +0000 (Sun, 06 Oct 2013)
Log Message:
-----------
disasm bug fixes
Modified Paths:
--------------
trunk/bochs/cpu/disasm.cc
trunk/bochs/cpu/ia_opcodes.h
trunk/bochs/disasm/dis_tables.inc
trunk/bochs/disasm/opcodes.inc
Modified: trunk/bochs/cpu/disasm.cc
===================================================================
--- trunk/bochs/cpu/disasm.cc 2013-10-06 18:10:58 UTC (rev 11856)
+++ trunk/bochs/cpu/disasm.cc 2013-10-06 18:37:56 UTC (rev 11857)
@@ -312,8 +312,17 @@
break;
case BX_IMM_BrOff32:
{
- bx_address target = rip + i->ilen() + (Bit32s) i->Id();
- disbufptr = dis_sprintf(disbufptr, ".%+d (0x" FMT_ADDRX ")", i->Id(), cs_base + target);
+#if BX_SUPPORT_X86_64
+ if (i->os64L()) {
+ Bit64u target = rip + i->ilen() + (Bit32s) i->Id();
+ disbufptr = dis_sprintf(disbufptr, ".%+d (0x" FMT_ADDRX ")", i->Id(), (Bit64u) (cs_base + target));
+ }
+ else
+#endif
+ {
+ Bit32u target = rip + i->ilen() + (Bit32s) i->Id();
+ disbufptr = dis_sprintf(disbufptr, ".%+d (0x%08x)", i->Id(), (Bit32u) (cs_base + target));
+ }
}
break;
case BX_RSIREF:
Modified: trunk/bochs/cpu/ia_opcodes.h
===================================================================
--- trunk/bochs/cpu/ia_opcodes.h 2013-10-06 18:10:58 UTC (rev 11856)
+++ trunk/bochs/cpu/ia_opcodes.h 2013-10-06 18:37:56 UTC (rev 11857)
@@ -506,29 +506,29 @@
bx_define_opcode(BX_IA_NOT_Ed, &BX_CPU_C::NOT_EdM, &BX_CPU_C::NOT_EdR, 0, OP_Ed, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_NEG_Ed, &BX_CPU_C::NEG_EdM, &BX_CPU_C::NEG_EdR, 0, OP_Ed, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_ROL_Eb, &BX_CPU_C::ROL_EbM, &BX_CPU_C::ROL_EbR, 0, OP_Eb, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_ROR_Eb, &BX_CPU_C::ROR_EbM, &BX_CPU_C::ROR_EbR, 0, OP_Eb, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_RCL_Eb, &BX_CPU_C::RCL_EbM, &BX_CPU_C::RCL_EbR, 0, OP_Eb, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_RCR_Eb, &BX_CPU_C::RCR_EbM, &BX_CPU_C::RCR_EbR, 0, OP_Eb, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_SHL_Eb, &BX_CPU_C::SHL_EbM, &BX_CPU_C::SHL_EbR, 0, OP_Eb, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_SHR_Eb, &BX_CPU_C::SHR_EbM, &BX_CPU_C::SHR_EbR, 0, OP_Eb, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_SAR_Eb, &BX_CPU_C::SAR_EbM, &BX_CPU_C::SAR_EbR, 0, OP_Eb, OP_NONE, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_ROL_Eb, &BX_CPU_C::ROL_EbM, &BX_CPU_C::ROL_EbR, 0, OP_Eb, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_ROR_Eb, &BX_CPU_C::ROR_EbM, &BX_CPU_C::ROR_EbR, 0, OP_Eb, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_RCL_Eb, &BX_CPU_C::RCL_EbM, &BX_CPU_C::RCL_EbR, 0, OP_Eb, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_RCR_Eb, &BX_CPU_C::RCR_EbM, &BX_CPU_C::RCR_EbR, 0, OP_Eb, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_SHL_Eb, &BX_CPU_C::SHL_EbM, &BX_CPU_C::SHL_EbR, 0, OP_Eb, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_SHR_Eb, &BX_CPU_C::SHR_EbM, &BX_CPU_C::SHR_EbR, 0, OP_Eb, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_SAR_Eb, &BX_CPU_C::SAR_EbM, &BX_CPU_C::SAR_EbR, 0, OP_Eb, OP_CLReg, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_ROL_Ew, &BX_CPU_C::ROL_EwM, &BX_CPU_C::ROL_EwR, 0, OP_Ew, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_ROR_Ew, &BX_CPU_C::ROR_EwM, &BX_CPU_C::ROR_EwR, 0, OP_Ew, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_RCL_Ew, &BX_CPU_C::RCL_EwM, &BX_CPU_C::RCL_EwR, 0, OP_Ew, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_RCR_Ew, &BX_CPU_C::RCR_EwM, &BX_CPU_C::RCR_EwR, 0, OP_Ew, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_SHL_Ew, &BX_CPU_C::SHL_EwM, &BX_CPU_C::SHL_EwR, 0, OP_Ew, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_SHR_Ew, &BX_CPU_C::SHR_EwM, &BX_CPU_C::SHR_EwR, 0, OP_Ew, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_SAR_Ew, &BX_CPU_C::SAR_EwM, &BX_CPU_C::SAR_EwR, 0, OP_Ew, OP_NONE, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_ROL_Ew, &BX_CPU_C::ROL_EwM, &BX_CPU_C::ROL_EwR, 0, OP_Ew, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_ROR_Ew, &BX_CPU_C::ROR_EwM, &BX_CPU_C::ROR_EwR, 0, OP_Ew, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_RCL_Ew, &BX_CPU_C::RCL_EwM, &BX_CPU_C::RCL_EwR, 0, OP_Ew, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_RCR_Ew, &BX_CPU_C::RCR_EwM, &BX_CPU_C::RCR_EwR, 0, OP_Ew, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_SHL_Ew, &BX_CPU_C::SHL_EwM, &BX_CPU_C::SHL_EwR, 0, OP_Ew, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_SHR_Ew, &BX_CPU_C::SHR_EwM, &BX_CPU_C::SHR_EwR, 0, OP_Ew, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_SAR_Ew, &BX_CPU_C::SAR_EwM, &BX_CPU_C::SAR_EwR, 0, OP_Ew, OP_CLReg, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_ROL_Ed, &BX_CPU_C::ROL_EdM, &BX_CPU_C::ROL_EdR, 0, OP_Ed, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_ROR_Ed, &BX_CPU_C::ROR_EdM, &BX_CPU_C::ROR_EdR, 0, OP_Ed, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_RCL_Ed, &BX_CPU_C::RCL_EdM, &BX_CPU_C::RCL_EdR, 0, OP_Ed, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_RCR_Ed, &BX_CPU_C::RCR_EdM, &BX_CPU_C::RCR_EdR, 0, OP_Ed, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_SHL_Ed, &BX_CPU_C::SHL_EdM, &BX_CPU_C::SHL_EdR, 0, OP_Ed, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_SHR_Ed, &BX_CPU_C::SHR_EdM, &BX_CPU_C::SHR_EdR, 0, OP_Ed, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_SAR_Ed, &BX_CPU_C::SAR_EdM, &BX_CPU_C::SAR_EdR, 0, OP_Ed, OP_NONE, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_ROL_Ed, &BX_CPU_C::ROL_EdM, &BX_CPU_C::ROL_EdR, 0, OP_Ed, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_ROR_Ed, &BX_CPU_C::ROR_EdM, &BX_CPU_C::ROR_EdR, 0, OP_Ed, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_RCL_Ed, &BX_CPU_C::RCL_EdM, &BX_CPU_C::RCL_EdR, 0, OP_Ed, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_RCR_Ed, &BX_CPU_C::RCR_EdM, &BX_CPU_C::RCR_EdR, 0, OP_Ed, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_SHL_Ed, &BX_CPU_C::SHL_EdM, &BX_CPU_C::SHL_EdR, 0, OP_Ed, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_SHR_Ed, &BX_CPU_C::SHR_EdM, &BX_CPU_C::SHR_EdR, 0, OP_Ed, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_SAR_Ed, &BX_CPU_C::SAR_EdM, &BX_CPU_C::SAR_EdR, 0, OP_Ed, OP_CLReg, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_ROL_EbIb, &BX_CPU_C::ROL_EbM, &BX_CPU_C::ROL_EbR, 0, OP_Eb, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_ROR_EbIb, &BX_CPU_C::ROR_EbM, &BX_CPU_C::ROR_EbR, 0, OP_Eb, OP_Ib, OP_NONE, OP_NONE, 0)
@@ -949,7 +949,7 @@
bx_define_opcode(BX_IA_PSHUFLW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSHUFLW_VdqWdqIbR, BX_ISA_SSE, OP_Vdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PINSRW_PqEwIb, &BX_CPU_C::PINSRW_PqEwIb, &BX_CPU_C::PINSRW_PqEwIb, BX_ISA_SSE | BX_ISA_3DNOW, OP_Pq, OP_Ew, OP_Ib, OP_NONE, 0)
bx_define_opcode(BX_IA_PEXTRW_GdNqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdNqIb, BX_ISA_SSE | BX_ISA_3DNOW, OP_Gd, OP_Qq, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_SHUFPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SHUFPS_VpsWpsIbR, BX_ISA_SSE, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SHUFPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SHUFPS_VpsWpsIbR, BX_ISA_SSE, OP_Vps, OP_Wps, OP_Ib, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PMOVMSKB_GdNq, &BX_CPU_C::BxError, &BX_CPU_C::PMOVMSKB_GdNq, BX_ISA_SSE | BX_ISA_3DNOW, OP_Gd, OP_Qq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PMINUB_PqQq, &BX_CPU_C::PMINUB_PqQq, &BX_CPU_C::PMINUB_PqQq, BX_ISA_SSE | BX_ISA_3DNOW, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PMAXUB_PqQq, &BX_CPU_C::PMAXUB_PqQq, &BX_CPU_C::PMAXUB_PqQq, BX_ISA_SSE | BX_ISA_3DNOW, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
@@ -998,10 +998,10 @@
bx_define_opcode(BX_IA_SQRTSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::SQRTSS_VssWssR, BX_ISA_SSE, OP_Vss, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_SQRTSD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::SQRTSD_VsdWsdR, BX_ISA_SSE2, OP_Vsd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CMPPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CMPPS_VpsWpsIbR, BX_ISA_SSE, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CMPPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CMPPD_VpdWpdIbR, BX_ISA_SSE2, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CMPSS_VssWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CMPSS_VssWssIbR, BX_ISA_SSE, OP_Vss, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_CMPSD_VsdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CMPSD_VsdWsdIbR, BX_ISA_SSE2, OP_Vsd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CMPPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CMPPS_VpsWpsIbR, BX_ISA_SSE, OP_Vps, OP_Wps, OP_Ib, OP_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CMPPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CMPPD_VpdWpdIbR, BX_ISA_SSE2, OP_Vpd, OP_Wpd, OP_Ib, OP_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CMPSS_VssWssIb, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CMPSS_VssWssIbR, BX_ISA_SSE, OP_Vss, OP_Wss, OP_Ib, OP_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_CMPSD_VsdWsdIb, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CMPSD_VsdWsdIbR, BX_ISA_SSE2, OP_Vsd, OP_Wsd, OP_Ib, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTPS2PD_VpdWps, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTPS2PD_VpdWpsR, BX_ISA_SSE2, OP_Vpd, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTPD2PS_VpsWpd, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTPD2PS_VpsWpdR, BX_ISA_SSE2, OP_Vps, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
@@ -1073,7 +1073,7 @@
bx_define_opcode(BX_IA_MOVNTI_Op32_MdGd, &BX_CPU_C::MOV32_EdGdM, &BX_CPU_C::BxError, BX_ISA_SSE2, OP_Ed, OP_Gd, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PINSRW_VdqEwIb, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::PINSRW_VdqHdqEwIbR, BX_ISA_SSE2, OP_Vdq, OP_Vdq, OP_Ew, OP_Ib, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PEXTRW_GdUdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdUdqIb, BX_ISA_SSE2, OP_Gd, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_SSE)
-bx_define_opcode(BX_IA_SHUFPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SHUFPD_VpdWpdIbR, BX_ISA_SSE2, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
+bx_define_opcode(BX_IA_SHUFPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SHUFPD_VpdWpdIbR, BX_ISA_SSE2, OP_Vpd, OP_Wpd, OP_Ib, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRLW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLW_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRLD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLD_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRLQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLQ_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
@@ -1426,13 +1426,13 @@
bx_define_opcode(BX_IA_NOT_Eq, &BX_CPU_C::NOT_EqM, &BX_CPU_C::NOT_EqR, 0, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_NEG_Eq, &BX_CPU_C::NEG_EqM, &BX_CPU_C::NEG_EqR, 0, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_ROL_Eq, &BX_CPU_C::ROL_EqM, &BX_CPU_C::ROL_EqR, 0, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_ROR_Eq, &BX_CPU_C::ROR_EqM, &BX_CPU_C::ROR_EqR, 0, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_RCL_Eq, &BX_CPU_C::RCL_EqM, &BX_CPU_C::RCL_EqR, 0, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_RCR_Eq, &BX_CPU_C::RCR_EqM, &BX_CPU_C::RCR_EqR, 0, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_SHL_Eq, &BX_CPU_C::SHL_EqM, &BX_CPU_C::SHL_EqR, 0, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_SHR_Eq, &BX_CPU_C::SHR_EqM, &BX_CPU_C::SHR_EqR, 0, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
-bx_define_opcode(BX_IA_SAR_Eq, &BX_CPU_C::SAR_EqM, &BX_CPU_C::SAR_EqR, 0, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_ROL_Eq, &BX_CPU_C::ROL_EqM, &BX_CPU_C::ROL_EqR, 0, OP_Eq, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_ROR_Eq, &BX_CPU_C::ROR_EqM, &BX_CPU_C::ROR_EqR, 0, OP_Eq, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_RCL_Eq, &BX_CPU_C::RCL_EqM, &BX_CPU_C::RCL_EqR, 0, OP_Eq, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_RCR_Eq, &BX_CPU_C::RCR_EqM, &BX_CPU_C::RCR_EqR, 0, OP_Eq, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_SHL_Eq, &BX_CPU_C::SHL_EqM, &BX_CPU_C::SHL_EqR, 0, OP_Eq, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_SHR_Eq, &BX_CPU_C::SHR_EqM, &BX_CPU_C::SHR_EqR, 0, OP_Eq, OP_CLReg, OP_NONE, OP_NONE, 0)
+bx_define_opcode(BX_IA_SAR_Eq, &BX_CPU_C::SAR_EqM, &BX_CPU_C::SAR_EqR, 0, OP_Eq, OP_CLReg, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_ROL_EqIb, &BX_CPU_C::ROL_EqM, &BX_CPU_C::ROL_EqR, 0, OP_Eq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_ROR_EqIb, &BX_CPU_C::ROR_EqM, &BX_CPU_C::ROR_EqR, 0, OP_Eq, OP_Ib, OP_NONE, OP_NONE, 0)
@@ -1679,7 +1679,7 @@
bx_define_opcode(BX_IA_VHADDPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHADDPS_VpsHpsWpsR, BX_ISA_AVX, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VHSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPD_VpdHpdWpdR, BX_ISA_AVX, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VHSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VHSUBPS_VpsHpsWpsR, BX_ISA_AVX, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_VSHUFPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPS_VpsHpsWpsIbR, BX_ISA_AVX, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_VSHUFPS_VpsHpsWpsIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPS_VpsHpsWpsIbR, BX_ISA_AVX, OP_Vps, OP_Hps, OP_Wps, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VSHUFPD_VpdHpdWpdIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VSHUFPD_VpdHpdWpdIbR, BX_ISA_AVX, OP_Vpd, OP_Hpd, OP_Wpd, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VADDSUBPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPD_VpdHpdWpdR, BX_ISA_AVX, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VADDSUBPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VADDSUBPS_VpsHpsWpsR, BX_ISA_AVX, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_AVX)
Modified: trunk/bochs/disasm/dis_tables.inc
===================================================================
--- trunk/bochs/disasm/dis_tables.inc 2013-10-06 18:10:58 UTC (rev 11856)
+++ trunk/bochs/disasm/dis_tables.inc 2013-10-06 18:37:56 UTC (rev 11857)
@@ -853,8 +853,8 @@
/* A1 */ { 0, &Ia_movw_Ow_AX },
/* A4 */ { 0, &Ia_movsb_Yb_Xb },
/* A5 */ { 0, &Ia_movsw_Yw_Xw },
- /* A6 */ { 0, &Ia_cmpsb_Yb_Xb },
- /* A7 */ { 0, &Ia_cmpsw_Yw_Xw },
+ /* A6 */ { 0, &Ia_cmpsb_Xb_Yb },
+ /* A7 */ { 0, &Ia_cmpsw_Xw_Yw },
/* A8 */ { 0, &Ia_testb_AL_Ib },
/* A9 */ { 0, &Ia_testw_AX_Iw },
/* AA */ { 0, &Ia_stosb_Yb_AL },
@@ -1374,8 +1374,8 @@
/* A1 */ { 0, &Ia_movl_Od_EAX },
/* A4 */ { 0, &Ia_movsb_Yb_Xb },
/* A5 */ { 0, &Ia_movsl_Yd_Xd },
- /* A6 */ { 0, &Ia_cmpsb_Yb_Xb },
- /* A7 */ { 0, &Ia_cmpsl_Yd_Xd },
+ /* A6 */ { 0, &Ia_cmpsb_Xb_Yb },
+ /* A7 */ { 0, &Ia_cmpsl_Xd_Yd },
/* A8 */ { 0, &Ia_testb_AL_Ib },
/* A9 */ { 0, &Ia_testl_EAX_Id },
/* AA */ { 0, &Ia_stosb_Yb_AL },
@@ -1895,8 +1895,8 @@
/* A1 */ { 0, &Ia_movw_Ow_AX },
/* A4 */ { 0, &Ia_movsb_Yb_Xb },
/* A5 */ { 0, &Ia_movsw_Yw_Xw },
- /* A6 */ { 0, &Ia_cmpsb_Yb_Xb },
- /* A7 */ { 0, &Ia_cmpsw_Yw_Xw },
+ /* A6 */ { 0, &Ia_cmpsb_Xb_Yb },
+ /* A7 */ { 0, &Ia_cmpsw_Xw_Yw },
/* A8 */ { 0, &Ia_testb_AL_Ib },
/* A9 */ { 0, &Ia_testw_AX_Iw },
/* AA */ { 0, &Ia_stosb_Yb_AL },
@@ -2413,8 +2413,8 @@
/* A1 */ { 0, &Ia_movl_Od_EAX },
/* A4 */ { 0, &Ia_movsb_Yb_Xb },
/* A5 */ { 0, &Ia_movsl_Yd_Xd },
- /* A6 */ { 0, &Ia_cmpsb_Yb_Xb },
- /* A7 */ { 0, &Ia_cmpsl_Yd_Xd },
+ /* A6 */ { 0, &Ia_cmpsb_Xb_Yb },
+ /* A7 */ { 0, &Ia_cmpsl_Xd_Yd },
/* A8 */ { 0, &Ia_testb_AL_Ib },
/* A9 */ { 0, &Ia_testl_EAX_Id },
/* AA */ { 0, &Ia_stosb_Yb_AL },
@@ -2931,8 +2931,8 @@
/* A1 */ { 0, &Ia_movq_Oq_RAX },
/* A4 */ { 0, &Ia_movsb_Yb_Xb },
/* A5 */ { 0, &Ia_movsq_Yq_Xq },
- /* A6 */ { 0, &Ia_cmpsb_Yb_Xb },
- /* A7 */ { 0, &Ia_cmpsq_Yq_Xq },
+ /* A6 */ { 0, &Ia_cmpsb_Xb_Yb },
+ /* A7 */ { 0, &Ia_cmpsq_Xq_Yq },
/* A8 */ { 0, &Ia_testb_AL_Ib },
/* A9 */ { 0, &Ia_testq_RAX_sId },
/* AA */ { 0, &Ia_stosb_Yb_AL },
Modified: trunk/bochs/disasm/opcodes.inc
===================================================================
--- trunk/bochs/disasm/opcodes.inc 2013-10-06 18:10:58 UTC (rev 11856)
+++ trunk/bochs/disasm/opcodes.inc 2013-10-06 18:37:56 UTC (rev 11857)
@@ -235,12 +235,12 @@
Ia_cmpq_Eq_sId = { "cmp", "cmpq", Eq, sIdq, XX, XX, 0 },
Ia_cmpq_Gq_Eq = { "cmp", "cmpq", Gq, Eq, XX, XX, 0 },
Ia_cmpq_RAX_sId = { "cmp", "cmpq", RAX_Reg, sIdq, XX, XX, 0 },
-Ia_cmpsb_Yb_Xb = { "cmpsb", "cmpsb", Yb, Xb, XX, XX, 0 },
+Ia_cmpsb_Xb_Yb = { "cmpsb", "cmpsb", Xb, Yb, XX, XX, 0 },
Ia_cmpsd_Vsd_Wsd_Ib = { "cmpsd", "cmpsd", Vsd, Wsd, Ib, XX, IA_SSE2 },
-Ia_cmpsl_Yd_Xd = { "cmpsd", "cmpsl", Yd, Xd, XX, XX, 0 },
-Ia_cmpsq_Yq_Xq = { "cmpsq", "cmpsq", Yq, Xq, XX, XX, 0 },
+Ia_cmpsl_Xd_Yd = { "cmpsd", "cmpsl", Xd, Yd, XX, XX, 0 },
+Ia_cmpsq_Xq_Yq = { "cmpsq", "cmpsq", Xq, Yq, XX, XX, 0 },
Ia_cmpss_Vss_Wss_Ib = { "cmpss", "cmpss", Vss, Wss, Ib, XX, IA_SSE },
-Ia_cmpsw_Yw_Xw = { "cmpsw", "cmpsw", Yw, Xw, XX, XX, 0 },
+Ia_cmpsw_Xw_Yw = { "cmpsw", "cmpsw", Xw, Yw, XX, XX, 0 },
Ia_cmpw_AX_Iw = { "cmp", "cmpw", AX_Reg, Iw, XX, XX, 0 },
Ia_cmpw_Ew_Gw = { "cmp", "cmpw", Ew, Gw, XX, XX, 0 },
Ia_cmpw_Ew_Iw = { "cmp", "cmpw", Ew, Iw, XX, XX, 0 },
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