Re: [Bochs-developers] CPU reset and SMBASE

[Gleb N. <gl...@re...>]

On Thu, Nov 20, 2008 at 08:31:22PM +0200, Stanislav wrote:
> Do not forget about delivering of INIT IPI using local APIC message.
> Currently the INIT would only reset the local APIC on the CPU (deliver INIT
> to local APIC only).
> Should I change it to deliver BX_RESET_SOFTWARE to the destination CPU ?
> 
INIT IPI should configure CPU to INIT state as described in Intel docs.

> Thanks,
> Stanislav
> 
> 
> -----Original Message-----
> From: Sebastian Herbszt [mailto:he...@gm...] 
> Sent: Wednesday, November 19, 2008 10:26 PM
> To: Gleb Natapov; Stanislav
> Cc: boc...@li...
> Subject: Re: [Bochs-developers] CPU reset and SMBASE
> 
> Gleb Natapov wrote:
> > On Tue, Nov 18, 2008 at 08:58:31PM +0200, Stanislav wrote:
> >> Just to make sure - SOFT RESET is INIT according to Intel manual:
> >> 
> >> pentium processor manual vol3, 19.3.1.11.3 'Initialization Reset (INIT)':
> >> "INIT is a software reset, and is delivered as a bus message.  INIT
> hasthe
> >> same effect on the Local APIC as the power-up Reset, except that theAPIC
> ID
> >> and the Arb ID registers are not affected."
> >> 
> >> I will tune CPU::reset method to keep register values that should not
> change
> >> on INIT.
> >> You, guys, have to figure our when INIT should be called and when HARD
> >> RESET.
> >> 
> > I was wrong about triple fault triggering RESET. According to piix3
> > documentation it triggers INIT if shut down special cycle is detected.
> > Keyboard controller should trigger RESET, but I haven't found this
> > written somewhere. Also kbd reset does not work on some modern boards.
> > PIIX4 chipset has additional way to trigger INIT from software by
> > writing 1 to bit 0 of port 92h. S3 should configure HW to power up state
> > (except memory of cause) so we should do hard reset there.
> 
> There is also a section and a diagram on resets in the 440fx PMC manual
> (4.5.3 SYSTEM RESET):
> 
> "The PMC generates a soft reset in response to a shutdown bus cycle on the
> CPU bus.
> External logic is required to combine the PMC soft reset with the keyboard
> controller
> and I/O port 92 soft reset generation."
> 
> "There are two sources of hard reset in the system:
> *  During Power-up, PWROK asserted 1 ms after the system power has
> stabilized
> *  I/O write to the PMC Turbo/Reset Control Register (configuration offset
> 93h)"
> 
> "The PMC should not be used to generate a hard reset in a system designed
> with PIIX3.
> Instead use the PIIX3 to generate the hard reset."
> 
> "There are 4 sources of soft reset in the system:
> *  CPU shutdown bus cycle
> *  I/O write to the keyboard controller
> *  I/O write to port 92h
> *  I/O write to the PMC Turbo/Reset Control Register"
> 
> - Sebastian

--
			Gleb.