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[Bochs-cvs] CVS: bochs/cpu access.cc, 1.67, 1.68 cpuid.cc, 1.43, 1.44 xmm.h, 1.22, 1.23
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From: Stanislav S. <ssh...@us...> - 2007-07-15 19:03:45
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Update of /cvsroot/bochs/bochs/cpu In directory sc8-pr-cvs3.sourceforge.net:/tmp/cvs-serv26198/cpu Modified Files: access.cc cpuid.cc xmm.h Log Message: Misaligned SSE support Index: access.cc =================================================================== RCS file: /cvsroot/bochs/bochs/cpu/access.cc,v retrieving revision 1.67 retrieving revision 1.68 diff -u -d -r1.67 -r1.68 --- access.cc 9 Apr 2007 21:55:07 -0000 1.67 +++ access.cc 15 Jul 2007 19:03:39 -0000 1.68 @@ -45,8 +45,8 @@ if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) { // do canonical checks if (!IsCanonical(offset)) { - BX_ERROR(("Canonical Failure 0x%08x:%08x", GET32H(offset), GET32L(offset))); - exception(BX_GP_EXCEPTION, 0, 0); + BX_ERROR(("write_virtual_checks(): canonical Failure 0x%08x:%08x", GET32H(offset), GET32L(offset))); + exception(int_number(seg), 0, 0); } seg->cache.valid |= SegAccessWOK; return; @@ -137,8 +137,8 @@ if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) { // do canonical checks if (!IsCanonical(offset)) { - BX_ERROR(("Canonical Failure 0x%08x:%08x", GET32H(offset), GET32L(offset))); - exception(BX_GP_EXCEPTION, 0, 0); + BX_ERROR(("read_virtual_checks(): canonical Failure 0x%08x:%08x", GET32H(offset), GET32L(offset))); + exception(int_number(seg), 0, 0); } seg->cache.valid |= SegAccessROK; return; @@ -967,7 +967,11 @@ BX_CPU_C::read_virtual_dqword_aligned(unsigned s, bx_address offset, Bit8u *data) { // If double quadword access is unaligned, #GP(0). - if (offset & 0xf) { + if ((offset & 0xf) +#if BX_SUPPORT_MISALIGNED_SSE + && !MXCSR.get_misaligned_exception_mask() +#endif + ) { BX_DEBUG(("read_virtual_dqword_aligned: access not aligned to 16-byte")); exception(BX_GP_EXCEPTION, 0, 0); } @@ -989,7 +993,11 @@ BX_CPU_C::write_virtual_dqword_aligned(unsigned s, bx_address offset, Bit8u *data) { // If double quadword access is unaligned, #GP(0). - if (offset & 0xf) { + if ((offset & 0xf) +#if BX_SUPPORT_MISALIGNED_SSE + && !MXCSR.get_misaligned_exception_mask() +#endif + ) { BX_DEBUG(("write_virtual_dqword_aligned: access not aligned to 16-byte")); exception(BX_GP_EXCEPTION, 0, 0); } Index: cpuid.cc =================================================================== RCS file: /cvsroot/bochs/bochs/cpu/cpuid.cc,v retrieving revision 1.43 retrieving revision 1.44 diff -u -d -r1.43 -r1.44 --- cpuid.cc 19 Apr 2007 16:12:18 -0000 1.43 +++ cpuid.cc 15 Jul 2007 19:03:39 -0000 1.44 @@ -368,9 +368,7 @@ break; case 0x80000001: - // long mode supported. - features = get_std_cpuid_features (); - RAX = features; + RAX = get_cpu_version_information(); // Many of the bits in EDX are the same as EAX [*] // [*] [0:0] FPU on chip // [*] [1:1] VME: Virtual-8086 Mode enhancements @@ -403,6 +401,7 @@ // [29:29] Long Mode // [30:30] AMD 3DNow! Extensions // [31:31] AMD 3DNow! Instructions + features = get_std_cpuid_features(); features = features & 0x0183F3FF; RDX = features | (1 << 29) | (1 << 27) | (1 << 25) | @@ -411,8 +410,20 @@ // RCX: // [0:0] LAHF/SAHF available in 64-bit mode - // [1:31] Reserved + // [1:1] AMD CmpLegacy + // [2:2] AMD Secure Virtual Machine Technology + // [3:3] Extended APIC Space + // [4:4] Alternative CR8 (treat lock mov cr0 as mov cr8) + // [5:5] LZCNT support + // [6:6] SSE4A support + // [7:7] Misaligned SSE support + // [8:8] 3DNow! prefetch support + // [9:9] OS visible workarounds + // [10:31] Reserved RCX = 1; +#if BX_SUPPORT_MISALIGNED_SSE + RCX |= (1<<7); +#endif break; // Processor Brand String, use the value given Index: xmm.h =================================================================== RCS file: /cvsroot/bochs/bochs/cpu/xmm.h,v retrieving revision 1.22 retrieving revision 1.23 diff -u -d -r1.22 -r1.23 --- xmm.h 19 Apr 2007 16:12:21 -0000 1.22 +++ xmm.h 15 Jul 2007 19:03:39 -0000 1.23 @@ -109,7 +109,7 @@ /* 31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16 * ==|==|=====|==|==|==|==|==|==|==|==|==|==|==|== (reserved) - * 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0 + * 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0| 0|MM| 0 * * 15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0 * ==|==|=====|==|==|==|==|==|==|==|==|==|==|==|== @@ -134,13 +134,16 @@ * PM 12 Precision Exception Mask 1 * RC 13-14 Floating-Point Rounding Control 00 * FZ 15 Flush-to-Zero for Masked Underflow 0 + * RZ 16 Reserved 0 + * MM 17 Misaligned Exceptuion Mask 0 */ -#define MXCSR_DAZ 0x00000040 -#define MXCSR_EXCEPTIONS 0x0000003F -#define MXCSR_MASKED_EXCEPTIONS 0x00001F80 -#define MXCSR_ROUNDING_CONTROL 0x00006000 -#define MXCSR_FLUSH_MASKED_UNDERFLOW 0x00008000 +#define MXCSR_EXCEPTIONS 0x0000003F +#define MXCSR_DAZ 0x00000040 +#define MXCSR_MASKED_EXCEPTIONS 0x00001F80 +#define MXCSR_ROUNDING_CONTROL 0x00006000 +#define MXCSR_FLUSH_MASKED_UNDERFLOW 0x00008000 +#define MXCSR_MISALIGNED_EXCEPTION_MASK 0x00020000 #define MXCSR_IE 0x00000001 #define MXCSR_DE 0x00000002 @@ -174,6 +177,7 @@ IMPLEMENT_MXCSR_ACCESSOR(DAZ, MXCSR_DAZ, 6); IMPLEMENT_MXCSR_ACCESSOR(rounding_mode, MXCSR_ROUNDING_CONTROL, 13); IMPLEMENT_MXCSR_ACCESSOR(flush_masked_underflow, MXCSR_FLUSH_MASKED_UNDERFLOW, 15); + IMPLEMENT_MXCSR_ACCESSOR(misaligned_exception_mask, MXCSR_MISALIGNED_EXCEPTION_MASK, 17); IMPLEMENT_MXCSR_ACCESSOR(IE, MXCSR_IE, 0); IMPLEMENT_MXCSR_ACCESSOR(DE, MXCSR_DE, 1); @@ -195,11 +199,10 @@ }; -#if BX_SUPPORT_DAZ -#define MXCSR_MASK 0x0000FFFF /* reset reserved bits */ -#else -#define MXCSR_MASK 0x0000FFBF /* reset reserved bits */ -#endif +/* reset reserved bits */ +#define MXCSR_MASK (0x0000FFBF | \ + (BX_SUPPORT_DAZ ? MXCSR_DAZ : 0) | \ + (BX_SUPPORT_MISALIGNED_SSE ? MXCSR_MISALIGNED_EXCEPTION_MASK : 0)) #if defined(NEED_CPU_REG_SHORTCUTS) #define MXCSR (BX_CPU_THIS_PTR mxcsr) |