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[Bochs-cvs] CVS: bochs/cpu cpu.cc,1.89,1.90 cpu.h,1.181,1.182 ctrl_xfer32.cc,1.30,1.31 ctrl_xfer64.cc,1.25,1.26 extdb.cc,1.12,1.13 paging.cc,1.48,1.49
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From: Stanislav S. <ssh...@us...> - 2004-10-29 21:16:02
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Update of /cvsroot/bochs/bochs/cpu In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv20603/cpu Modified Files: cpu.cc cpu.h ctrl_xfer32.cc ctrl_xfer64.cc extdb.cc paging.cc Log Message: Fixed compilation prroblem reported in bug [ bochs-Bugs-913418 ] compiler errors with --enable-external-debugger option Remove code duplication Index: cpu.cc =================================================================== RCS file: /cvsroot/bochs/bochs/cpu/cpu.cc,v retrieving revision 1.89 retrieving revision 1.90 diff -u -d -r1.89 -r1.90 --- cpu.cc 16 Oct 2004 19:34:17 -0000 1.89 +++ cpu.cc 29 Oct 2004 21:15:47 -0000 1.90 @@ -750,8 +750,7 @@ BX_PANIC(("prefetch: running in bogus memory")); } else { - BX_PANIC(("prefetch: getHostMemAddr vetoed direct read, pAddr=0x%x.", - pAddr)); + BX_PANIC(("prefetch: getHostMemAddr vetoed direct read, pAddr=0x%x.", pAddr)); } } Index: cpu.h =================================================================== RCS file: /cvsroot/bochs/bochs/cpu/cpu.h,v retrieving revision 1.181 retrieving revision 1.182 diff -u -d -r1.181 -r1.182 --- cpu.h 21 Oct 2004 18:20:32 -0000 1.181 +++ cpu.h 29 Oct 2004 21:15:47 -0000 1.182 @@ -738,8 +738,6 @@ } bx_segment_reg_t; typedef void * (*BxVoidFPtr_t)(void); -class BX_CPU_C; - class bxInstruction_c { public: @@ -1475,7 +1473,11 @@ // constructors & destructors... BX_CPU_C(); - ~BX_CPU_C(void); +#if BX_EXTERNAL_DEBUGGER + virtual ~BX_CPU_C(); +#else + ~BX_CPU_C(); +#endif void init (BX_MEM_C *addrspace); // prototypes for CPU instructions... Index: ctrl_xfer32.cc =================================================================== RCS file: /cvsroot/bochs/bochs/cpu/ctrl_xfer32.cc,v retrieving revision 1.30 retrieving revision 1.31 diff -u -d -r1.30 -r1.31 --- ctrl_xfer32.cc 19 Oct 2004 20:05:07 -0000 1.30 +++ ctrl_xfer32.cc 29 Oct 2004 21:15:48 -0000 1.31 @@ -62,7 +62,7 @@ /* ??? #SS(0) -or #GP(0) */ } - access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 0, + access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP, 4, CPL==3, BX_READ, &return_EIP); if (protected_mode() && @@ -120,7 +120,7 @@ /* ??? #SS(0) -or #GP(0) */ } - access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP + 0, + access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_ESP, 4, CPL==3, BX_READ, &return_EIP); if ( return_EIP > BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled ) { Index: ctrl_xfer64.cc =================================================================== RCS file: /cvsroot/bochs/bochs/cpu/ctrl_xfer64.cc,v retrieving revision 1.25 retrieving revision 1.26 diff -u -d -r1.25 -r1.26 --- ctrl_xfer64.cc 19 Oct 2004 20:05:07 -0000 1.25 +++ ctrl_xfer64.cc 29 Oct 2004 21:15:48 -0000 1.26 @@ -56,7 +56,7 @@ // /* ??? #SS(0) -or #GP(0) */ // } - access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + 0, + access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP, 8, CPL==3, BX_READ, &return_RIP); /* Pentium book says imm16 is number of words ??? */ @@ -90,7 +90,7 @@ // /* ??? #SS(0) -or #GP(0) */ // } - access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP + 0, + access_linear(BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.base + temp_RSP, 8, CPL==3, BX_READ, &return_RIP); RIP = return_RIP; Index: extdb.cc =================================================================== RCS file: /cvsroot/bochs/bochs/cpu/extdb.cc,v retrieving revision 1.12 retrieving revision 1.13 diff -u -d -r1.12 -r1.13 --- extdb.cc 26 Feb 2003 02:35:11 -0000 1.12 +++ extdb.cc 29 Oct 2004 21:15:48 -0000 1.13 @@ -2,7 +2,7 @@ #ifdef WIN32 // windows.h included in bochs.h #else -//# error "extdb.cc only supported in win32 environment" +# error "extdb.cc only supported in win32 environment" #endif TRegs regs; Index: paging.cc =================================================================== RCS file: /cvsroot/bochs/bochs/cpu/paging.cc,v retrieving revision 1.48 retrieving revision 1.49 diff -u -d -r1.48 -r1.49 --- paging.cc 21 Oct 2004 18:20:34 -0000 1.48 +++ paging.cc 29 Oct 2004 21:15:48 -0000 1.49 @@ -604,7 +604,6 @@ bx_address lpf; Bit32u ppf, poffset, error_code, paddress; Bit32u pde, pde_addr; - bx_bool isWrite; Bit32u accessBits, combined_access; unsigned priv_index; #if BX_USE_TLB @@ -614,15 +613,14 @@ InstrTLB_Increment(tlbLookups); InstrTLB_Stats(); + bx_bool isWrite = (rw>=BX_WRITE); // write or r-m-w + #if BX_SupportPAE if (BX_CPU_THIS_PTR cr4.get_PAE()) { Bit32u pdp, pdp_addr; lpf = laddr & BX_CONST64(0xfffffffffffff000); // linear page frame poffset = laddr & 0x00000fff; // physical offset - isWrite = (rw>=BX_WRITE); // write or r-m-w - - //BX_DEBUG (("poffset: %-8x laddr: %-8x lpf: %-8x",poffset,laddr,lpf)); #if BX_USE_TLB TLB_index = BX_TLB_INDEX_OF(lpf); @@ -658,33 +656,33 @@ // PML4 Entry NOT present error_code = 0x00000000; // RSVD=0, P=0 goto page_fault_not_present; - } + } if ( !(pml4 & 0x20) ) { pml4 |= 0x20; BX_CPU_THIS_PTR mem->writePhysicalPage(this, pml4_addr, 4, &pml4); - } + } // Get PDP entry pdp_addr = (pml4 & 0xfffff000) | ((laddr & BX_CONST64(0x0000007fc0000000)) >> 27); - } + } else #endif - { + { pdp_addr = BX_CPU_THIS_PTR cr3_masked | ((laddr & 0xc0000000) >> 27); - } + } BX_CPU_THIS_PTR mem->readPhysicalPage(this, pdp_addr, 4, &pdp); if ( !(pdp & 0x01) ) { // PDP Entry NOT present error_code = 0x00000000; // RSVD=0, P=0 goto page_fault_not_present; - } + } if ( !(pdp & 0x20) ) { pdp |= 0x20; BX_CPU_THIS_PTR mem->writePhysicalPage(this, pdp_addr, 4, &pdp); - } + } // Get page dir entry pde_addr = (pdp & 0xfffff000) | @@ -695,7 +693,7 @@ // Page Directory Entry NOT present error_code = 0x00000000; // RSVD=0, P=0 goto page_fault_not_present; - } + } #if BX_SUPPORT_4MEG_PAGES // (KPL) Weird. I would think the processor would consult CR.PSE? @@ -724,18 +722,18 @@ if (!priv_check[priv_index]) { error_code = 0x00000001; // RSVD=0, P=1 goto page_fault_access; - } + } // Update PDE if A/D bits if needed. if ( ((pde & 0x20)==0) || (isWrite && ((pde&0x40)==0)) ) { pde |= (0x20 | (isWrite<<6)); // Update A and possibly D bits BX_CPU_THIS_PTR mem->writePhysicalPage(this, pde_addr, 4, &pde); - } } + } else #endif - { // 4k pages. + { // 4k pages. Bit32u pte, pte_addr; // Get page table entry @@ -756,7 +754,7 @@ // Page Table Entry NOT present error_code = 0x00000000; // RSVD=0, P=0 goto page_fault_not_present; - } + } priv_index = #if BX_CPU_LEVEL >= 4 @@ -769,21 +767,21 @@ if (!priv_check[priv_index]) { error_code = 0x00000001; // RSVD=0, P=1 goto page_fault_access; - } + } // Update PDE A bit if needed. if ( (pde & 0x20)==0 ) { pde |= 0x20; // Update A bit. BX_CPU_THIS_PTR mem->writePhysicalPage(this, pde_addr, 4, &pde); - } + } // Update PTE A/D bits if needed. - if ( ((pte & 0x20)==0) || - (isWrite && ((pte&0x40)==0)) ) { + if (((pte & 0x20)==0) || (isWrite && ((pte&0x40)==0))) + { pte |= (0x20 | (isWrite<<6)); // Update A and possibly D bits BX_CPU_THIS_PTR mem->writePhysicalPage(this, pte_addr, 4, &pte); - } } + } // Calculate physical memory address and fill in TLB cache entry paddress = ppf | poffset; @@ -825,7 +823,6 @@ lpf = laddr & 0xfffff000; // linear page frame poffset = laddr & 0x00000fff; // physical offset - isWrite = (rw>=BX_WRITE); // write or r-m-w #if BX_USE_TLB TLB_index = BX_TLB_INDEX_OF(lpf); @@ -854,7 +851,7 @@ // Page Directory Entry NOT present error_code = 0x00000000; // RSVD=0, P=0 goto page_fault_not_present; - } + } #if BX_SUPPORT_4MEG_PAGES if ((pde & 0x80) && (BX_CPU_THIS_PTR cr4.get_PSE())) { @@ -885,20 +882,18 @@ if (!priv_check[priv_index]) { error_code = 0x00000001; // RSVD=0, P=1 goto page_fault_access; - } + } // Update PDE if A/D bits if needed. - if ( ((pde & 0x20)==0) || - (isWrite && ((pde&0x40)==0)) ) { + if (((pde & 0x20)==0) || (isWrite && ((pde&0x40)==0))) { pde |= (0x20 | (isWrite<<6)); // Update A and possibly D bits BX_CPU_THIS_PTR mem->writePhysicalPage(this, pde_addr, 4, &pde); - } } - + } // Else normal 4Kbyte page... else #endif - { + { Bit32u pte, pte_addr; #if (BX_CPU_LEVEL < 6) @@ -906,7 +901,7 @@ if ( !(pde & 0x20) ) { pde |= 0x20; BX_CPU_THIS_PTR mem->writePhysicalPage(this, pde_addr, 4, &pde); - } + } #endif // Get page table entry @@ -934,7 +929,7 @@ // Page Table Entry NOT present error_code = 0x00000000; // RSVD=0, P=0 goto page_fault_not_present; - } + } priv_index = #if BX_CPU_LEVEL >= 4 @@ -947,24 +942,23 @@ if (!priv_check[priv_index]) { error_code = 0x00000001; // RSVD=0, P=1 goto page_fault_access; - } + } #if (BX_CPU_LEVEL >= 6) // update PDE if A bit was not set before if ( !(pde & 0x20) ) { pde |= 0x20; BX_CPU_THIS_PTR mem->writePhysicalPage(this, pde_addr, 4, &pde); - } + } #endif // Update PTE if A/D bits if needed. - if ( ((pte & 0x20)==0) || - (isWrite && ((pte&0x40)==0)) ) { + if (((pte & 0x20)==0) || (isWrite && ((pte&0x40)==0))) + { pte |= (0x20 | (isWrite<<6)); // Update A and possibly D bits BX_CPU_THIS_PTR mem->writePhysicalPage(this, pte_addr, 4, &pte); - } } - + } // Calculate physical memory address and fill in TLB cache entry paddress = ppf | poffset; @@ -1115,9 +1109,6 @@ BX_CPU_C::access_linear(bx_address laddr, unsigned length, unsigned pl, unsigned rw, void *data) { - Bit32u pageOffset; - unsigned xlate_rw; - #if BX_X86_DEBUGGER if ( BX_CPU_THIS_PTR dr7 & 0x000000ff ) { @@ -1137,15 +1128,9 @@ } #endif - if (rw==BX_RW) { - xlate_rw = BX_RW; - rw = BX_READ; - } - else { - xlate_rw = rw; - } - - pageOffset = laddr & 0x00000fff; + Bit32u pageOffset = laddr & 0x00000fff; + unsigned xlate_rw = rw; + if (rw==BX_RW) rw = BX_READ; if (BX_CPU_THIS_PTR cr0.pg) { /* check for reference across multiple pages */ @@ -1239,7 +1224,6 @@ return; } } - else { // Paging off. if ( (pageOffset + length) <= 4096 ) { @@ -1388,7 +1372,6 @@ } #endif } - return; } } |