CVS: blob/include/blob/arch ra_alpha.h,1.2,1.3

[Stefan E. <se...@us...>]

Update of /cvsroot/blob/blob/include/blob/arch
In directory sc8-pr-cvs1:/tmp/cvs-serv19908

Modified Files:
	ra_alpha.h 
Log Message:
Use defines from pxa-regs.h for better readability.
Define IRQ GPIOs as input (first shot).


Index: ra_alpha.h
===================================================================
RCS file: /cvsroot/blob/blob/include/blob/arch/ra_alpha.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- ra_alpha.h	10 Nov 2003 20:54:25 -0000	1.2
+++ ra_alpha.h	11 Nov 2003 12:40:55 -0000	1.3
@@ -73,41 +73,37 @@
 /* the size (in kbytes) to which the compressed ramdisk expands */
 #define RAMDISK_SIZE		(4 * 1024)
 
-#define MDREFR_VALUE	0x0009f018
-#define MDCNFG_VALUE	0x000019c9
+#if 1 /* Full Speed */
+// #define MDREFR_VALUE	0x0009f018
+// #define MDCNFG_VALUE	0x000019c9
+# define MDCNFG_VALUE	( MDCNFG_DE0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | \
+						  MDCNFG_DNB0 | MDCNFG_DTC0(1) )
+# define MDREFR_VALUE	( MDREFR_DRI(24) | MDREFR_E0PIN | MDREFR_K0RUN | \
+# 						  MDREFR_K0DB2 | MDREFR_E1PIN | MDREFR_K1RUN | \
+# 						  MDREFR_K2DB2 )
 #define MDMRS_VALUE		0x00020002
-/* L=27, M=4, N=1 */
-#define CCCR_VALUE		0x00000161
-
-#if 0
-#define MDREFR_VAL          0x00018018
-#define MDCNFG_VAL          0x00001AC9
-#define MDMRS_VAL           0x00000000
-#define MSC0_VAL            0x23F223F2
-#define MSC1_VAL            0x3FF1A441
-#define MSC2_VAL            0x7FF17FF1
-#define MECR_VAL            0x00000000
-#define MCMEM0_VAL          0x00010504
-#define MCMEM1_VAL          0x00010504
-#define MCATT0_VAL          0x00010504
-#define MCATT1_VAL          0x00010504
-#define MCIO0_VAL           0x00004715
-#define MCIO1_VAL           0x00004715
+#define CCCR_VALUE		( CCCR_L(27) | CCCR_M(4) | CCCR_N(1) )
+#else /* SDRAM at half speed */
+# define MDCNFG_VALUE	( MDCNFG_DE0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | \
+						  MDCNFG_DNB0 | MDCNFG_DTC0(1) )
+# define MDREFR_VALUE	( MDREFR_DRI(24) | MDREFR_E0PIN | MDREFR_K0RUN | \
+# 						  MDREFR_K0DB2 | MDREFR_E1PIN | MDREFR_K1RUN | \
+# 						  MDREFR_K1DB2 | MDREFR_K2DB2 )
+# define MDMRS_VALUE	0x00020002
 #endif
 
-
 /* GPIO configuration */
 #define GPIO0_VALUE		GPIO_OUT_LO
 #define GPIO1_VALUE		GPIO_OUT_LO
 #define GPIO2_VALUE		GPIO_OUT_LO
-#define GPIO3_VALUE		GPIO_INPUT						/* eth_wakeup			*/
-#define GPIO4_VALUE		GPIO_INPUT						/* bank_switch_int		*/
-#define GPIO5_VALUE		GPIO_INPUT						/* eth_link_status		*/
+#define GPIO3_VALUE		GPIO_INPUT						/* USB IRQ */
+#define GPIO4_VALUE		GPIO_INPUT						/* LAN IRQ (neg) */
+#define GPIO5_VALUE		GPIO_INPUT						/* CF IRQ (neg) */
 #define GPIO6_VALUE		GPIO_OUT_LO
-#define GPIO7_VALUE		GPIO_OUT_LO						/* cpld_clk				*/
+#define GPIO7_VALUE		GPIO_OUT_LO						
 #define GPIO8_VALUE		GPIO_OUT_LO
-#define GPIO9_VALUE		GPIO_INPUT						/* eth_int				*/
-#define GPIO10_VALUE	GPIO_OUT_HI						/* eth_reset			*/
+#define GPIO9_VALUE		GPIO_OUT_LO
+#define GPIO10_VALUE	GPIO_OUT_LO
 #define GPIO11_VALUE	GPIO_OUT_LO
 #define GPIO12_VALUE	GPIO_OUT_LO						/* watchdog_strobe		*/
 #define GPIO13_VALUE	GPIO_INPUT						/* cpld_hw_reset		*/
@@ -122,7 +118,7 @@
 #define GPIO22_VALUE	GPIO_OUT_LO
 #define GPIO23_VALUE	GPIO_OUT_LO
 #define GPIO24_VALUE	GPIO_OUT_LO
-#define GPIO25_VALUE	GPIO_OUT_HI						/* LED [debug]			*/
+#define GPIO25_VALUE	GPIO_OUT_LO
 #define GPIO26_VALUE	GPIO_OUT_LO
 #define GPIO27_VALUE	GPIO_OUT_LO
 #define GPIO28_VALUE	GPIO_OUT_LO