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From: <cv...@ce...> - 2006-07-09 12:19:54
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-dyngen-ops.cpp Log Message: Some minor optimizations: xchg (unused), movdqa in sse2 code. |
From: <cv...@ce...> - 2006-07-09 12:15:55
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/jit by gbeauche Modified Files: basic-dyngen-ops.cpp basic-dyngen.cpp basic-dyngen.hpp dyngen-exec.h Log Message: Remove use of global register A0 (now aliased to T0). This makes it possible to cache the CPU context pointer to a register and thus rendering generated code CPU context independent. Not useful to SheepShaver, but it is for another project for threads emulation on plain x86-32. Note: AltiVec performance may drop a little on x86 but this will be restored (and even improved) in the future. |
From: <cv...@ce...> - 2006-07-09 12:15:54
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-dyngen-ops.cpp ppc-dyngen.cpp ppc-dyngen.hpp ppc-translate.cpp Log Message: Remove use of global register A0 (now aliased to T0). This makes it possible to cache the CPU context pointer to a register and thus rendering generated code CPU context independent. Not useful to SheepShaver, but it is for another project for threads emulation on plain x86-32. Note: AltiVec performance may drop a little on x86 but this will be restored (and even improved) in the future. |
From: <cv...@ce...> - 2006-07-09 12:15:54
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu by gbeauche Modified Files: sheepshaver_glue.cpp Log Message: Remove use of global register A0 (now aliased to T0). This makes it possible to cache the CPU context pointer to a register and thus rendering generated code CPU context independent. Not useful to SheepShaver, but it is for another project for threads emulation on plain x86-32. Note: AltiVec performance may drop a little on x86 but this will be restored (and even improved) in the future. |
From: <cv...@ce...> - 2006-07-06 00:07:50
|
Update of /home/cvs/cebix/SheepShaver/src/Unix by gbeauche Modified Files: configure.ac Log Message: Use -fno-align-functions to really disable function alignment (a value of 0 used the default alignment, e.g. 16 bytes on x86_64). This is purely cosmetics and only helps reading the resulting disassembly. |
From: <cv...@ce...> - 2006-07-06 00:04:36
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-dyngen-ops.cpp ppc-dyngen.cpp Log Message: Remove obsolete vminfp & vmaxfp (too long sequences) |
From: <cv...@ce...> - 2006-07-06 00:01:08
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-dyngen-ops.cpp Log Message: Add more micro asm optimisations to x86{,-64} (mulhw, mulhwu, slw, srw, cntlzw and subf* series). Also now enable the optimzations on x86_64 by default. |
From: <cv...@ce...> - 2006-07-06 00:01:08
|
Update of /home/cvs/cebix/SheepShaver/src/Unix by gbeauche Modified Files: sysdeps.h Log Message: Add more micro asm optimisations to x86{,-64} (mulhw, mulhwu, slw, srw, cntlzw and subf* series). Also now enable the optimzations on x86_64 by default. |
From: <cv...@ce...> - 2006-07-04 23:27:09
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/mathlib by gbeauche Modified Files: mathlib.cpp Log Message: cosmetics |
From: <cv...@ce...> - 2006-07-04 23:23:44
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/mathlib by gbeauche Modified Files: mathlib.hpp Log Message: Use extra precision (e.g. long double) for fma operations though this inhibits some underflow conditions. |
From: <cv...@ce...> - 2006-07-04 23:20:47
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-execute.hpp Log Message: Fix fmadd et al. to set FPSCR[VXISI] only if any of the multiply operands is an inifinity (2.1.5 -- don't set based on the intermediate result) |
From: <cv...@ce...> - 2006-07-04 23:17:41
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-execute.cpp Log Message: Fix frsp FPSCR[OX] condition |
From: <cv...@ce...> - 2006-07-04 10:41:51
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-execute.cpp Log Message: Fix mtfsb0 & mtfsb1 (VEX's xlc_dbl_u32 + code review) |
From: <cv...@ce...> - 2006-07-04 08:58:42
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-operations.hpp Log Message: remove dead code (fdivs was never used) |
From: <cv...@ce...> - 2006-07-04 08:54:56
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-decode.cpp Log Message: Fix mismerge from kpx branch |
From: <cv...@ce...> - 2006-07-04 07:19:19
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-cpu.hpp ppc-execute.cpp ppc-execute.hpp Log Message: Improve FPU emulation accurracy. However, PPC_ENABLE_FPU_EXCEPTIONS is still set to 0 until generated code is optimized enough (current slow down factor is 3x vs. previous core, expectations are about 50% slower FP code). The main benefit is exception bits are accurate. All glibc test-fenv, test-arith{,f}, test-double, test-float pass on ppc, and mostly on x86_64 with gcc 4.0.1. Yes, this is also compiler dependent. FIXME: find a real Mac application that depends on precise FPSCR bits... I think I don't want to care optimizing yet until someone shows me a real world application. |
From: <cv...@ce...> - 2006-07-04 07:19:19
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/mathlib by gbeauche Modified Files: ieeefp.hpp Log Message: Improve FPU emulation accurracy. However, PPC_ENABLE_FPU_EXCEPTIONS is still set to 0 until generated code is optimized enough (current slow down factor is 3x vs. previous core, expectations are about 50% slower FP code). The main benefit is exception bits are accurate. All glibc test-fenv, test-arith{,f}, test-double, test-float pass on ppc, and mostly on x86_64 with gcc 4.0.1. Yes, this is also compiler dependent. FIXME: find a real Mac application that depends on precise FPSCR bits... I think I don't want to care optimizing yet until someone shows me a real world application. |
From: <cv...@ce...> - 2006-07-04 07:06:20
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/mathlib by gbeauche Modified Files: mathlib.hpp Added Files: mathlib-ppc.hpp Log Message: Fix fnmadds & fnmsubs emulation + try to provide optimized fma routines for better precision |
From: <cv...@ce...> - 2006-07-04 07:06:20
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-decode.cpp ppc-operations.hpp Log Message: Fix fnmadds & fnmsubs emulation + try to provide optimized fma routines for better precision |
From: <cv...@ce...> - 2006-07-04 06:59:30
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/mathlib by gbeauche Added Files: mathlib-x86_64.hpp Log Message: Use lrint() for fctiw on x86-64. This is because some glibc use AMD optimized math library where floor(), ceil() et al. don't set the inexact flag correctly |
From: <cv...@ce...> - 2006-07-04 06:58:27
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-cpu.hpp ppc-decode.cpp ppc-execute.cpp ppc-operations.hpp Log Message: Fix fctiw emulation (VEX's jm-ppc-test -f, handle current rounding mode) |
From: <cv...@ce...> - 2006-07-04 06:58:26
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/mathlib by gbeauche Modified Files: mathlib-i386.hpp mathlib.cpp mathlib.hpp Log Message: Fix fctiw emulation (VEX's jm-ppc-test -f, handle current rounding mode) |
From: <cv...@ce...> - 2006-07-04 04:47:06
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-operations.hpp ppc-translate.cpp Log Message: Fix vminfp & vmaxfp emulation (VEX's jm-ppc-test -a, triggered nan bugs) |
From: <cv...@ce...> - 2006-07-04 04:37:17
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-operations.hpp Log Message: Fix vctsxs & vctuxs emulation (VEX's jm-ppc-test -a, triggered inf/nan bugs) |
From: <cv...@ce...> - 2006-07-04 04:37:16
|
Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/mathlib by gbeauche Modified Files: ieeefp.hpp mathlib.cpp mathlib.hpp Log Message: Fix vctsxs & vctuxs emulation (VEX's jm-ppc-test -a, triggered inf/nan bugs) |