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From: <cv...@ce...> - 2006-07-17 07:34:38
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-jit.cpp Log Message: Fix for 32-bit x86, was generating setcc CC,%dh instead of %dl. i.e. force use of ecx & edx -- though it was fine in 64-bit mode, of course |
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From: <cv...@ce...> - 2006-07-17 06:56:40
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/jit by gbeauche Modified Files: basic-dyngen.cpp basic-dyngen.hpp jit-cache.hpp Log Message: Use new code generator. The gain is only 10%, bottlenecks are elsewhere. Optimize Altivec vector splat instructions after Agner's guide. |
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From: <cv...@ce...> - 2006-07-17 06:56:39
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-cpu.hpp ppc-dyngen-ops.cpp ppc-dyngen.cpp ppc-dyngen.hpp ppc-jit.cpp ppc-jit.hpp ppc-translate.cpp Log Message: Use new code generator. The gain is only 10%, bottlenecks are elsewhere. Optimize Altivec vector splat instructions after Agner's guide. |
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From: <cv...@ce...> - 2006-07-17 06:52:15
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/jit/amd64 by gbeauche Modified Files: dyngen-target-exec.h Log Message: Define global XMM registers for SIMD & FPU (64-bit mode) |
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From: <cv...@ce...> - 2006-07-17 06:52:15
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/jit by gbeauche Modified Files: dyngen-exec.h Log Message: Define global XMM registers for SIMD & FPU (64-bit mode) |
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From: <cv...@ce...> - 2006-07-17 06:52:15
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/jit/x86 by gbeauche Modified Files: dyngen-target-exec.h Log Message: Define global XMM registers for SIMD & FPU (64-bit mode) |
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From: <cv...@ce...> - 2006-07-17 06:49:08
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/jit/x86 by gbeauche Added Files: jit-target-codegen.hpp Log Message: Add new code generator for testing purposes (i386, x86_64) -- It's to be used for mid-level optimizations |
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From: <cv...@ce...> - 2006-07-17 06:49:08
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/jit/amd64 by gbeauche Added Files: jit-target-codegen.hpp Log Message: Add new code generator for testing purposes (i386, x86_64) -- It's to be used for mid-level optimizations |
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From: <cv...@ce...> - 2006-07-17 06:49:08
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/jit by gbeauche Added Files: jit-codegen.hpp Log Message: Add new code generator for testing purposes (i386, x86_64) -- It's to be used for mid-level optimizations |
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From: <cv...@ce...> - 2006-07-17 06:47:00
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-registers.hpp Log Message: Make VSCR an uint32, don't bother splitting it into NJ, SAT values since the gain is almost nil and actually hurts performance in JIT mode. |
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From: <cv...@ce...> - 2006-07-17 04:07:44
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Update of /home/cvs/cebix/BasiliskII/src/uae_cpu/compiler by gbeauche Modified Files: codegen_x86.h Log Message: Add LEALQmr, EMMS, SSE CMP and a series of new SSE opcodes (auto-generated) |
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From: <cv...@ce...> - 2006-07-16 12:47:41
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-cpu.hpp ppc-dyngen.cpp ppc-dyngen.hpp ppc-translate.cpp Added Files: ppc-jit.cpp ppc-jit.hpp Log Message: Prepare for new code generator and mid-level optimizations. |
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From: <cv...@ce...> - 2006-07-16 12:47:41
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Update of /home/cvs/cebix/SheepShaver/src/Unix by gbeauche Modified Files: Makefile.in configure.ac Log Message: Prepare for new code generator and mid-level optimizations. |
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From: <cv...@ce...> - 2006-07-16 12:28:03
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/utils by gbeauche Added Files: utils-cpuinfo.cpp utils-cpuinfo.hpp utils-sentinel.hpp Log Message: Move processor capability information to utils-cpuinfo.[ch]hpp. Add new utils-sentinel.hpp for helper functions to be called at program initialization and termination. |
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From: <cv...@ce...> - 2006-07-16 12:26:39
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/utils by gbeauche Log Message: Directory /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/utils added to the repository |
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From: <cv...@ce...> - 2006-07-16 12:23:06
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/test by gbeauche Modified Files: test-powerpc.cpp Log Message: Fix for new code generator -- FIXME: backend macros should be enabled only in ppc-jit.cpp (e.g. define a new ENABLE_JIT_TARGET_ASM macro?) |
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From: <cv...@ce...> - 2006-07-16 12:19:04
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/jit by gbeauche Modified Files: jit-cache.cpp Log Message: Remove obsolete code (HAVE_STATIC_DATA_EXEC). |
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From: <cv...@ce...> - 2006-07-16 12:19:04
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Update of /home/cvs/cebix/SheepShaver/src/Unix by gbeauche Modified Files: configure.ac Log Message: Remove obsolete code (HAVE_STATIC_DATA_EXEC). |
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From: <cv...@ce...> - 2006-07-16 12:09:44
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/jit by gbeauche Modified Files: dyngen-exec.h Log Message: forgot to commit this __op_PARAM? change |
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From: <cv...@ce...> - 2006-07-14 16:53:53
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Update of /home/cvs/cebix/BasiliskII/src/uae_cpu/compiler by gbeauche Modified Files: codegen_x86.h Log Message: Add more SSE templates for new SheepShaver's code generator -- though it should be made independent of this file. |
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From: <cv...@ce...> - 2006-07-14 09:09:17
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Update of /home/cvs/cebix/BasiliskII/src/uae_cpu/compiler by gbeauche Modified Files: codegen_x86.h Log Message: Run-time assembler fixes: - Check for RIP register only in 64-bit mode - Add missing macros and arguments (BT*im) - MOVSWQ/MOVZWQ are 64-bit mode instructions only |
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From: <cv...@ce...> - 2006-07-09 16:11:11
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/ppc by gbeauche Modified Files: ppc-translate.cpp Log Message: Fix debugging of generated code to include the block chainer trampoline. |
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From: <cv...@ce...> - 2006-07-09 15:19:35
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/jit by gbeauche Modified Files: dyngen.c basic-dyngen-ops.cpp Log Message: Fix gen_op_invoke*() for 64-bit offsets on x86-64. Drop CPUPARAM since it's now cached to a host register. |
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From: <cv...@ce...> - 2006-07-09 15:18:09
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/jit by gbeauche Modified Files: basic-dyngen.cpp basic-dyngen.hpp Log Message: Optimize alignment routine for x86 & x86_64. |
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From: <cv...@ce...> - 2006-07-09 12:19:54
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Update of /home/cvs/cebix/SheepShaver/src/kpx_cpu/src/cpu/jit by gbeauche Modified Files: basic-dyngen-ops.cpp Log Message: Some minor optimizations: xchg (unused), movdqa in sse2 code. |
