[Armadeus-commitlog] armadeus/u-boot branch, armadeus-2024.01, updated. b7222197d4dbb294d0accb2d10
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[Armadeus-commitlog] armadeus/u-boot branch, armadeus-2024.01, updated. b7222197d4dbb294d0accb2d1012ce6502439898
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From: sszy <ss...@us...> - 2024-11-06 09:19:42
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The branch, armadeus-2024.01 has been updated
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- Log -----------------------------------------------------------------
commit b7222197d4dbb294d0accb2d1012ce6502439898
Author: Sébastien Szymanski <seb...@ar...>
Date: Thu Oct 31 20:21:28 2024 +0100
imx9: opos93: ddr: update timings
commit 1b9ad332309ad07c6a21aef15504abc61b3806d4
Author: haidong.zheng <hai...@nx...>
Date: Mon Aug 5 13:25:40 2024 +0800
LFU-781 ddr: imx9: Disable dynamic refresh rate when do mr operation
On i.MX93/91, dynamic refresh rate should be disabled before doing any
MR read or write. Otherwise conflict may happen with read MR12/MR14 in
ddr_init.
We randomly meet DDR unstable with low drive mode frequencies and 1600MTS
DDR setting on iMX91. With this fix, the issue is gone.
Signed-off-by: haidong.zheng <hai...@nx...>
Tested-by: Ye Li <ye...@nx...>
Reviewed-by: Jacky Bai <pin...@nx...>
(cherry picked from commit c50050b80a7d61c8e28d851b15af76d829c15032)
commit fa76591113da27030ca4ef7087580619fcafbfea
Author: Tom.zheng <hai...@nx...>
Date: Tue Aug 8 13:48:27 2023 +0800
LF-9746 ddr: imx9: wait until dram initialization complete
If the DDR data INIT bit is set, and ddr is running at low frequency,
need to make sure DDR initialization complete before continue.
Otherwise, unpredictable behavior when inline ECC id enabled.
Signed-off-by: Tom.zheng <hai...@nx...>
Signed-off-by: Jacky Bai <pin...@nx...>
Reviewed-by: Peng Fan <pen...@nx...>
(cherry picked from commit 162b57e3c389a6f941db2b5440c2c14e7158c5c3)
commit 7e868cb6cc957878dbe9bdf43f153258624d23ac
Author: Peng Fan <pen...@nx...>
Date: Fri Aug 2 17:29:53 2024 +0800
LFU-780 imx9: wait ssar when power on power domain
SSAR handshake done means power on finished, not ISO done. so correct
the waiting mask.
Reviewed-by: Ye Li <ye...@nx...>
Signed-off-by: Peng Fan <pen...@nx...>
(cherry picked from commit 7a7445a2113fa5bcf171347e85200decbcaa6487)
-----------------------------------------------------------------------
Summary of changes:
arch/arm/include/asm/arch-imx9/ddr.h | 1 +
arch/arm/include/asm/arch-imx9/imx-regs.h | 1 +
arch/arm/mach-imx/imx9/opos93_lpddr4_timing.c | 107 +++++++++++++-------------
arch/arm/mach-imx/imx9/soc.c | 2 +-
drivers/ddr/imx/imx9/ddr_init.c | 34 +++++++-
5 files changed, 90 insertions(+), 55 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h
index 2b22f3a5be..911ce1612a 100644
--- a/arch/arm/include/asm/arch-imx9/ddr.h
+++ b/arch/arm/include/asm/arch-imx9/ddr.h
@@ -19,6 +19,7 @@
#define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24)
#define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104)
#define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110)
+#define REG_DDR_SDRAM_CFG2 (DDR_CTL_BASE + 0x114)
#define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160)
#define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48)
#define REG_DDR_SDRAM_CFG_3 (DDR_CTL_BASE + 0x260)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 76d241eab0..9953c33b73 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -38,6 +38,7 @@
#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0)
#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2)
#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
+#define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT BIT(8)
#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
#define IMG_CONTAINER_BASE (0x80000000UL)
diff --git a/arch/arm/mach-imx/imx9/opos93_lpddr4_timing.c b/arch/arm/mach-imx/imx9/opos93_lpddr4_timing.c
index f2bbdcdce3..0c927a3ce2 100644
--- a/arch/arm/mach-imx/imx9/opos93_lpddr4_timing.c
+++ b/arch/arm/mach-imx/imx9/opos93_lpddr4_timing.c
@@ -1,9 +1,10 @@
/*
* Copyright 2024 NXP
*
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: BSD-3-Clause
*
- * Code generated with DDR Tool v3.2.0_7.5.
+ * Code generated with DDR Tool v3.4.0_8.3-e3369a1a.
+ * DDR PHY FW2022.01
*/
#include <linux/kernel.h>
@@ -39,26 +40,26 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
{0x4e300100, 0x1451311B},
{0x4e300104, 0xF8CC0017},
{0x4e300108, 0xD4D68E00},
- {0x4e30010C, 0x00718100},
- {0x4e300124, 0x18680000},
+ {0x4e30010C, 0x0071E100},
+ {0x4e300124, 0x18660000},
{0x4e300160, 0x00009101},
{0x4e30016C, 0x33F00000},
{0x4e300170, 0x8B0B0608},
{0x4e300250, 0x00000022},
- {0x4e300254, 0x00880088},
+ {0x4e300254, 0x00000000},
{0x4e300258, 0x00000008},
{0x4e30025C, 0x00000400},
{0x4e300300, 0x1D441D0D},
{0x4e300304, 0x00881E10},
- {0x4e300308, 0x0C300C34},
+ {0x4e300308, 0x0C3C0C34},
},
{
{0x01, 0xD4},
{0x02, 0x2D},
{0x03, 0x33},
{0x0b, 0x46},
- {0x0c, 0x48},
- {0x0e, 0x48},
+ {0x0c, 0x49},
+ {0x0e, 0x18},
{0x16, 0x04},
},
0,
@@ -74,7 +75,7 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
{0x4e30016C, 0x30700000},
{0x4e300170, 0x8A0A0508},
{0x4e300250, 0x00000011},
- {0x4e300254, 0x00400040},
+ {0x4e300254, 0x00000000},
{0x4e300258, 0x00000008},
{0x4e30025C, 0x00000400},
},
@@ -83,8 +84,8 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
{0x02, 0x52},
{0x03, 0x33},
{0x0b, 0x46},
- {0x0c, 0x48},
- {0x0e, 0x48},
+ {0x0c, 0x49},
+ {0x0e, 0x18},
{0x16, 0x04},
},
0,
@@ -100,7 +101,7 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
{0x4e30016C, 0x30000000},
{0x4e300170, 0x89090408},
{0x4e300250, 0x00000007},
- {0x4e300254, 0x00150015},
+ {0x4e300254, 0x00010001},
{0x4e300258, 0x00000008},
{0x4e30025C, 0x00000400},
},
@@ -109,8 +110,8 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
{0x02, 0x9},
{0x03, 0x33},
{0x0b, 0x46},
- {0x0c, 0x48},
- {0x0e, 0x48},
+ {0x0c, 0x49},
+ {0x0e, 0x18},
{0x16, 0x04},
},
1,
@@ -210,17 +211,17 @@ static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{0x120008, 0x190},
{0x220008, 0x9c},
{0x20088, 0x9},
- {0x200b2, 0x10c},
+ {0x200b2, 0x134},
{0x10043, 0x5a1},
{0x10143, 0x5a1},
{0x11043, 0x5a1},
{0x11143, 0x5a1},
- {0x1200b2, 0x10c},
+ {0x1200b2, 0x134},
{0x110043, 0x5a1},
{0x110143, 0x5a1},
{0x111043, 0x5a1},
{0x111143, 0x5a1},
- {0x2200b2, 0x10c},
+ {0x2200b2, 0x134},
{0x210043, 0x5a1},
{0x210143, 0x5a1},
{0x211043, 0x5a1},
@@ -1238,7 +1239,7 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
{0xd0000, 0x0},
{0x54003, 0xc80},
{0x54004, 0x4},
- {0x54006, 0x15},
+ {0x54006, 0x18},
{0x54008, 0x131f},
{0x54009, 0xc8},
{0x5400b, 0x4},
@@ -1247,25 +1248,25 @@ static struct dram_cfg_param ddr_fsp0_cfg[] = {
{0x54012, 0x110},
{0x54019, 0x2dd4},
{0x5401a, 0x33},
- {0x5401b, 0x4846},
- {0x5401c, 0x4808},
+ {0x5401b, 0x4946},
+ {0x5401c, 0x1808},
{0x5401e, 0x4},
{0x5401f, 0x2dd4},
{0x54020, 0x33},
- {0x54021, 0x4846},
- {0x54022, 0x4808},
+ {0x54021, 0x4946},
+ {0x54022, 0x1808},
{0x54024, 0x4},
{0x54032, 0xd400},
{0x54033, 0x332d},
{0x54034, 0x4600},
- {0x54035, 0x848},
- {0x54036, 0x48},
+ {0x54035, 0x849},
+ {0x54036, 0x18},
{0x54037, 0x400},
{0x54038, 0xd400},
{0x54039, 0x332d},
{0x5403a, 0x4600},
- {0x5403b, 0x848},
- {0x5403c, 0x48},
+ {0x5403b, 0x849},
+ {0x5403c, 0x18},
{0x5403d, 0x400},
{0xd0000, 0x1}
};
@@ -1276,7 +1277,7 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
{0x54002, 0x1},
{0x54003, 0x640},
{0x54004, 0x4},
- {0x54006, 0x15},
+ {0x54006, 0x18},
{0x54008, 0x121f},
{0x54009, 0xc8},
{0x5400b, 0x4},
@@ -1285,25 +1286,25 @@ static struct dram_cfg_param ddr_fsp1_cfg[] = {
{0x54012, 0x110},
{0x54019, 0x52a4},
{0x5401a, 0x33},
- {0x5401b, 0x4846},
- {0x5401c, 0x4808},
+ {0x5401b, 0x4946},
+ {0x5401c, 0x1808},
{0x5401e, 0x4},
{0x5401f, 0x52a4},
{0x54020, 0x33},
- {0x54021, 0x4846},
- {0x54022, 0x4808},
+ {0x54021, 0x4946},
+ {0x54022, 0x1808},
{0x54024, 0x4},
{0x54032, 0xa400},
{0x54033, 0x3352},
{0x54034, 0x4600},
- {0x54035, 0x848},
- {0x54036, 0x48},
+ {0x54035, 0x849},
+ {0x54036, 0x18},
{0x54037, 0x400},
{0x54038, 0xa400},
{0x54039, 0x3352},
{0x5403a, 0x4600},
- {0x5403b, 0x848},
- {0x5403c, 0x48},
+ {0x5403b, 0x849},
+ {0x5403c, 0x18},
{0x5403d, 0x400},
{0xd0000, 0x1}
};
@@ -1314,7 +1315,7 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
{0x54002, 0x102},
{0x54003, 0x270},
{0x54004, 0x4},
- {0x54006, 0x15},
+ {0x54006, 0x18},
{0x54008, 0x121f},
{0x54009, 0xc8},
{0x5400b, 0x4},
@@ -1323,25 +1324,25 @@ static struct dram_cfg_param ddr_fsp2_cfg[] = {
{0x54012, 0x110},
{0x54019, 0x994},
{0x5401a, 0x33},
- {0x5401b, 0x4846},
- {0x5401c, 0x4800},
+ {0x5401b, 0x4946},
+ {0x5401c, 0x1800},
{0x5401e, 0x4},
{0x5401f, 0x994},
{0x54020, 0x33},
- {0x54021, 0x4846},
- {0x54022, 0x4800},
+ {0x54021, 0x4946},
+ {0x54022, 0x1800},
{0x54024, 0x4},
{0x54032, 0x9400},
{0x54033, 0x3309},
{0x54034, 0x4600},
- {0x54035, 0x48},
- {0x54036, 0x48},
+ {0x54035, 0x49},
+ {0x54036, 0x18},
{0x54037, 0x400},
{0x54038, 0x9400},
{0x54039, 0x3309},
{0x5403a, 0x4600},
- {0x5403b, 0x48},
- {0x5403c, 0x48},
+ {0x5403b, 0x49},
+ {0x5403c, 0x18},
{0x5403d, 0x400},
{0xd0000, 0x1}
};
@@ -1352,7 +1353,7 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{0xd0000, 0x0},
{0x54003, 0xc80},
{0x54004, 0x4},
- {0x54006, 0x15},
+ {0x54006, 0x18},
{0x54008, 0x61},
{0x54009, 0xc8},
{0x5400b, 0x4},
@@ -1362,25 +1363,25 @@ static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{0x54012, 0x110},
{0x54019, 0x2dd4},
{0x5401a, 0x33},
- {0x5401b, 0x4846},
- {0x5401c, 0x4808},
+ {0x5401b, 0x4946},
+ {0x5401c, 0x1808},
{0x5401e, 0x4},
{0x5401f, 0x2dd4},
{0x54020, 0x33},
- {0x54021, 0x4846},
- {0x54022, 0x4808},
+ {0x54021, 0x4946},
+ {0x54022, 0x1808},
{0x54024, 0x4},
{0x54032, 0xd400},
{0x54033, 0x332d},
{0x54034, 0x4600},
- {0x54035, 0x848},
- {0x54036, 0x48},
+ {0x54035, 0x849},
+ {0x54036, 0x18},
{0x54037, 0x400},
{0x54038, 0xd400},
{0x54039, 0x332d},
{0x5403a, 0x4600},
- {0x5403b, 0x848},
- {0x5403c, 0x48},
+ {0x5403b, 0x849},
+ {0x5403c, 0x18},
{0x5403d, 0x400},
{0xd0000, 0x1}
};
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 60c0bc27bd..8980819f9a 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -721,7 +721,7 @@ static int mix_power_init(enum mix_power_domain pd)
/* power on */
clrbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
val = readl(&mix_regs->func_stat);
- while (val & SRC_MIX_SLICE_FUNC_STAT_ISO_STAT)
+ while (val & SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT)
val = readl(&mix_regs->func_stat);
return 0;
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
index b793274c97..747a2673c0 100644
--- a/drivers/ddr/imx/imx9/ddr_init.c
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -266,6 +266,11 @@ void update_umctl2_rank_space_setting(struct dram_timing_info *dram_timing, unsi
u32 ddrc_mrr(u32 chip_select, u32 mode_reg_num, u32 *mode_reg_val)
{
u32 temp;
+ u8 dyn_ref_rate_en = 0;
+
+ dyn_ref_rate_en = !!(readl(REG_DDR_SDRAM_CFG_3) & BIT(7));
+ if (dyn_ref_rate_en)
+ clrbits_le32(REG_DDR_SDRAM_CFG_3, BIT(7));
writel(0x80000000, REG_DDR_SDRAM_MD_CNTL_2);
temp = 0x80000000 | (chip_select << 28) | (mode_reg_num << 0);
@@ -281,12 +286,20 @@ u32 ddrc_mrr(u32 chip_select, u32 mode_reg_num, u32 *mode_reg_val)
writel(0x0, REG_DDR_SDRAM_MPR4);
writel(0x0, REG_DDR_SDRAM_MD_CNTL_2);
+ if (dyn_ref_rate_en)
+ setbits_le32(REG_DDR_SDRAM_CFG_3, BIT(7));
+
return 0;
}
void ddrc_mrs(u32 cs_sel, u32 opcode, u32 mr)
{
u32 regval;
+ u8 dyn_ref_rate_en = 0;
+
+ dyn_ref_rate_en = !!(readl(REG_DDR_SDRAM_CFG_3) & BIT(7));
+ if (dyn_ref_rate_en)
+ clrbits_le32(REG_DDR_SDRAM_CFG_3, BIT(7));
regval = (cs_sel << 28) | (opcode << 6) | (mr);
writel(regval, REG_DDR_SDRAM_MD_CNTL);
@@ -294,6 +307,9 @@ void ddrc_mrs(u32 cs_sel, u32 opcode, u32 mr)
while ((readl(REG_DDR_SDRAM_MD_CNTL) & 0x80000000) == 0x80000000)
;
check_ddrc_idle();
+
+ if (dyn_ref_rate_en)
+ setbits_le32(REG_DDR_SDRAM_CFG_3, BIT(7));
}
u32 lpddr4_mr_read(u32 mr_rank, u32 mr_addr)
@@ -342,9 +358,11 @@ int ddr_init(struct dram_timing_info *dram_timing)
unsigned int initial_drate;
struct dram_timing_info *saved_timing;
void *fsp;
- int ret;
+ int i, ret;
u32 mr12, mr14;
u32 regval;
+ struct dram_cfg_param *ddrc_cfg;
+ unsigned int ddrc_cfg_num;
debug("DDRINFO: start DRAM init\n");
@@ -387,6 +405,20 @@ int ddr_init(struct dram_timing_info *dram_timing)
check_ddrc_idle();
+ /* if DRAM Data INIT set, wait it be completed */
+ ddrc_cfg = dram_timing->ddrc_cfg;
+ ddrc_cfg_num = dram_timing->ddrc_cfg_num;
+ for (i = 0; i < ddrc_cfg_num; i++) {
+ if (ddrc_cfg->reg == REG_DDR_SDRAM_CFG2) {
+ if (ddrc_cfg->val & 0x10) {
+ while (readl(REG_DDR_SDRAM_CFG2) & 0x10)
+ ;
+ }
+ break;
+ }
+ ddrc_cfg++;
+ }
+
mr12 = lpddr4_mr_read(1, 12);
mr14 = lpddr4_mr_read(1, 14);
hooks/post-receive
--
armadeus/u-boot
|