[Armadeus-commitlog] armadeus/u-boot branch, armadeus-2024.01, updated. 1dea4371660c9976b7f4ac983c
Brought to you by:
sszy
Menu
▾
▴
[Armadeus-commitlog] armadeus/u-boot branch, armadeus-2024.01, updated. 1dea4371660c9976b7f4ac983c674442d9a4cbc4
|
From: sszy <ss...@us...> - 2024-06-21 10:25:35
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus/u-boot".
The branch, armadeus-2024.01 has been updated
via 1dea4371660c9976b7f4ac983c674442d9a4cbc4 (commit)
via 522e1ed619ab74ef941dab4bc720d92028c12d83 (commit)
via 0018eedd004ea7c5754918b93f144d001ac80d7c (commit)
from 8a9dd3daac182fef6e0269c2638563691c7b165e (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 1dea4371660c9976b7f4ac983c674442d9a4cbc4
Author: Sébastien Szymanski <seb...@ar...>
Date: Fri Jun 21 12:20:21 2024 +0200
imx9: opos93: update LPDDR4 timings
commit 522e1ed619ab74ef941dab4bc720d92028c12d83
Author: Ye Li <ye...@nx...>
Date: Mon May 15 11:40:14 2023 +0800
LF-9015 ddr: imx9: Fix DDR MRS bug
When write DDR mode registers, should poll the MD_EN bit of
DDR_SDRAM_MD_CNTL to ensure the MRW command is issued by controller.
Otherwise, it may have problem that following MRS overwrite the
previous one which has not been issued yet.
Signed-off-by: Ye Li <ye...@nx...>
Reviewed-by: Jacky Bai <pin...@nx...>
(cherry picked from commit c4b7e876d16bc6ca5c8c29f12b32ca6e77c975d2)
commit 0018eedd004ea7c5754918b93f144d001ac80d7c
Author: Sébastien Szymanski <seb...@ar...>
Date: Fri Jun 21 12:18:46 2024 +0200
imx9: clock: add more clocks in {int,frac}pll_tbl
-----------------------------------------------------------------------
Summary of changes:
arch/arm/mach-imx/imx9/clock.c | 5 +
arch/arm/mach-imx/imx9/opos93_lpddr4_timing.c | 239 +++++++++++++-------------
drivers/ddr/imx/imx9/ddr_init.c | 2 +
3 files changed, 123 insertions(+), 123 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 92c41e9a67..3e6118df3d 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -31,17 +31,22 @@ static struct imx_intpll_rate_table imx9_intpll_tbl[] = {
INT_PLL_RATE(1400000000U, 1, 175, 3), /* 1.4Ghz */
INT_PLL_RATE(1000000000U, 1, 166, 4), /* 1000Mhz */
INT_PLL_RATE(900000000U, 1, 150, 4), /* 900Mhz */
+ INT_PLL_RATE(800000000U, 1, 200, 6), /* 800Mhz */
};
static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */
FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
+ FRAC_PLL_RATE(800000000U, 1, 200, 6, 0, 1), /* 800Mhz */
FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
+ FRAC_PLL_RATE(600000000U, 1, 200, 8, 0, 1), /* 600Mhz */
FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1),
FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1),
FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1),
+ FRAC_PLL_RATE(233000000U, 1, 174, 18, 3, 4), /* 233Mhz */
+ FRAC_PLL_RATE(200000000U, 1, 200, 24, 0, 1), /* 200Mhz */
};
/* return in khz */
diff --git a/arch/arm/mach-imx/imx9/opos93_lpddr4_timing.c b/arch/arm/mach-imx/imx9/opos93_lpddr4_timing.c
index d2569f49c0..17a269f610 100644
--- a/arch/arm/mach-imx/imx9/opos93_lpddr4_timing.c
+++ b/arch/arm/mach-imx/imx9/opos93_lpddr4_timing.c
@@ -1,16 +1,16 @@
/*
- * Copyright 2023 NXP
+ * Copyright 2024 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*
- * Code generated with DDR Tool v1.0.0.
+ * Code generated with DDR Tool v3.2.0_7.5.
*/
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
-struct dram_cfg_param ddr_ddrc_cfg[] = {
- /** Initialize DDRC registers **/
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x4e300110, 0x44100001},
{0x4e300000, 0x80009f},
{0x4e300008, 0x0},
@@ -30,36 +30,35 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x4e301254, 0x0},
{0x4e301258, 0x0},
{0x4e30125c, 0x0},
-
};
/* dram fsp cfg */
static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
{
{
- {0x4e300100, 0x2494321B},
- {0x4e300104, 0xF8EE001B},
- {0x4e300108, 0x2F2E8233},
- {0x4e30010C, 0x0005E18B},
- {0x4e300124, 0x1C770000},
- {0x4e300160, 0x00009102},
- {0x4e30016C, 0x35F00000},
+ {0x4e300100, 0x1451311B},
+ {0x4e300104, 0xF8CC0017},
+ {0x4e300108, 0xD4D68E00},
+ {0x4e30010C, 0x00718100},
+ {0x4e300124, 0x18680000},
+ {0x4e300160, 0x00009101},
+ {0x4e30016C, 0x33F00000},
{0x4e300170, 0x8B0B0608},
- {0x4e300250, 0x00000028},
- {0x4e300254, 0x00A000A0},
+ {0x4e300250, 0x00000022},
+ {0x4e300254, 0x00880088},
{0x4e300258, 0x00000008},
{0x4e30025C, 0x00000400},
- {0x4e300300, 0x224F2213},
- {0x4e300304, 0x00A02213},
- {0x4e300308, 0x0A3C0E3C},
+ {0x4e300300, 0x1D441D0D},
+ {0x4e300304, 0x00881E10},
+ {0x4e300308, 0x0C300C34},
},
{
- {0x01, 0xE4},
- {0x02, 0x36},
+ {0x01, 0xD4},
+ {0x02, 0x2D},
{0x03, 0x33},
{0x0b, 0x46},
- {0x0c, 0x12},
- {0x0e, 0x23},
+ {0x0c, 0x48},
+ {0x0e, 0x48},
{0x16, 0x04},
},
0,
@@ -71,7 +70,7 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
{0x4e300108, 0x181604AA},
{0x4e30010C, 0x005101E6},
{0x4e300124, 0x0E3C0000},
- {0x4e300160, 0x00009102},
+ {0x4e300160, 0x00009100},
{0x4e30016C, 0x30900000},
{0x4e300170, 0x8A0A0508},
{0x4e300250, 0x00000014},
@@ -84,8 +83,8 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
{0x02, 0x1B},
{0x03, 0x33},
{0x0b, 0x46},
- {0x0c, 0x12},
- {0x0e, 0x23},
+ {0x0c, 0x48},
+ {0x0e, 0x48},
{0x16, 0x04},
},
0,
@@ -97,7 +96,7 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
{0x4e300108, 0x6E621A48},
{0x4e30010C, 0x0031010D},
{0x4e300124, 0x04C50000},
- {0x4e300160, 0x00009102},
+ {0x4e300160, 0x00009100},
{0x4e30016C, 0x30000000},
{0x4e300170, 0x89090408},
{0x4e300250, 0x00000007},
@@ -110,8 +109,8 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
{0x02, 0x9},
{0x03, 0x33},
{0x0b, 0x46},
- {0x0c, 0x12},
- {0x0e, 0x23},
+ {0x0c, 0x48},
+ {0x0e, 0x48},
{0x16, 0x04},
},
1,
@@ -120,7 +119,7 @@ static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
};
/* PHY Initialize Configuration */
-struct dram_cfg_param ddr_ddrphy_cfg[] = {
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
{0x100a0, 0x4},
{0x100a1, 0x5},
{0x100a2, 0x6},
@@ -176,30 +175,30 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
{0x20056, 0x3},
{0x120056, 0x3},
{0x220056, 0x3},
- {0x1004d, 0xe00},
- {0x1014d, 0xe00},
- {0x1104d, 0xe00},
- {0x1114d, 0xe00},
- {0x11004d, 0xe00},
- {0x11014d, 0xe00},
- {0x11104d, 0xe00},
- {0x11114d, 0xe00},
- {0x21004d, 0xe00},
- {0x21014d, 0xe00},
- {0x21104d, 0xe00},
- {0x21114d, 0xe00},
- {0x10049, 0xe3f},
- {0x10149, 0xe3f},
- {0x11049, 0xe3f},
- {0x11149, 0xe3f},
- {0x110049, 0xe3f},
- {0x110149, 0xe3f},
- {0x111049, 0xe3f},
- {0x111149, 0xe3f},
- {0x210049, 0xe3f},
- {0x210149, 0xe3f},
- {0x211049, 0xe3f},
- {0x211149, 0xe3f},
+ {0x1004d, 0x200},
+ {0x1014d, 0x200},
+ {0x1104d, 0x200},
+ {0x1114d, 0x200},
+ {0x11004d, 0x200},
+ {0x11014d, 0x200},
+ {0x11104d, 0x200},
+ {0x11114d, 0x200},
+ {0x21004d, 0x200},
+ {0x21014d, 0x200},
+ {0x21104d, 0x200},
+ {0x21114d, 0x200},
+ {0x10049, 0x61f},
+ {0x10149, 0x61f},
+ {0x11049, 0x61f},
+ {0x11149, 0x61f},
+ {0x110049, 0x61f},
+ {0x110149, 0x61f},
+ {0x111049, 0x61f},
+ {0x111149, 0x61f},
+ {0x210049, 0x61f},
+ {0x210149, 0x61f},
+ {0x211049, 0x61f},
+ {0x211149, 0x61f},
{0x43, 0x7f},
{0x1043, 0x7f},
{0x2043, 0x7f},
@@ -207,7 +206,7 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
{0x20075, 0x4},
{0x20050, 0x11},
{0x2009b, 0x2},
- {0x20008, 0x3a5},
+ {0x20008, 0x320},
{0x120008, 0x1d3},
{0x220008, 0x9c},
{0x20088, 0x9},
@@ -252,11 +251,10 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
{0x1200c7, 0x21},
{0x200ca, 0x24},
{0x1200ca, 0x24},
-
};
-/* ddr phy trained csr */
-struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+/* PHY trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{0x1005f, 0x0},
{0x1015f, 0x0},
{0x1105f, 0x0},
@@ -1233,13 +1231,12 @@ struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{0x11640, 0x0},
{0x11740, 0x0},
{0x11840, 0x0},
-
};
/* P0 message block parameter for training firmware */
-struct dram_cfg_param ddr_fsp0_cfg[] = {
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
{0xd0000, 0x0},
- {0x54003, 0xe94},
+ {0x54003, 0xc80},
{0x54004, 0x4},
{0x54006, 0x15},
{0x54008, 0x131f},
@@ -1248,32 +1245,33 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
{0x5400d, 0x100},
{0x5400f, 0x100},
{0x54012, 0x110},
- {0x54019, 0x36e4},
+ {0x54019, 0x2dd4},
{0x5401a, 0x33},
- {0x5401b, 0x1246},
- {0x5401c, 0x2308},
+ {0x5401b, 0x4846},
+ {0x5401c, 0x4808},
{0x5401e, 0x4},
- {0x5401f, 0x36e4},
+ {0x5401f, 0x2dd4},
{0x54020, 0x33},
- {0x54021, 0x1246},
- {0x54022, 0x2308},
+ {0x54021, 0x4846},
+ {0x54022, 0x4808},
{0x54024, 0x4},
- {0x54032, 0xe400},
- {0x54033, 0x3336},
+ {0x54032, 0xd400},
+ {0x54033, 0x332d},
{0x54034, 0x4600},
- {0x54035, 0x812},
- {0x54036, 0x23},
+ {0x54035, 0x848},
+ {0x54036, 0x48},
{0x54037, 0x400},
- {0x54038, 0xe400},
- {0x54039, 0x3336},
+ {0x54038, 0xd400},
+ {0x54039, 0x332d},
{0x5403a, 0x4600},
- {0x5403b, 0x812},
- {0x5403c, 0x23},
+ {0x5403b, 0x848},
+ {0x5403c, 0x48},
{0x5403d, 0x400},
{0xd0000, 0x1}
};
+
/* P1 message block parameter for training firmware */
-struct dram_cfg_param ddr_fsp1_cfg[] = {
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
{0xd0000, 0x0},
{0x54002, 0x1},
{0x54003, 0x74a},
@@ -1287,30 +1285,31 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
{0x54012, 0x110},
{0x54019, 0x1bb4},
{0x5401a, 0x33},
- {0x5401b, 0x1246},
- {0x5401c, 0x2308},
+ {0x5401b, 0x4846},
+ {0x5401c, 0x4808},
{0x5401e, 0x4},
{0x5401f, 0x1bb4},
{0x54020, 0x33},
- {0x54021, 0x1246},
- {0x54022, 0x2308},
+ {0x54021, 0x4846},
+ {0x54022, 0x4808},
{0x54024, 0x4},
{0x54032, 0xb400},
{0x54033, 0x331b},
{0x54034, 0x4600},
- {0x54035, 0x812},
- {0x54036, 0x23},
+ {0x54035, 0x848},
+ {0x54036, 0x48},
{0x54037, 0x400},
{0x54038, 0xb400},
{0x54039, 0x331b},
{0x5403a, 0x4600},
- {0x5403b, 0x812},
- {0x5403c, 0x23},
+ {0x5403b, 0x848},
+ {0x5403c, 0x48},
{0x5403d, 0x400},
{0xd0000, 0x1}
};
+
/* P2 message block parameter for training firmware */
-struct dram_cfg_param ddr_fsp2_cfg[] = {
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
{0xd0000, 0x0},
{0x54002, 0x102},
{0x54003, 0x270},
@@ -1324,34 +1323,34 @@ struct dram_cfg_param ddr_fsp2_cfg[] = {
{0x54012, 0x110},
{0x54019, 0x994},
{0x5401a, 0x33},
- {0x5401b, 0x1246},
- {0x5401c, 0x2300},
+ {0x5401b, 0x4846},
+ {0x5401c, 0x4800},
{0x5401e, 0x4},
{0x5401f, 0x994},
{0x54020, 0x33},
- {0x54021, 0x1246},
- {0x54022, 0x2300},
+ {0x54021, 0x4846},
+ {0x54022, 0x4800},
{0x54024, 0x4},
{0x54032, 0x9400},
{0x54033, 0x3309},
{0x54034, 0x4600},
- {0x54035, 0x12},
- {0x54036, 0x23},
+ {0x54035, 0x48},
+ {0x54036, 0x48},
{0x54037, 0x400},
{0x54038, 0x9400},
{0x54039, 0x3309},
{0x5403a, 0x4600},
- {0x5403b, 0x12},
- {0x5403c, 0x23},
+ {0x5403b, 0x48},
+ {0x5403c, 0x48},
{0x5403d, 0x400},
{0xd0000, 0x1}
};
/* P0 2D message block parameter for training firmware */
-struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{0xd0000, 0x0},
- {0x54003, 0xe94},
+ {0x54003, 0xc80},
{0x54004, 0x4},
{0x54006, 0x15},
{0x54008, 0x61},
@@ -1361,33 +1360,33 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{0x5400f, 0x100},
{0x54010, 0x2080},
{0x54012, 0x110},
- {0x54019, 0x36e4},
+ {0x54019, 0x2dd4},
{0x5401a, 0x33},
- {0x5401b, 0x1246},
- {0x5401c, 0x2308},
+ {0x5401b, 0x4846},
+ {0x5401c, 0x4808},
{0x5401e, 0x4},
- {0x5401f, 0x36e4},
+ {0x5401f, 0x2dd4},
{0x54020, 0x33},
- {0x54021, 0x1246},
- {0x54022, 0x2308},
+ {0x54021, 0x4846},
+ {0x54022, 0x4808},
{0x54024, 0x4},
- {0x54032, 0xe400},
- {0x54033, 0x3336},
+ {0x54032, 0xd400},
+ {0x54033, 0x332d},
{0x54034, 0x4600},
- {0x54035, 0x812},
- {0x54036, 0x23},
+ {0x54035, 0x848},
+ {0x54036, 0x48},
{0x54037, 0x400},
- {0x54038, 0xe400},
- {0x54039, 0x3336},
+ {0x54038, 0xd400},
+ {0x54039, 0x332d},
{0x5403a, 0x4600},
- {0x5403b, 0x812},
- {0x5403c, 0x23},
+ {0x5403b, 0x848},
+ {0x5403c, 0x48},
{0x5403d, 0x400},
{0xd0000, 0x1}
};
/* DRAM PHY init engine image */
-struct dram_cfg_param ddr_phy_pie[] = {
+static struct dram_cfg_param ddr_phy_pie[] = {
{0xd0000, 0x0},
{0x90000, 0x10},
{0x90001, 0x400},
@@ -1871,9 +1870,9 @@ struct dram_cfg_param ddr_phy_pie[] = {
{0x400d7, 0x20b},
{0x2003a, 0x2},
{0x200be, 0x3},
- {0x2000b, 0x41a},
- {0x2000c, 0xe9},
- {0x2000d, 0x91c},
+ {0x2000b, 0x384},
+ {0x2000c, 0xc8},
+ {0x2000d, 0x7d0},
{0x2000e, 0x2c},
{0x12000b, 0x20d},
{0x12000c, 0x74},
@@ -1947,17 +1946,15 @@ struct dram_cfg_param ddr_phy_pie[] = {
{0x20088, 0x19},
{0xc0080, 0x0},
{0xd0000, 0x1},
-
};
-struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
- /* P0 3733mts 1D */
- .drate = 3733,
+ /* P0 3200mts 1D */
+ .drate = 3200,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
-
},
{
/* P1 1866mts 1D */
@@ -1965,7 +1962,6 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = {
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp1_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
-
},
{
/* P2 625mts 1D */
@@ -1973,17 +1969,14 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = {
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp2_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
-
},
-
{
- /* P0 3733mts 2D */
- .drate = 3733,
+ /* P0 3200mts 2D */
+ .drate = 3200,
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
},
-
};
/* ddr timing config params */
@@ -1998,7 +1991,7 @@ struct dram_timing_info dram_timing = {
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3733, 1866, 625, },
+ .fsp_table = { 3200, 1866, 625, },
.fsp_cfg = ddr_dram_fsp_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg),
};
diff --git a/drivers/ddr/imx/imx9/ddr_init.c b/drivers/ddr/imx/imx9/ddr_init.c
index 7a333880e6..b793274c97 100644
--- a/drivers/ddr/imx/imx9/ddr_init.c
+++ b/drivers/ddr/imx/imx9/ddr_init.c
@@ -291,6 +291,8 @@ void ddrc_mrs(u32 cs_sel, u32 opcode, u32 mr)
regval = (cs_sel << 28) | (opcode << 6) | (mr);
writel(regval, REG_DDR_SDRAM_MD_CNTL);
setbits_le32(REG_DDR_SDRAM_MD_CNTL, BIT(31));
+ while ((readl(REG_DDR_SDRAM_MD_CNTL) & 0x80000000) == 0x80000000)
+ ;
check_ddrc_idle();
}
hooks/post-receive
--
armadeus/u-boot
|