[Armadeus-commitlog] armadeus/u-boot branch, armadeus-2020.07, updated. 815dd4fdf0fedb63c7d78e4733
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[Armadeus-commitlog] armadeus/u-boot branch, armadeus-2020.07, updated. 815dd4fdf0fedb63c7d78e473328f2d253d8b354
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From: Sébastien S. <ss...@us...> - 2022-02-25 13:37:52
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- Log -----------------------------------------------------------------
commit 815dd4fdf0fedb63c7d78e473328f2d253d8b354
Author: Sébastien Szymanski <seb...@ar...>
Date: Fri Feb 25 11:24:03 2022 +0100
cmd: backport pwm command from upstream
commit b1d2b9fa994af59e580095402d0e63c4248c0d19
Author: Sébastien Szymanski <seb...@ar...>
Date: Fri Feb 25 10:08:55 2022 +0100
pwm: imx: Enable PWM support on i.MX8MM
Add missing parts for i.MX8MM PWM support
-----------------------------------------------------------------------
Summary of changes:
arch/arm/include/asm/arch-imx8m/imx-regs.h | 22 ++++++
cmd/Kconfig | 6 ++
cmd/Makefile | 1 +
cmd/pwm.c | 115 +++++++++++++++++++++++++++++
drivers/clk/imx/clk-imx8mm.c | 30 +++++++-
drivers/pwm/pwm-imx-util.c | 2 +-
drivers/pwm/pwm-imx.c | 26 +++++++
7 files changed, 200 insertions(+), 2 deletions(-)
create mode 100644 cmd/pwm.c
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index ee9669f9cd..e659b046f8 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -92,6 +92,28 @@
#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
+#define PWM1_BASE_ADDR 0x30660000
+#define PWM2_BASE_ADDR 0x30670000
+#define PWM3_BASE_ADDR 0x30680000
+#define PWM4_BASE_ADDR 0x30690000
+
+#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
+#define PWMCR_DOZEEN (1 << 24)
+#define PWMCR_WAITEN (1 << 23)
+#define PWMCR_DBGEN (1 << 22)
+#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define PWMCR_CLKSRC_IPG (1 << 16)
+#define PWMCR_EN (1 << 0)
+
+struct pwm_regs {
+ u32 cr;
+ u32 sr;
+ u32 ir;
+ u32 sar;
+ u32 pr;
+ u32 cnr;
+};
+
struct iomuxc_gpr_base_regs {
u32 gpr[47];
};
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 192b3b262f..32bab49d08 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -988,6 +988,12 @@ config CMD_GPIO
help
GPIO support.
+config CMD_PWM
+ bool "pwm"
+ depends on DM_PWM
+ help
+ Control PWM channels, this allows invert/config/enable/disable PWM channels.
+
config CMD_GPT
bool "GPT (GUID Partition Table) command"
select EFI_PARTITION
diff --git a/cmd/Makefile b/cmd/Makefile
index 974ad48b0a..09fff4b6dd 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -112,6 +112,7 @@ endif
obj-$(CONFIG_CMD_PINMUX) += pinmux.o
obj-$(CONFIG_CMD_PMC) += pmc.o
obj-$(CONFIG_CMD_PXE) += pxe.o pxe_utils.o
+obj-$(CONFIG_CMD_PWM) += pwm.o
obj-$(CONFIG_CMD_WOL) += wol.o
obj-$(CONFIG_CMD_QFW) += qfw.o
obj-$(CONFIG_CMD_READ) += read.o
diff --git a/cmd/pwm.c b/cmd/pwm.c
new file mode 100644
index 0000000000..7f9206f67c
--- /dev/null
+++ b/cmd/pwm.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Control PWM channels
+ *
+ * Copyright (c) 2020 SiFive, Inc
+ * author: Pragnesh Patel <pra...@si...>
+ */
+
+#include <command.h>
+#include <dm.h>
+#include <pwm.h>
+
+enum pwm_cmd {
+ PWM_SET_INVERT,
+ PWM_SET_CONFIG,
+ PWM_SET_ENABLE,
+ PWM_SET_DISABLE,
+};
+
+static int do_pwm(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ const char *str_cmd, *str_channel = NULL, *str_enable = NULL;
+ const char *str_pwm = NULL, *str_period = NULL, *str_duty = NULL;
+ enum pwm_cmd sub_cmd;
+ struct udevice *dev;
+ u32 channel, pwm_enable, pwm_dev, period_ns = 0, duty_ns = 0;
+ int ret;
+
+ if (argc < 4)
+ return CMD_RET_USAGE;
+
+ str_cmd = argv[1];
+ argc -= 2;
+ argv += 2;
+
+ str_pwm = *argv;
+ argc--;
+ argv++;
+
+ if (!str_pwm)
+ return CMD_RET_USAGE;
+
+ switch (*str_cmd) {
+ case 'i':
+ sub_cmd = PWM_SET_INVERT;
+ if (argc != 2)
+ return CMD_RET_USAGE;
+ break;
+ case 'c':
+ sub_cmd = PWM_SET_CONFIG;
+ if (argc != 3)
+ return CMD_RET_USAGE;
+ break;
+ case 'e':
+ sub_cmd = PWM_SET_ENABLE;
+ if (argc != 1)
+ return CMD_RET_USAGE;
+ break;
+ case 'd':
+ sub_cmd = PWM_SET_DISABLE;
+ if (argc != 1)
+ return CMD_RET_USAGE;
+ break;
+ default:
+ return CMD_RET_USAGE;
+ }
+
+ pwm_dev = simple_strtoul(str_pwm, NULL, 10);
+ ret = uclass_get_device(UCLASS_PWM, pwm_dev, &dev);
+ if (ret) {
+ printf("pwm: '%s' not found\n", str_pwm);
+ return cmd_process_error(cmdtp, ret);
+ }
+
+ str_channel = *argv;
+ channel = simple_strtoul(str_channel, NULL, 10);
+ argc--;
+ argv++;
+
+ if (sub_cmd == PWM_SET_INVERT) {
+ str_enable = *argv;
+ pwm_enable = simple_strtoul(str_enable, NULL, 10);
+ ret = pwm_set_invert(dev, channel, pwm_enable);
+ } else if (sub_cmd == PWM_SET_CONFIG) {
+ str_period = *argv;
+ argc--;
+ argv++;
+ period_ns = simple_strtoul(str_period, NULL, 10);
+
+ str_duty = *argv;
+ duty_ns = simple_strtoul(str_duty, NULL, 10);
+
+ ret = pwm_set_config(dev, channel, period_ns, duty_ns);
+ } else if (sub_cmd == PWM_SET_ENABLE) {
+ ret = pwm_set_enable(dev, channel, 1);
+ } else if (sub_cmd == PWM_SET_DISABLE) {
+ ret = pwm_set_enable(dev, channel, 0);
+ }
+
+ if (ret) {
+ printf("error(%d)\n", ret);
+ return CMD_RET_FAILURE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(pwm, 6, 0, do_pwm,
+ "control pwm channels",
+ "invert <pwm_dev_num> <channel> <polarity> - invert polarity\n"
+ "pwm config <pwm_dev_num> <channel> <period_ns> <duty_ns> - config PWM\n"
+ "pwm enable <pwm_dev_num> <channel> - enable PWM output\n"
+ "pwm disable <pwm_dev_num> <channel> - eisable PWM output\n"
+ "Note: All input values are in decimal");
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index d609fad7ac..bf8ea6dc58 100644
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -119,6 +119,18 @@ static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_
static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
"sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
+static const char *imx8mm_pwm1_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
+ "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm2_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
+ "sys_pll3_out", "clk_ext1", "sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm3_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
+ "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
+
+static const char *imx8mm_pwm4_sels[] = {"clock-osc-24m", "sys_pll2_100m", "sys_pll1_160m", "sys_pll1_40m",
+ "sys_pll3_out", "clk_ext2", "sys_pll1_80m", "video_pll1_out", };
+
static ulong imx8mm_clk_get_rate(struct clk *clk)
{
struct clk *c;
@@ -373,7 +385,23 @@ static int imx8mm_clk_probe(struct udevice *dev)
clk_dm(IMX8MM_CLK_USDHC3,
imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
base + 0xbc80));
-
+ clk_dm(IMX8MM_CLK_PWM1,
+ imx8m_clk_composite("pwm1", imx8mm_pwm1_sels, base + 0xb380));
+ clk_dm(IMX8MM_CLK_PWM2,
+ imx8m_clk_composite("pwm2", imx8mm_pwm2_sels, base + 0xb400));
+ clk_dm(IMX8MM_CLK_PWM3,
+ imx8m_clk_composite("pwm3", imx8mm_pwm3_sels, base + 0xb480));
+ clk_dm(IMX8MM_CLK_PWM4,
+ imx8m_clk_composite("pwm4", imx8mm_pwm4_sels, base + 0xb500));
+
+ clk_dm(IMX8MM_CLK_PWM1_ROOT,
+ imx_clk_gate4("pwm1_root_clk", "pwm1", base + 0x4280, 0));
+ clk_dm(IMX8MM_CLK_PWM2_ROOT,
+ imx_clk_gate4("pwm2_root_clk", "pwm2", base + 0x4290, 0));
+ clk_dm(IMX8MM_CLK_PWM3_ROOT,
+ imx_clk_gate4("pwm3_root_clk", "pwm3", base + 0x42a0, 0));
+ clk_dm(IMX8MM_CLK_PWM4_ROOT,
+ imx_clk_gate4("pwm4_root_clk", "pwm4", base + 0x42b0, 0));
clk_dm(IMX8MM_CLK_I2C1_ROOT,
imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
clk_dm(IMX8MM_CLK_I2C2_ROOT,
diff --git a/drivers/pwm/pwm-imx-util.c b/drivers/pwm/pwm-imx-util.c
index 823a9d2d6b..f87e4f6e1a 100644
--- a/drivers/pwm/pwm-imx-util.c
+++ b/drivers/pwm/pwm-imx-util.c
@@ -22,7 +22,7 @@ struct pwm_regs *pwm_id_to_reg(int pwm_id)
return (struct pwm_regs *)PWM1_BASE_ADDR;
case 1:
return (struct pwm_regs *)PWM2_BASE_ADDR;
-#ifdef CONFIG_MX6
+#if defined(CONFIG_MX6) || defined(CONFIG_IMX8MM)
case 2:
return (struct pwm_regs *)PWM3_BASE_ADDR;
case 3:
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index f5b9544cb8..eb49dc9128 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -7,6 +7,7 @@
*/
#include <common.h>
+#include <clk.h>
#include <div64.h>
#include <dm.h>
#include <log.h>
@@ -83,6 +84,8 @@ void pwm_disable(int pwm_id)
struct imx_pwm_priv {
struct pwm_regs *regs;
bool invert;
+ struct clk per_clk;
+ struct clk ipg_clk;
};
static int imx_pwm_set_invert(struct udevice *dev, uint channel,
@@ -137,6 +140,29 @@ static int imx_pwm_ofdata_to_platdata(struct udevice *dev)
static int imx_pwm_probe(struct udevice *dev)
{
+ if (CONFIG_IS_ENABLED(CLK_CCF)) {
+ struct imx_pwm_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
+ if (ret < 0) {
+ debug("Can't get PWM ipg clk: %d\n", ret);
+ return ret;
+ }
+ ret = clk_enable(&priv->ipg_clk);
+ if(ret)
+ return ret;
+
+ ret = clk_get_by_name(dev, "per", &priv->per_clk);
+ if (ret < 0) {
+ debug("Can't get PWM per clk: %d\n", ret);
+ return ret;
+ }
+ ret = clk_enable(&priv->ipg_clk);
+ if(ret)
+ return ret;
+ }
+
return 0;
}
hooks/post-receive
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armadeus/u-boot
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