[Armadeus-commitlog] armadeus branch, master, updated. armadeus-7.0-281-gb27674cef

[Fabien M <fa...@us...>]

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- Log -----------------------------------------------------------------
commit b27674ceff485b0215cf41db1991c3aeef750790
Author: Fabien Marteau <fab...@ar...>
Date:   Thu Sep 9 17:43:55 2021 +0200

    [GATEWARE][APF51] fix read/write/strobe clock synchro for imx_eim wrapper in examples

-----------------------------------------------------------------------

Summary of changes:
 .../imx51_wb16_wrapper00/hdl/imx51_wb16_wrapper.vhd | 21 +++++++++++++++------
 .../imx51_wb16_wrapper/imx51_wb16_wrapper.vhd       | 21 +++++++++++++++------
 2 files changed, 30 insertions(+), 12 deletions(-)

diff --git a/firmware/wishbone_example/wishbone_example51/components/imx51_wb16_wrapper00/hdl/imx51_wb16_wrapper.vhd b/firmware/wishbone_example/wishbone_example51/components/imx51_wb16_wrapper00/hdl/imx51_wb16_wrapper.vhd
index 5220c6ced..84d32486b 100644
--- a/firmware/wishbone_example/wishbone_example51/components/imx51_wb16_wrapper00/hdl/imx51_wb16_wrapper.vhd
+++ b/firmware/wishbone_example/wishbone_example51/components/imx51_wb16_wrapper00/hdl/imx51_wb16_wrapper.vhd
@@ -53,7 +53,7 @@ Architecture RTL of imx51_wb16_wrapper is
     signal strobe     : std_logic;
     signal writedata  : std_logic_vector(15 downto 0);
     signal address    : std_logic_vector(15 downto 0);
-
+    signal adv_old : std_logic;
 begin
 
     -- ----------------------------------------------------------------------------
@@ -64,17 +64,27 @@ begin
       if(gls_reset='1') then
         writedata <= (others => '0');
         address   <= (others => '0');
+        adv_old <= '1';
+        strobe <= '0';
+        write  <= '0';
+        read   <= '0';
       elsif(rising_edge(gls_clk)) then
-        if (imx_adv = '0') then
+        if (adv_old = '1' and imx_adv = '0') then
             address <= imx_da;
         else
             writedata <= imx_da;
         end if;
+        adv_old <= imx_adv;
+        strobe  <= not (imx_cs_n);
+        write   <= (not (imx_cs_n)) and (not(imx_rw));
+        read    <= (not (imx_cs_n)) and imx_rw;
+        if ((read = '1') and (strobe = '1')) then
+            imx_da <= wbm_readdata;
+        else
+            imx_da <= (others => 'Z');
+        end if;
       end if;
     end process;
-    strobe  <= not (imx_cs_n);
-    write   <= (not (imx_cs_n)) and (not(imx_rw));
-    read    <= (not (imx_cs_n)) and imx_rw;
 
     wbm_address    <= address;
     wbm_writedata  <= writedata when (write = '1') else (others => '0');
@@ -82,6 +92,5 @@ begin
     wbm_write      <= write;
     wbm_cycle      <= strobe;
 
-    imx_da <= wbm_readdata when ((read = '1') and (strobe = '1')) else (others => 'Z');
 
 end architecture RTL;
diff --git a/firmware/wishbone_example/wishbone_example51/synthesis/imx51_wb16_wrapper/imx51_wb16_wrapper.vhd b/firmware/wishbone_example/wishbone_example51/synthesis/imx51_wb16_wrapper/imx51_wb16_wrapper.vhd
index 5220c6ced..84d32486b 100644
--- a/firmware/wishbone_example/wishbone_example51/synthesis/imx51_wb16_wrapper/imx51_wb16_wrapper.vhd
+++ b/firmware/wishbone_example/wishbone_example51/synthesis/imx51_wb16_wrapper/imx51_wb16_wrapper.vhd
@@ -53,7 +53,7 @@ Architecture RTL of imx51_wb16_wrapper is
     signal strobe     : std_logic;
     signal writedata  : std_logic_vector(15 downto 0);
     signal address    : std_logic_vector(15 downto 0);
-
+    signal adv_old : std_logic;
 begin
 
     -- ----------------------------------------------------------------------------
@@ -64,17 +64,27 @@ begin
       if(gls_reset='1') then
         writedata <= (others => '0');
         address   <= (others => '0');
+        adv_old <= '1';
+        strobe <= '0';
+        write  <= '0';
+        read   <= '0';
       elsif(rising_edge(gls_clk)) then
-        if (imx_adv = '0') then
+        if (adv_old = '1' and imx_adv = '0') then
             address <= imx_da;
         else
             writedata <= imx_da;
         end if;
+        adv_old <= imx_adv;
+        strobe  <= not (imx_cs_n);
+        write   <= (not (imx_cs_n)) and (not(imx_rw));
+        read    <= (not (imx_cs_n)) and imx_rw;
+        if ((read = '1') and (strobe = '1')) then
+            imx_da <= wbm_readdata;
+        else
+            imx_da <= (others => 'Z');
+        end if;
       end if;
     end process;
-    strobe  <= not (imx_cs_n);
-    write   <= (not (imx_cs_n)) and (not(imx_rw));
-    read    <= (not (imx_cs_n)) and imx_rw;
 
     wbm_address    <= address;
     wbm_writedata  <= writedata when (write = '1') else (others => '0');
@@ -82,6 +92,5 @@ begin
     wbm_write      <= write;
     wbm_cycle      <= strobe;
 
-    imx_da <= wbm_readdata when ((read = '1') and (strobe = '1')) else (others => 'Z');
 
 end architecture RTL;


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