[Armadeus-commitlog] UNNAMED PROJECT branch, opos6ul-2018.05, updated. 316dbbbb6239461f309e220ccdc82560acce5cbf

[Sébastien S. <ss...@us...>]

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- Log -----------------------------------------------------------------
commit 316dbbbb6239461f309e220ccdc82560acce5cbf
Author: Sébastien Szymanski <seb...@ar...>
Date:   Mon Sep 24 10:15:30 2018 +0200

    opos6ulsp: allow multiple calls to fpga load

-----------------------------------------------------------------------

Summary of changes:
 arch/arm/mach-imx/mx6/opos6ulsp.c | 56 ++++++++++++++++++++++++---------------
 1 file changed, 34 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-imx/mx6/opos6ulsp.c b/arch/arm/mach-imx/mx6/opos6ulsp.c
index 91b13837c3..8a7afbdf0c 100644
--- a/arch/arm/mach-imx/mx6/opos6ulsp.c
+++ b/arch/arm/mach-imx/mx6/opos6ulsp.c
@@ -67,10 +67,39 @@ static struct gpio_desc fpga_program_b;
 static u32 temp_data;
 static u32 temp_index;
 
+int fpga_pre_fn(int cookie)
+{
+	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	// ACLK_EIM_SLOW derive from AXI (198MHz) divided by 6 = 33MHz
+	clrbits_le32(&ccm_regs->CCGR6, (0x3 << 10));
+	clrbits_le32(&ccm_regs->cscmr1, (0x3 << 29));
+	clrsetbits_le32(&ccm_regs->cscmr1, (0x7 << 23), (0x5 << 23));
+	setbits_le32(&ccm_regs->CCGR6, (0x3 << 10));
+
+	mdelay(1);
+
+	writel(0x00000828, &weim_regs->wcr);
+	writel(0x00000010, &weim_regs->wiar); // not documented in i.MX6ULL RM
+
+	writel(0x019100bf, &weim_regs->cs0gcr1);
+	writel(0x00000000, &weim_regs->cs0gcr2);
+
+	writel(0x01000010, &weim_regs->cs0rcr1);
+	writel(0x00000000, &weim_regs->cs0rcr2);
+
+	writel(0x01000008, &weim_regs->cs0wcr1);
+	writel(0x00000000, &weim_regs->cs0wcr2);
+
+	return 0;
+}
+
 int fpga_pgm_fn(int assert, int flush, int cookie)
 {
 	dm_gpio_set_value(&fpga_program_b, assert);
-	return assert;
+	mdelay(5);
+	return 0;
 }
 
 int fpga_clk_fn(int assert_clk, int flush, int cookie)
@@ -146,9 +175,11 @@ int fpga_post_fn(int cookie)
 	// ACLK_EIM_SLOW derive from PLL2 PFD2 (396MHz) divided by 4 = 99MHz
 	clrbits_le32(&ccm_regs->CCGR6, (0x3 << 10));
 	clrsetbits_le32(&ccm_regs->cscmr1, (0x3 << 29), (0x2 << 29));
+	clrsetbits_le32(&ccm_regs->cscmr1, (0x7 << 23), (0x3 << 23));
 	setbits_le32(&ccm_regs->CCGR6, (0x3 << 10));
 
-	writel(0x019100bf, &weim_regs->cs0gcr1);
+	mdelay(1);
+
 	writel(0x04000010, &weim_regs->cs0rcr1);
 	writel(0x04000008, &weim_regs->cs0wcr1);
 
@@ -166,7 +197,7 @@ int fpga_busy_fn(int cookie)
 }
 
 xilinx_spartan3_slave_parallel_fns fpga_fns = {
-        NULL,
+        fpga_pre_fn,
         fpga_pgm_fn,
         fpga_init_fn,
         NULL,
@@ -186,28 +217,9 @@ xilinx_desc fpga = XILINX_XC6SLX9_DESC(slave_parallel, (void *) &fpga_fns, 0);
 void opos6ulsp_fpga_init(void)
 {
 	int ret;
-	struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
-	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
-
-	// Divide by 4 -> 49MHz
-	clrbits_le32(&ccm_regs->CCGR6, (0x3 << 10));
-	clrsetbits_le32(&ccm_regs->cscmr1, (0x7 << 23), (0x3 << 23));
-	setbits_le32(&ccm_regs->CCGR6, (0x3 << 10));
 
 	imx_iomux_v3_setup_multiple_pads(eim_pads, ARRAY_SIZE(eim_pads));
 
-	writel(0x00000828, &weim_regs->wcr);
-	writel(0x00000010, &weim_regs->wiar); // not documented in i.MX6ULL RM
-
-	writel(0x019100bf, &weim_regs->cs0gcr1);
-	writel(0x00000000, &weim_regs->cs0gcr2);
-
-	writel(0x01000010, &weim_regs->cs0rcr1);
-	writel(0x00000000, &weim_regs->cs0rcr2);
-
-	writel(0x01000008, &weim_regs->cs0wcr1);
-	writel(0x00000000, &weim_regs->cs0wcr2);
-
 	ret = dm_gpio_lookup_name("GPIO4_10", &fpga_done);
 	if (ret) {
 		printf("Cannot get GPIO4_10\n");


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