[Armadeus-commitlog] armadeus branch, master, updated. armadeus-7.0-4-g79ca44441
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-7.0-4-g79ca44441
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From: Sébastien S. <ss...@us...> - 2018-08-29 08:34:53
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 79ca444418da944bb61128a0a4590f24fa6dda4d (commit)
from 9161f1ad075a0f20c4860d803c950715acaac555 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 79ca444418da944bb61128a0a4590f24fa6dda4d
Author: Sébastien Szymanski <seb...@ar...>
Date: Wed Aug 29 10:44:03 2018 +0200
[BSP] Add OPOS6ULSP support
-----------------------------------------------------------------------
Summary of changes:
.../{opos6ul_defconfig => opos6ulsp_defconfig} | 12 +-
.../armadeus/{opos6ul => opos6ulsp}/genimage.cfg | 2 +-
.../opos6ulsp-linux-4.17.config} | 0
.../4.17/0110-ARM-dts-imx6ul-Add-weim-node.patch | 38 +++
...madeus-opos6ul_sp-opos6ul_sp_dev-support.patch} | 364 ++++++++++++---------
5 files changed, 250 insertions(+), 166 deletions(-)
copy buildroot/configs/{opos6ul_defconfig => opos6ulsp_defconfig} (91%)
copy buildroot/target/device/armadeus/{opos6ul => opos6ulsp}/genimage.cfg (87%)
copy buildroot/target/device/armadeus/{opos6ulnano/opos6ulnano-linux-4.17.config => opos6ulsp/opos6ulsp-linux-4.17.config} (100%)
create mode 100644 patches/linux/4.17/0110-ARM-dts-imx6ul-Add-weim-node.patch
copy patches/linux/4.17/{0104-ARM-dts-add-Armadeus-Systems-OPOS6ULNano-and-OPOS6UL.patch => 0111-armadeus-opos6ul_sp-opos6ul_sp_dev-support.patch} (68%)
diff --git a/buildroot/configs/opos6ul_defconfig b/buildroot/configs/opos6ulsp_defconfig
similarity index 91%
copy from buildroot/configs/opos6ul_defconfig
copy to buildroot/configs/opos6ulsp_defconfig
index 01410ec0f..0ea20ac49 100644
--- a/buildroot/configs/opos6ul_defconfig
+++ b/buildroot/configs/opos6ulsp_defconfig
@@ -6,7 +6,7 @@ BR2_BACKUP_SITE="ftp://ftp2.armadeus.com/armadeusw/download"
BR2_CCACHE=y
BR2_CCACHE_DIR="$(TOPDIR)/.$(BR2_BOARD_NAME)-buildroot-ccache"
BR2_TOOLCHAIN_EXTERNAL=y
-BR2_TARGET_GENERIC_HOSTNAME="opos6ul"
+BR2_TARGET_GENERIC_HOSTNAME="opos6ulsp"
BR2_TARGET_GENERIC_ISSUE="Welcome to Armadeus development platform !"
BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_MDEV=y
BR2_TARGET_GENERIC_GETTY_PORT="ttymxc0"
@@ -15,9 +15,9 @@ BR2_TARGET_LOCALTIME="Europe/Paris"
BR2_ROOTFS_OVERLAY="$(ARMADEUS_PATH)/rootfs/target_overlay"
BR2_ROOTFS_POST_BUILD_SCRIPT="$(ARMADEUS_PATH)/rootfs/post_build.sh"
BR2_ROOTFS_POST_IMAGE_SCRIPT="$(ARMADEUS_PATH)/rootfs/post_image_creation.sh"
-BR2_ROOTFS_POST_SCRIPT_ARGS="opos6ul imx6ul"
+BR2_ROOTFS_POST_SCRIPT_ARGS="opos6ulsp imx6ul"
BR2_TARGET_ARMADEUS=y
-BR2_BOARD_NAME="opos6ul"
+BR2_BOARD_NAME="opos6ulsp"
BR2_CPU_NAME="imx6ul"
BR2_TARGET_ARMADEUS_SDRAM_SIZE="256"
BR2_LINUX_KERNEL=y
@@ -27,7 +27,7 @@ BR2_LINUX_KERNEL_PATCH="../patches/linux/4.17"
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-4.17.config"
BR2_LINUX_KERNEL_DTS_SUPPORT=y
-BR2_LINUX_KERNEL_INTREE_DTS_NAME="imx6ul-opos6uldev imx6ull-opos6uldev imx6ul-opos6uldev-dual-ethernet imx6ull-opos6uldev-dual-ethernet"
+BR2_LINUX_KERNEL_INTREE_DTS_NAME="imx6ul-opos6ulspdev imx6ull-opos6ulspdev"
BR2_LINUX_KERNEL_INSTALL_TARGET=y
BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
BR2_PACKAGE_BUSYBOX_CONFIG="$(ARMADEUS_PATH)/busybox.config"
@@ -130,8 +130,8 @@ BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
BR2_TARGET_UBOOT_CUSTOM_GIT=y
BR2_TARGET_UBOOT_CUSTOM_REPO_URL="git://git.code.sf.net/p/armadeus/u-boot"
-BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="ed432e132cf358593dd3aca5abc2024adf2d9288"
-BR2_TARGET_UBOOT_BOARD_DEFCONFIG="opos6uldev"
+BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="94abcef685195131f4665372c3b065f53eceb5bc"
+BR2_TARGET_UBOOT_BOARD_DEFCONFIG="opos6ulspdev"
BR2_TARGET_UBOOT_NEEDS_DTC=y
# BR2_TARGET_UBOOT_FORMAT_BIN is not set
BR2_TARGET_UBOOT_FORMAT_DTB_IMG=y
diff --git a/buildroot/target/device/armadeus/opos6ul/genimage.cfg b/buildroot/target/device/armadeus/opos6ulsp/genimage.cfg
similarity index 87%
copy from buildroot/target/device/armadeus/opos6ul/genimage.cfg
copy to buildroot/target/device/armadeus/opos6ulsp/genimage.cfg
index ec509ed18..f03b8b9ed 100644
--- a/buildroot/target/device/armadeus/opos6ul/genimage.cfg
+++ b/buildroot/target/device/armadeus/opos6ulsp/genimage.cfg
@@ -1,4 +1,4 @@
-# Image for the OPOS6UL eMMC "User Data" partition
+# Image for the OPOS6UL SP eMMC "User Data" partition
#
# For details about the layout, see:
# http://www.armadeus.org/wiki/index.php?title=EMMC_OPOS6UL
diff --git a/buildroot/target/device/armadeus/opos6ulnano/opos6ulnano-linux-4.17.config b/buildroot/target/device/armadeus/opos6ulsp/opos6ulsp-linux-4.17.config
similarity index 100%
copy from buildroot/target/device/armadeus/opos6ulnano/opos6ulnano-linux-4.17.config
copy to buildroot/target/device/armadeus/opos6ulsp/opos6ulsp-linux-4.17.config
diff --git a/patches/linux/4.17/0110-ARM-dts-imx6ul-Add-weim-node.patch b/patches/linux/4.17/0110-ARM-dts-imx6ul-Add-weim-node.patch
new file mode 100644
index 000000000..564199da5
--- /dev/null
+++ b/patches/linux/4.17/0110-ARM-dts-imx6ul-Add-weim-node.patch
@@ -0,0 +1,38 @@
+From 38b5b8027c6a42043d70dda4e6e41a436291421b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?S=C3=A9bastien=20Szymanski?=
+ <seb...@ar...>
+Date: Fri, 24 Aug 2018 18:29:53 +0200
+Subject: [PATCH 1/1] ARM: dts: imx6ul: Add weim node
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add weim node for i.MX6UL SOC.
+
+Signed-off-by: Sébastien Szymanski <seb...@ar...>
+---
+ arch/arm/boot/dts/imx6ul.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+Index: linux-4.17.17/arch/arm/boot/dts/imx6ul.dtsi
+===================================================================
+--- linux-4.17.17.orig/arch/arm/boot/dts/imx6ul.dtsi
++++ linux-4.17.17/arch/arm/boot/dts/imx6ul.dtsi
+@@ -921,6 +921,17 @@
+ reg = <0x021b0000 0x4000>;
+ };
+
++ weim: weim@21b8000 {
++ #address-cells = <2>;
++ #size-cells = <1>;
++ compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
++ reg = <0x021b8000 0x4000>;
++ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&clks IMX6UL_CLK_EIM>;
++ fsl,weim-cs-gpr = <&gpr>;
++ status = "disabled";
++ };
++
+ ocotp: ocotp-ctrl@21bc000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
diff --git a/patches/linux/4.17/0104-ARM-dts-add-Armadeus-Systems-OPOS6ULNano-and-OPOS6UL.patch b/patches/linux/4.17/0111-armadeus-opos6ul_sp-opos6ul_sp_dev-support.patch
similarity index 68%
copy from patches/linux/4.17/0104-ARM-dts-add-Armadeus-Systems-OPOS6ULNano-and-OPOS6UL.patch
copy to patches/linux/4.17/0111-armadeus-opos6ul_sp-opos6ul_sp_dev-support.patch
index af62b0e44..8a31351f1 100644
--- a/patches/linux/4.17/0104-ARM-dts-add-Armadeus-Systems-OPOS6ULNano-and-OPOS6UL.patch
+++ b/patches/linux/4.17/0111-armadeus-opos6ul_sp-opos6ul_sp_dev-support.patch
@@ -1,29 +1,8 @@
-From b697351b49e58573ec604ce074c3cdd337c78537 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?S=C3=A9bastien=20Szymanski?=
- <seb...@ar...>
-Date: Thu, 22 Jun 2017 10:28:57 +0200
-Subject: [PATCH] ARM: dts: add Armadeus Systems OPOS6ULNano and OPOS6ULNanoDEV
- support
-
-OPOS6ULNano is an i.MX6UL based SoM.
-OPOS6ULNanoDev is a carrier board for the OPOS6ULNano SoM.
----
- arch/arm/boot/dts/Makefile | 4 +-
- arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnano.dtsi | 190 ++++++++++++++++
- .../boot/dts/imx6ul-imx6ull-opos6ulnanodev.dtsi | 245 +++++++++++++++++++++
- arch/arm/boot/dts/imx6ul-opos6ulnanodev.dts | 56 +++++
- arch/arm/boot/dts/imx6ull-opos6ulnanodev.dts | 56 +++++
- 5 files changed, 550 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnano.dtsi
- create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnanodev.dtsi
- create mode 100644 arch/arm/boot/dts/imx6ul-opos6ulnanodev.dts
- create mode 100644 arch/arm/boot/dts/imx6ull-opos6ulnanodev.dts
-
-Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnano.dtsi
+Index: linux-4.17.17/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulsp.dtsi
===================================================================
--- /dev/null
-+++ linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnano.dtsi
-@@ -0,0 +1,190 @@
++++ linux-4.17.17/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulsp.dtsi
+@@ -0,0 +1,234 @@
+/*
+ * Copyright 2018 Armadeus Systems <su...@ar...>
+ *
@@ -72,7 +51,7 @@ Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnano.dtsi
+ */
+
+/ {
-+ memory {
++ memory@80000000 {
+ reg = <0x80000000 0>; /* will be filled by U-Boot */
+ };
+
@@ -82,19 +61,20 @@ Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnano.dtsi
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
++};
+
-+ usdhc2_pwrseq: usdhc2-pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
-+ };
++&clks {
++ assigned-clocks = <&clks IMX6UL_CLK_EIM_SLOW_SEL>, <&clks IMX6UL_CLK_EIM_SLOW_PODF>;
++ assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>, <0>;
++ assigned-clock-rates = <0>, <99000000>;
+};
+
-+&fec2 {
++&fec1 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_enet2>;
++ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-reset-duration = <1>;
-+ phy-reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
++ phy-reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ phy-handle = <ðphy1>;
+ phy-supply = <®_3v3>;
+ status = "okay";
@@ -106,18 +86,34 @@ Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnano.dtsi
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
-+ interrupt-parent = <&gpio2>;
-+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
++ interrupt-parent = <&gpio1>;
++ interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+ };
+ };
+};
+
-+/* Bluetooth */
-+&uart3 {
++&i2c3 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart3>;
-+ uart-has-rtscts;
++ pinctrl-0 = <&pinctrl_i2c3>;
++ clock_frequency = <400000>;
++ status = "okay";
++
++ eeprom@50 {
++ compatible = "atmel,24c00";
++ reg = <0x50>;
++ };
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1>;
++ status = "okay";
++};
++
++&uart5 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart5>;
+ status = "okay";
+};
+
@@ -131,56 +127,63 @@ Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnano.dtsi
+ status = "okay";
+};
+
-+/* WiFi */
-+&usdhc2 {
++&weim {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_usdhc2>;
-+ bus-width = <4>;
-+ no-1-8-v;
-+ non-removable;
-+ mmc-pwrseq = <&usdhc2_pwrseq>;
++ pinctrl-0 = <&pinctrl_weim>;
++ ranges = <0 0 0x08000000 0x08000000>;
+ status = "okay";
+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ brcmf: brcmf@1 {
-+ compatible = "brcm,bcm4329-fmac";
-+ reg = <1>;
-+ interrupt-parent = <&gpio4>;
-+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
-+ interrupt-names = "host-wake";
++ fpga@0,0 {
++ reg = <0 0 0x08000000>;
++ fsl,weim-cs-timing = <
++ 0x019100bf /* CS0GCR1 */
++ 0x00000000 /* CS0GCR2 */
++ 0x04000010 /* CS0RCR1 */
++ 0x00000000 /* CS0RCR2 */
++ 0x04000008 /* CS0WCR1 */
++ 0x00000000 /* CS0WCR2 */
++ >;
+ };
+};
+
+&iomuxc {
-+ pinctrl_enet2: enet2grp {
++ pinctrl_enet1: enet1grp {
+ fsl,pins = <
-+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
-+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
-+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x130b0
-+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x130b0
-+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x130b0
-+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x130b0
-+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
-+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
-+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
++ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
++ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
++ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
++ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
++ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
++ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
++ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
++ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
++ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ /* INT# */
-+ MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x1b0b0
++ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x1b0b0
+ /* RST# */
-+ MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x130b0
-+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
++ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x130b0
++ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ >;
+ };
+
-+ pinctrl_uart3: uart3grp {
++ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
-+ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0
-+ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0
-+ MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0
-+ MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0
-+ /* BT_REG_ON */
-+ MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x130b0
++ MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x4001b8b0
++ MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x4001b8b0
++ >;
++ };
++
++ pinctrl_uart1: uart1grp {
++ fsl,pins = <
++ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
++ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5: uart5grp {
++ fsl,pins = <
++ MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1
++ MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1
+ >;
+ };
+
@@ -199,26 +202,46 @@ Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnano.dtsi
+ >;
+ };
+
-+ pinctrl_usdhc2: usdhc2grp {
++ pinctrl_weim: weimgrp {
+ fsl,pins = <
-+ MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
-+ MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
-+ MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
-+ MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
-+ MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
-+ MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
-+ /* WL_REG_ON */
-+ MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x130b0
-+ /* WL_IRQ */
-+ MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x1b0b0 /* 100k pullup */
++ MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x1b0b0
++ MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x1b0b0
++ MX6UL_PAD_CSI_VSYNC__EIM_RW 0x1b0b0
++ MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x1b0b0
++ MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x1b0b0
++ MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x1b0b0
++ MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x1b0b0
++ MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x1b0b0
++ MX6UL_PAD_CSI_DATA00__EIM_AD00 0x1b0b0
++ MX6UL_PAD_CSI_DATA01__EIM_AD01 0x1b0b0
++ MX6UL_PAD_CSI_DATA02__EIM_AD02 0x1b0b0
++ MX6UL_PAD_CSI_DATA03__EIM_AD03 0x1b0b0
++ MX6UL_PAD_CSI_DATA04__EIM_AD04 0x1b0b0
++ MX6UL_PAD_CSI_DATA05__EIM_AD05 0x1b0b0
++ MX6UL_PAD_CSI_DATA06__EIM_AD06 0x1b0b0
++ MX6UL_PAD_CSI_DATA07__EIM_AD07 0x1b0b0
++ MX6UL_PAD_NAND_DATA00__EIM_AD08 0x1b0b0
++ MX6UL_PAD_NAND_DATA01__EIM_AD09 0x1b0b0
++ MX6UL_PAD_NAND_DATA02__EIM_AD10 0x1b0b0
++ MX6UL_PAD_NAND_DATA03__EIM_AD11 0x1b0b0
++ MX6UL_PAD_NAND_DATA04__EIM_AD12 0x1b0b0
++ MX6UL_PAD_NAND_DATA05__EIM_AD13 0x1b0b0
++ MX6UL_PAD_NAND_DATA06__EIM_AD14 0x1b0b0
++ MX6UL_PAD_NAND_DATA07__EIM_AD15 0x1b0b0
++ /* FPGA_INITB */
++ MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
++ /* FPGA_DONE */
++ MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x1b0b0
++ /* FPGA_PROGRAMB */
++ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x130b0
+ >;
+ };
+};
-Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnanodev.dtsi
+Index: linux-4.17.17/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulspdev.dtsi
===================================================================
--- /dev/null
-+++ linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnanodev.dtsi
-@@ -0,0 +1,245 @@
++++ linux-4.17.17/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulspdev.dtsi
+@@ -0,0 +1,268 @@
+/*
+ * Copyright 2018 Armadeus Systems <su...@ar...>
+ *
@@ -271,16 +294,13 @@ Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnanodev.dtsi
+ stdout-path = &uart1;
+ };
+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ user-led {
-+ label = "User";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_led>;
-+ gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
-+ linux,default-trigger = "heartbeat";
-+ };
++ backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm2 0 191000>;
++ brightness-levels = <0 4 8 16 32 64 128 255>;
++ default-brightness-level = <7>;
++ power-supply = <®_5v>;
++ status = "okay";
+ };
+
+ reg_5v: regulator-5v {
@@ -294,26 +314,32 @@ Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnanodev.dtsi
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
-+ cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
++ cs-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ spidev0: spi@0 {
+ compatible = "spidev";
+ reg = <0>;
-+ spi-max-frequency = <60000000>;
++ spi-max-frequency = <5000000>;
+ };
+};
+
-+&i2c1 {
++&ecspi3 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c1>;
-+ clock_frequency = <400000>;
++ pinctrl-0 = <&pinctrl_ecspi3>;
++ cs-gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
+ status = "okay";
++
++ spidev1: spi@0 {
++ compatible = "spidev";
++ reg = <0>;
++ spi-max-frequency = <5000000>;
++ };
+};
+
-+&i2c2 {
++&i2c4 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_i2c2>;
++ pinctrl-0 = <&pinctrl_i2c4>;
+ clock_frequency = <400000>;
+ status = "okay";
+};
@@ -330,7 +356,7 @@ Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnanodev.dtsi
+ bus-width = <18>;
+
+ display-timings {
-+ timing0: timing0 {
++ ST0700 {
+ clock-frequency = <33000033>;
+ hactive = <800>;
+ vactive = <480>;
@@ -341,31 +367,48 @@ Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnanodev.dtsi
+ hsync-len = <64>;
+ vsync-len = <4>;
+ de-active = <1>;
-+ pixelclk-active = <0>;
++ pixelclk-active = <1>;
++ };
++
++ LQ043 {
++ clock-frequency = <8690000>;
++ hactive = <480>;
++ vactive = <272>;
++ hback-porch = <16>;
++ hfront-porch = <16>;
++ vback-porch = <4>;
++ vfront-porch = <2>;
++ hsync-len = <4>;
++ vsync-len = <4>;
++ hsync-active = <0>;
++ vsync-active = <0>;
++ de-active = <0>;
++ pixelclk-active = <1>;
+ };
+ };
+ };
+};
+
-+&snvs_pwrkey {
-+ status = "disabled";
-+};
-+
-+&uart1 {
++&pwm2 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart1>;
++ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
-+&uart2 {
++&snvs_pwrkey {
++ status = "disabled";
++};
++
++&uart3 {
+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_uart2>;
++ pinctrl-0 = <&pinctrl_uart3>;
++ uart-has-rtscts;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_5v>;
-+ dr_mode = "peripheral";
++ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
@@ -383,37 +426,45 @@ Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnanodev.dtsi
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
-+ MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x1b0b0
-+ MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x1b0b0
-+ MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x1b0b0
-+ MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x1b0b0
++ MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x1b0b0
++ MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x1b0b0
++ MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x1b0b0
++ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b0b0
+ >;
+ };
+
-+ pinctrl_gpios: gpiosgrp {
++ pinctrl_ecspi3: ecspi3grp {
+ fsl,pins = <
-+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x1b0b0
-+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x1b0b0
-+ MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x1b0b0
-+ MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x1b0b0
-+ MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b0
-+ MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b0b0
-+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x1b0b0
-+ MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x1b0b0
++ MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x1b0b0
++ MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x1b0b0
++ MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x1b0b0
++ MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x1b0b0
+ >;
+ };
+
-+ pinctrl_i2c1: i2c1grp {
++ pinctrl_gpios: gpiosgrp {
+ fsl,pins = <
-+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
-+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
++ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x1b0b0
++ MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x1b0b0
++ MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x1b0b0
++ MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0
++ MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x1b0b0
++ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0
++ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0
++ MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0
++ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0
++ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0
++ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0
++ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
++ MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0
++ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
+ >;
+ };
+
-+ pinctrl_i2c2: i2c2grp {
++ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
-+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
-+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
++ MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x4001b8b0
++ MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x4001b8b0
+ >;
+ };
+
@@ -444,30 +495,25 @@ Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-imx6ull-opos6ulnanodev.dtsi
+ >;
+ };
+
-+ pinctrl_led: ledgrp {
++ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
-+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0b0b0
++ MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x1b0b0
+ >;
+ };
+
-+ pinctrl_uart1: uart1grp {
-+ fsl,pins = <
-+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
-+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
-+ >;
-+ };
-+
-+ pinctrl_uart2: uart2grp {
++ pinctrl_uart3: uart3grp {
+ fsl,pins = <
-+ MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
-+ MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
++ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
++ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
++ MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
++ MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
+ >;
+ };
+};
-Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-opos6ulnanodev.dts
+Index: linux-4.17.17/arch/arm/boot/dts/imx6ul-opos6ulspdev.dts
===================================================================
--- /dev/null
-+++ linux-4.17.1/arch/arm/boot/dts/imx6ul-opos6ulnanodev.dts
++++ linux-4.17.17/arch/arm/boot/dts/imx6ul-opos6ulspdev.dts
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2018 Armadeus Systems <su...@ar...>
@@ -518,17 +564,17 @@ Index: linux-4.17.1/arch/arm/boot/dts/imx6ul-opos6ulnanodev.dts
+
+/dts-v1/;
+#include "imx6ul.dtsi"
-+#include "imx6ul-imx6ull-opos6ulnano.dtsi"
-+#include "imx6ul-imx6ull-opos6ulnanodev.dtsi"
++#include "imx6ul-imx6ull-opos6ulsp.dtsi"
++#include "imx6ul-imx6ull-opos6ulspdev.dtsi"
+
+/ {
-+ model = "Armadeus Systems OPOS6UL Nano SoM (i.MX6UL) on OPOS6ULDev board (customized for OPOS6UL Nano)";
-+ compatible = "armadeus,opos6ulnanodev", "armadeus,opos6ulnano", "fsl,imx6ul";
++ model = "Armadeus Systems OPOS6UL SP SoM (i.MX6UL) on OPOS6ULSPDev board";
++ compatible = "armadeus,opos6ulspdev", "armadeus,opos6ulsp", "fsl,imx6ul";
+};
-Index: linux-4.17.1/arch/arm/boot/dts/imx6ull-opos6ulnanodev.dts
+Index: linux-4.17.17/arch/arm/boot/dts/imx6ull-opos6ulspdev.dts
===================================================================
--- /dev/null
-+++ linux-4.17.1/arch/arm/boot/dts/imx6ull-opos6ulnanodev.dts
++++ linux-4.17.17/arch/arm/boot/dts/imx6ull-opos6ulspdev.dts
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2018 Armadeus Systems <su...@ar...>
@@ -579,10 +625,10 @@ Index: linux-4.17.1/arch/arm/boot/dts/imx6ull-opos6ulnanodev.dts
+
+/dts-v1/;
+#include "imx6ull.dtsi"
-+#include "imx6ul-imx6ull-opos6ulnano.dtsi"
-+#include "imx6ul-imx6ull-opos6ulnanodev.dtsi"
++#include "imx6ul-imx6ull-opos6ulsp.dtsi"
++#include "imx6ul-imx6ull-opos6ulspdev.dtsi"
+
+/ {
-+ model = "Armadeus Systems OPOS6UL Nano SoM (i.MX6ULL) on OPOS6ULDev board (customized for OPOS6UL Nano)";
-+ compatible = "armadeus,opos6ulnanodev", "armadeus,opos6ulnano", "fsl,imx6ull";
++ model = "Armadeus Systems OPOS6UL SP SoM (i.MX6ULL) on OPOS6ULSPDev board";
++ compatible = "armadeus,opos6ulspdev", "armadeus,opos6ulsp", "fsl,imx6ull";
+};
hooks/post-receive
--
armadeus
|