[Armadeus-commitlog] armadeus branch, master, updated. armadeus-6.0-456-g92033b6d8
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-6.0-456-g92033b6d8
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From: Sébastien S. <ss...@us...> - 2018-07-20 11:16:23
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from a527ca703a574bac3df9ec3cbc9864546c36b904 (commit)
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- Log -----------------------------------------------------------------
commit 92033b6d8d2fd8c150a85cf4c1f42a33134e247a
Author: Sébastien Szymanski <seb...@ar...>
Date: Fri Jul 20 12:23:51 2018 +0200
[LINUX] 4.17: fix UART5 on i.MX6ULL
-----------------------------------------------------------------------
Summary of changes:
...6ull-add-UART5-input-select-register-defi.patch | 63 ++++++++++++++++
...x6ull-add-UART5-RTS-input-select-register.patch | 65 +++++++++++++++++
...6ull-keep-IMX6UL_-prefix-for-signals-on-b.patch | 84 ++++++++++++++++++++++
3 files changed, 212 insertions(+)
create mode 100644 patches/linux/4.17/0107-ARM-dts-imx6ull-add-UART5-input-select-register-defi.patch
create mode 100644 patches/linux/4.17/0108-ARM-dts-imx6ull-add-UART5-RTS-input-select-register.patch
create mode 100644 patches/linux/4.17/0109-ARM-dts-imx6ull-keep-IMX6UL_-prefix-for-signals-on-b.patch
diff --git a/patches/linux/4.17/0107-ARM-dts-imx6ull-add-UART5-input-select-register-defi.patch b/patches/linux/4.17/0107-ARM-dts-imx6ull-add-UART5-input-select-register-defi.patch
new file mode 100644
index 000000000..70b9f5a25
--- /dev/null
+++ b/patches/linux/4.17/0107-ARM-dts-imx6ull-add-UART5-input-select-register-defi.patch
@@ -0,0 +1,63 @@
+From 9b483b889da23998f973cf683f0935879a7ff294 Mon Sep 17 00:00:00 2001
+From: Greg Ungerer <ge...@li...>
+Date: Thu, 29 Mar 2018 00:22:23 +1000
+Subject: [PATCH] ARM: dts: imx6ull: add UART5 input select register
+ definitions
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The iMX6ULL UART5_RX_DATA_SELECT_INPUT DAISY Register has some different
+bit definitions to that same register in the iMX6UL.
+
+The bits for the iMX6UL:
+
+000 CSI_DATA00_ALT8 â Selecting Pad: CSI_DATA00 for Mode: ALT8
+001 CSI_DATA01_ALT8 â Selecting Pad: CSI_DATA01 for Mode: ALT8
+010 GPIO1_IO04_ALT8 â Selecting Pad: GPIO1_IO04 for Mode: ALT8
+011 GPIO1_IO05_ALT8 â Selecting Pad: GPIO1_IO05 for Mode: ALT
+100 UART5_TX_DATA_ALT0 â Selecting Pad: UART5_TX_DATA for Mode: ALT
+101 UART5_RX_DATA_ALT0 â Selecting Pad: UART5_RX_DATA for Mode: ALT
+
+But for the iMX6ULL:
+
+000 CSI_DATA00_ALT8 â Selecting Pad: CSI_DATA00 for Mode: ALT8
+001 CSI_DATA01_ALT8 â Selecting Pad: CSI_DATA01 for Mode: ALT8
+010 GPIO1_IO04_ALT8 â Selecting Pad: GPIO1_IO04 for Mode: ALT8
+011 GPIO1_IO05_ALT8 â Selecting Pad: GPIO1_IO05 for Mode: ALT
+100 UART1_TX_DATA_ALT9 â Selecting Pad: UART1_TX_DATA for Mode: ALT9
+101 UART1_RX_DATA_ALT9 â Selecting Pad: UART1_RX_DATA for Mode: ALT9
+110 UART5_TX_DATA_ALT0 â Selecting Pad: UART5_TX_DATA for Mode: ALT0
+111 UART5_RX_DATA_ALT0 â Selecting Pad: UART5_RX_DATA for Mode: ALT0
+
+Specifically for a board I am working on with the serial console on UART5
+I need to be able to enable UART5_RX_DATA_ALT0 mode. There is no definition
+for the iMX6ULL version of that in imx6ul-pinfunc.h or imx6ull-pinfunc.h.
+
+Add definitions for the missing UART5 input select register bits of the
+iMX6ULL.
+
+Signed-off-by: Greg Ungerer <ge...@li...>
+Acked-by: Stefan Wahren <ste...@i2...>
+Signed-off-by: Shawn Guo <sha...@ke...>
+---
+ arch/arm/boot/dts/imx6ull-pinfunc.h | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/imx6ull-pinfunc.h b/arch/arm/boot/dts/imx6ull-pinfunc.h
+index 118202336691..090846b97680 100644
+--- a/arch/arm/boot/dts/imx6ull-pinfunc.h
++++ b/arch/arm/boot/dts/imx6ull-pinfunc.h
+@@ -14,6 +14,10 @@
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
++#define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
++#define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
++#define MX6ULL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
++#define MX6ULL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
+ #define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
+ #define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
+ #define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
+--
+2.16.4
diff --git a/patches/linux/4.17/0108-ARM-dts-imx6ull-add-UART5-RTS-input-select-register.patch b/patches/linux/4.17/0108-ARM-dts-imx6ull-add-UART5-RTS-input-select-register.patch
new file mode 100644
index 000000000..6ca9108ce
--- /dev/null
+++ b/patches/linux/4.17/0108-ARM-dts-imx6ull-add-UART5-RTS-input-select-register.patch
@@ -0,0 +1,65 @@
+From 04fffabdf1343e4179237bb2bb3e61fa396e32a8 Mon Sep 17 00:00:00 2001
+From: Stefan Wahren <ste...@i2...>
+Date: Thu, 19 Apr 2018 13:19:39 +0200
+Subject: [PATCH] ARM: dts: imx6ull: add UART5 RTS input select register
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The iMX6ULL UART5_RTS_B_DATA_SELECT_INPUT DAISY Register has some different
+bit definitions to that same register in the i.MX6UL.
+
+The bits for the i.MX6UL:
+
+000 CSI_DATA03_ALT8 â Selecting Pad: CSI_DATA03 for Mode: ALT8
+001 GPIO1_IO08_ALT8 â Selecting Pad: GPIO1_IO08 for Mode: ALT8
+010 GPIO1_IO09_ALT8 â Selecting Pad: GPIO1_IO09 for Mode: ALT8
+011 ENET1_RX_EN_ALT1 â Selecting Pad: ENET1_RX_EN for Mode: ALT1
+100 ENET1_TX_DATA0_ALT1 â Selecting Pad: ENET1_TX_DATA0 for Mode: ALT1
+101 CSI_DATA02_ALT8 â Selecting Pad: CSI_DATA02 for Mode: ALT8
+
+But for the i.MX6ULL:
+
+000 CSI_DATA03_ALT8 â Selecting Pad: CSI_DATA03 for Mode: ALT8
+001 GPIO1_IO08_ALT8 â Selecting Pad: GPIO1_IO08 for Mode: ALT8
+010 GPIO1_IO09_ALT8 â Selecting Pad: GPIO1_IO09 for Mode: ALT8
+011 UART1_CTS_B_ALT9 â Selecting Pad: UART1_CTS_B for Mode: ALT9
+100 UART1_RTS_B_ALT9 â Selecting Pad: UART1_RTS_B for Mode: ALT9
+101 ENET1_RX_EN_ALT1 â Selecting Pad: ENET1_RX_EN for Mode: ALT1
+110 ENET1_TX_DATA0_ALT1 â Selecting Pad: ENET1_TX_DATA0 for Mode: ALT1
+111 CSI_DATA02_ALT8 â Selecting Pad: CSI_DATA02 for Mode: ALT8
+
+Signed-off-by: Stefan Wahren <ste...@i2...>
+Acked-by: Rob Herring <ro...@ke...>
+Signed-off-by: Shawn Guo <sha...@ke...>
+---
+ arch/arm/boot/dts/imx6ull-pinfunc.h | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/imx6ull-pinfunc.h b/arch/arm/boot/dts/imx6ull-pinfunc.h
+index 090846b97680..fdc46bb09cc1 100644
+--- a/arch/arm/boot/dts/imx6ull-pinfunc.h
++++ b/arch/arm/boot/dts/imx6ull-pinfunc.h
+@@ -16,8 +16,12 @@
+ */
+ #define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
+ #define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
++#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_RTS 0x008C 0x0318 0x0640 0x9 0x3
++#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_RTS 0x0090 0x031C 0x0640 0x9 0x4
+ #define MX6ULL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
+ #define MX6ULL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
++#define MX6ULL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
++#define MX6ULL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
+ #define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
+ #define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
+ #define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
+@@ -51,6 +55,7 @@
+ #define MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
+ #define MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
+ #define MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
++#define MX6ULL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7
+ #define MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
+ #define MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
+ #define MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
+--
+2.16.4
diff --git a/patches/linux/4.17/0109-ARM-dts-imx6ull-keep-IMX6UL_-prefix-for-signals-on-b.patch b/patches/linux/4.17/0109-ARM-dts-imx6ull-keep-IMX6UL_-prefix-for-signals-on-b.patch
new file mode 100644
index 000000000..c6bcdd4e0
--- /dev/null
+++ b/patches/linux/4.17/0109-ARM-dts-imx6ull-keep-IMX6UL_-prefix-for-signals-on-b.patch
@@ -0,0 +1,84 @@
+From 342eb957b977269cb32ab864ea991081e2109c4f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?S=C3=A9bastien=20Szymanski?=
+ <seb...@ar...>
+Date: Fri, 20 Jul 2018 11:44:19 +0200
+Subject: [PATCH 1/1] ARM: dts: imx6ull: keep IMX6UL_ prefix for signals on
+ both i.MX6UL and i.MX6ULL
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signals available on both i.MX6UL and i.MX6ULL should have the same name
+because it is the case of all others common signals, it avoids to make
+mistakes (use the wrong ones) and it makes writing device tree files
+less complicated. For example:
+
+imx6ul-imx6ull-board.dtsi:
+ ...
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
+ >;
+ };
+
+imx6ul-board.dts:
+ #include <imx6ul.dtsi>
+ #include <imx6ul-imx6ull-board.dtsi>
+ ...
+
+imx6ull-board.dts:
+ #include <imx6ull.dtsi>
+ #include <imx6ul-imx6ull-board.dtsi>
+ ...
+
+Without this patch, the imx6ull-board.dtb will use
+MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX instead of
+MX6ULL_PAD_UART5_RX_DATA__UART5_DCE_RX and the uart5 will be
+misconfigured.
+
+Signed-off-by: Sébastien Szymanski <seb...@ar...>
+---
+ arch/arm/boot/dts/imx6ull-pinfunc.h | 27 +++++++++++++++++++--------
+ 1 file changed, 19 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm/boot/dts/imx6ull-pinfunc.h b/arch/arm/boot/dts/imx6ull-pinfunc.h
+index fdc46bb09cc1..7d7f05f7ea77 100644
+--- a/arch/arm/boot/dts/imx6ull-pinfunc.h
++++ b/arch/arm/boot/dts/imx6ull-pinfunc.h
+@@ -14,14 +14,25 @@
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+-#define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
+-#define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
+-#define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_RTS 0x008C 0x0318 0x0640 0x9 0x3
+-#define MX6ULL_PAD_UART1_RTS_B__UART5_DTE_RTS 0x0090 0x031C 0x0640 0x9 0x4
+-#define MX6ULL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
+-#define MX6ULL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
+-#define MX6ULL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
+-#define MX6ULL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
++/* signals common for i.MX6UL and i.MX6ULL */
++#undef MX6UL_PAD_UART1_TX_DATA__UART5_DTE_RX
++#define MX6UL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4
++#undef MX6UL_PAD_UART1_RX_DATA__UART5_DCE_RX
++#define MX6UL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5
++#undef MX6UL_PAD_UART1_CTS_B__UART5_DCE_RTS
++#define MX6UL_PAD_UART1_CTS_B__UART5_DCE_RTS 0x008C 0x0318 0x0640 0x9 0x3
++#undef MX6UL_PAD_UART1_RTS_B__UART5_DTE_RTS
++#define MX6UL_PAD_UART1_RTS_B__UART5_DTE_RTS 0x0090 0x031C 0x0640 0x9 0x4
++#undef MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX
++#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6
++#undef MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX
++#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7
++#undef MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS
++#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5
++#undef MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS
++#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6
++
++/* signals for i.MX6ULL only */
+ #define MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
+ #define MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
+ #define MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
+--
+2.16.4
hooks/post-receive
--
armadeus
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