[Armadeus-commitlog] armadeus branch, master, updated. armadeus-6.0-310-gbe1e02c
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-6.0-310-gbe1e02c
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From: Sébastien S. <ss...@us...> - 2017-08-01 11:57:17
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- Log -----------------------------------------------------------------
commit be1e02cc704ef7a1396eda727bb40f5fafceca30
Author: Sébastien Szymanski <seb...@ar...>
Date: Tue Aug 1 14:02:45 2017 +0200
[LINUX] apf6: 3.19: fix HDMI on i.MX6 SoCs without VPU
-----------------------------------------------------------------------
Summary of changes:
...lk-Change-hdmi_isfr-clock-s-parent-to-be-.patch | 34 +++++++++++++++
...lk-Change-hsi_tx-clock-to-be-a-shared-clo.patch | 43 ++++++++++++++++++
...lk-Add-support-for-mipi_core_cfg-clock-as.patch | 51 ++++++++++++++++++++++
...lk-Add-support-for-mipi_ipg-clock-as-a-sh.patch | 48 ++++++++++++++++++++
...fine-hdmi_isfr-s-parent-to-make-HDMI-work.patch | 50 +++++++++++++++++++++
5 files changed, 226 insertions(+)
create mode 100644 patches/linux/3.19/0711-ARM-imx6q-clk-Change-hdmi_isfr-clock-s-parent-to-be-.patch
create mode 100644 patches/linux/3.19/0712-ARM-imx6q-clk-Change-hsi_tx-clock-to-be-a-shared-clo.patch
create mode 100644 patches/linux/3.19/0713-ARM-imx6q-clk-Add-support-for-mipi_core_cfg-clock-as.patch
create mode 100644 patches/linux/3.19/0714-ARM-imx6q-clk-Add-support-for-mipi_ipg-clock-as-a-sh.patch
create mode 100644 patches/linux/3.19/0715-clk-imx6-refine-hdmi_isfr-s-parent-to-make-HDMI-work.patch
diff --git a/patches/linux/3.19/0711-ARM-imx6q-clk-Change-hdmi_isfr-clock-s-parent-to-be-.patch b/patches/linux/3.19/0711-ARM-imx6q-clk-Change-hdmi_isfr-clock-s-parent-to-be-.patch
new file mode 100644
index 0000000..ed06b65
--- /dev/null
+++ b/patches/linux/3.19/0711-ARM-imx6q-clk-Change-hdmi_isfr-clock-s-parent-to-be-.patch
@@ -0,0 +1,34 @@
+From 974a7115986ee5d0b2db9cc8cd551e6f88e01378 Mon Sep 17 00:00:00 2001
+From: Liu Ying <Yin...@fr...>
+Date: Thu, 12 Feb 2015 14:01:27 +0800
+Subject: [PATCH 1/4] ARM: imx6q: clk: Change hdmi_isfr clock's parent to be
+ video_27m clock
+
+According to the table 33-1 in the i.MX6Q reference manual, the hdmi_isfr
+clock's parent should be the video_27m clock. The i.MX6DL reference manual
+has the same statement. This patch changes the hdmi_isfr clock's parent
+from the pll3_pfd1_540m clock to the video_27m clock.
+
+Suggested-by: Philipp Zabel <p....@pe...>
+Signed-off-by: Liu Ying <Yin...@fr...>
+Signed-off-by: Shawn Guo <sha...@li...>
+---
+ arch/arm/mach-imx/clk-imx6q.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
+index 8335bfc..ab6acd9 100644
+--- a/arch/arm/mach-imx/clk-imx6q.c
++++ b/arch/arm/mach-imx/clk-imx6q.c
+@@ -401,7 +401,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
+ clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
+ clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
+ clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
+- clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
++ clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "video_27m", base + 0x70, 4);
+ clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
+ clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
+ clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
+--
+2.7.3
+
diff --git a/patches/linux/3.19/0712-ARM-imx6q-clk-Change-hsi_tx-clock-to-be-a-shared-clo.patch b/patches/linux/3.19/0712-ARM-imx6q-clk-Change-hsi_tx-clock-to-be-a-shared-clo.patch
new file mode 100644
index 0000000..5f18571
--- /dev/null
+++ b/patches/linux/3.19/0712-ARM-imx6q-clk-Change-hsi_tx-clock-to-be-a-shared-clo.patch
@@ -0,0 +1,43 @@
+From 721fee59d26e46700476f4c70572e9e0f1cc8fd3 Mon Sep 17 00:00:00 2001
+From: Liu Ying <Yin...@fr...>
+Date: Thu, 12 Feb 2015 14:01:28 +0800
+Subject: [PATCH 2/4] ARM: imx6q: clk: Change hsi_tx clock to be a shared clock
+ gate
+
+The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg'
+clock, according to the i.MX6q/sdl reference manuals. This clock is
+actually the gate for several clocks, including the hsi_tx_sel clock's
+output and the video_27m clock's output. So, this patch changes the
+hsi_tx clock to be a shared clock gate.
+
+Suggested-by: Philipp Zabel <p....@pe...>
+Signed-off-by: Liu Ying <Yin...@fr...>
+Signed-off-by: Shawn Guo <sha...@li...>
+---
+ arch/arm/mach-imx/clk-imx6q.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
+index ab6acd9..6843ea9 100644
+--- a/arch/arm/mach-imx/clk-imx6q.c
++++ b/arch/arm/mach-imx/clk-imx6q.c
+@@ -119,6 +119,7 @@ static unsigned int share_count_asrc;
+ static unsigned int share_count_ssi1;
+ static unsigned int share_count_ssi2;
+ static unsigned int share_count_ssi3;
++static unsigned int share_count_mipi_core_cfg;
+
+ static void __init imx6q_clocks_init(struct device_node *ccm_node)
+ {
+@@ -416,7 +417,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
+ clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
+ clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
+ clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
+- clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
++ clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg);
+ if (cpu_is_imx6dl())
+ /*
+ * The multiplexer and divider of the imx6q clock gpu2d get
+--
+2.7.3
+
diff --git a/patches/linux/3.19/0713-ARM-imx6q-clk-Add-support-for-mipi_core_cfg-clock-as.patch b/patches/linux/3.19/0713-ARM-imx6q-clk-Add-support-for-mipi_core_cfg-clock-as.patch
new file mode 100644
index 0000000..af1d61d
--- /dev/null
+++ b/patches/linux/3.19/0713-ARM-imx6q-clk-Add-support-for-mipi_core_cfg-clock-as.patch
@@ -0,0 +1,51 @@
+From 5ccc248cc53708337a2bfe4ea380c20948e8bbed Mon Sep 17 00:00:00 2001
+From: Liu Ying <Yin...@fr...>
+Date: Thu, 12 Feb 2015 14:01:29 +0800
+Subject: [PATCH 3/4] ARM: imx6q: clk: Add support for mipi_core_cfg clock as a
+ shared clock gate
+
+The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock,
+according to the i.MX6q/sdl reference manuals. This clock is actually the
+gate for several clocks, including the hsi_tx_sel clock's output and the
+video_27m clock's output. The MIPI DSI host controller embedded in the
+i.MX6q/sdl SoCs uses the video_27m clock to generate PLL reference clock and
+MIPI core configuration clock. In order to gate/ungate the two MIPI DSI
+host controller relevant clocks, this patch adds the mipi_core_cfg clock as
+a shared clock gate.
+
+Suggested-by: Philipp Zabel <p....@pe...>
+Signed-off-by: Liu Ying <Yin...@fr...>
+Signed-off-by: Shawn Guo <sha...@li...>
+---
+ arch/arm/mach-imx/clk-imx6q.c | 1 +
+ include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
+index 6843ea9..e59e2c6 100644
+--- a/arch/arm/mach-imx/clk-imx6q.c
++++ b/arch/arm/mach-imx/clk-imx6q.c
+@@ -418,6 +418,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
+ clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
+ clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
+ clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg);
++ clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);
+ if (cpu_is_imx6dl())
+ /*
+ * The multiplexer and divider of the imx6q clock gpu2d get
+diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
+index 25625bf..dbc828c 100644
+--- a/include/dt-bindings/clock/imx6qdl-clock.h
++++ b/include/dt-bindings/clock/imx6qdl-clock.h
+@@ -249,6 +249,7 @@
+ #define IMX6QDL_PLL7_BYPASS 236
+ #define IMX6QDL_CLK_GPT_3M 237
+ #define IMX6QDL_CLK_VIDEO_27M 238
+-#define IMX6QDL_CLK_END 239
++#define IMX6QDL_CLK_MIPI_CORE_CFG 239
++#define IMX6QDL_CLK_END 240
+
+ #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
+--
+2.7.3
+
diff --git a/patches/linux/3.19/0714-ARM-imx6q-clk-Add-support-for-mipi_ipg-clock-as-a-sh.patch b/patches/linux/3.19/0714-ARM-imx6q-clk-Add-support-for-mipi_ipg-clock-as-a-sh.patch
new file mode 100644
index 0000000..089a34a
--- /dev/null
+++ b/patches/linux/3.19/0714-ARM-imx6q-clk-Add-support-for-mipi_ipg-clock-as-a-sh.patch
@@ -0,0 +1,48 @@
+From e654df7a1a4843429b5d1d6ee40cac9ecef75304 Mon Sep 17 00:00:00 2001
+From: Liu Ying <Yin...@fr...>
+Date: Thu, 12 Feb 2015 14:01:30 +0800
+Subject: [PATCH 4/4] ARM: imx6q: clk: Add support for mipi_ipg clock as a
+ shared clock gate
+
+The CG8 field of the CCM CCGR3 register is the 'mipi_core_cfg' gate clock,
+according to the i.MX6q/sdl reference manuals. This clock is actually the
+gate for several clocks, including the ipg clock's output. The MIPI DSI host
+controller embedded in the i.MX6q/sdl SoCs takes the ipg clock as the pclk -
+the APB clock signal . In order to gate/ungate the ipg clock, this patch adds
+a new shared clock gate named as "mipi_ipg".
+
+Signed-off-by: Liu Ying <Yin...@fr...>
+Signed-off-by: Shawn Guo <sha...@li...>
+---
+ arch/arm/mach-imx/clk-imx6q.c | 1 +
+ include/dt-bindings/clock/imx6qdl-clock.h | 3 ++-
+ 2 files changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
+index e59e2c6..469a150 100644
+--- a/arch/arm/mach-imx/clk-imx6q.c
++++ b/arch/arm/mach-imx/clk-imx6q.c
+@@ -419,6 +419,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
+ clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
+ clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg);
+ clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);
++ clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg);
+ if (cpu_is_imx6dl())
+ /*
+ * The multiplexer and divider of the imx6q clock gpu2d get
+diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
+index dbc828c..8780868 100644
+--- a/include/dt-bindings/clock/imx6qdl-clock.h
++++ b/include/dt-bindings/clock/imx6qdl-clock.h
+@@ -250,6 +250,7 @@
+ #define IMX6QDL_CLK_GPT_3M 237
+ #define IMX6QDL_CLK_VIDEO_27M 238
+ #define IMX6QDL_CLK_MIPI_CORE_CFG 239
+-#define IMX6QDL_CLK_END 240
++#define IMX6QDL_CLK_MIPI_IPG 240
++#define IMX6QDL_CLK_END 241
+
+ #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
+--
+2.7.3
+
diff --git a/patches/linux/3.19/0715-clk-imx6-refine-hdmi_isfr-s-parent-to-make-HDMI-work.patch b/patches/linux/3.19/0715-clk-imx6-refine-hdmi_isfr-s-parent-to-make-HDMI-work.patch
new file mode 100644
index 0000000..0c3cf55
--- /dev/null
+++ b/patches/linux/3.19/0715-clk-imx6-refine-hdmi_isfr-s-parent-to-make-HDMI-work.patch
@@ -0,0 +1,50 @@
+From ad681a6629d462a154941605c9fd76c70bbb1d6d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?S=C3=A9bastien=20Szymanski?=
+ <seb...@ar...>
+Date: Tue, 1 Aug 2017 12:08:24 +0200
+Subject: [PATCH 1/1] clk: imx6: refine hdmi_isfr's parent to make HDMI work on
+ i.MX6 SoCs w/o VPU
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On i.MX6 SoCs without VPU (in my case MCIMX6D4AVT10AC), the hdmi driver
+fails to probe:
+
+[ 2.540030] dwhdmi-imx 120000.hdmi: Unsupported HDMI controller
+(0000:00:00)
+[ 2.548199] imx-drm display-subsystem: failed to bind 120000.hdmi
+(ops dw_hdmi_imx_ops): -19
+[ 2.557403] imx-drm display-subsystem: master bind failed: -19
+
+That's because hdmi_isfr's parent, video_27m, is not correctly ungated.
+As explained in commit 5ccc248cc537 ("ARM: imx6q: clk: Add support for
+mipi_core_cfg clock as a shared clock gate"), video_27m is gated by
+CCM_CCGR3[CG8].
+
+On i.MX6 SoCs with VPU, the hdmi is working thanks to the
+CCM_CMEOR[mod_en_ov_vpu] bit which makes the video_27m ungated whatever
+is in CCM_CCGR3[CG8]. The issue can be reproduced by setting
+CCMEOR[mod_en_ov_vpu] to 0.
+
+Make the HDMI work in every case by setting hdmi_isfr's parent to
+mipi_core_cfg.
+
+Signed-off-by: Sébastien Szymanski <seb...@ar...>
+---
+ drivers/clk/imx/clk-imx6q.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+Index: linux-3.19.8/arch/arm/mach-imx/clk-imx6q.c
+===================================================================
+--- linux-3.19.8.orig/arch/arm/mach-imx/clk-imx6q.c
++++ linux-3.19.8/arch/arm/mach-imx/clk-imx6q.c
+@@ -402,7 +402,7 @@ static void __init imx6q_clocks_init(str
+ clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
+ clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
+ clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
+- clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "video_27m", base + 0x70, 4);
++ clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "mipi_core_cfg", base + 0x70, 4);
+ clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6);
+ clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8);
+ clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
hooks/post-receive
--
armadeus
|