[Armadeus-commitlog] armadeus branch, master, updated. armadeus-6.0-58-g3efba30
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-6.0-58-g3efba30
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From: Julien B a. A. <ar...@us...> - 2016-04-08 14:18:41
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 3efba309430306807c3c2154021194cc8179acf3 (commit)
via ce93f9267fd340675b48913689a260b807d1fc44 (commit)
from 260561965a3fa4589581b5339bbe63e35dcf5e79 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 3efba309430306807c3c2154021194cc8179acf3
Author: Julien BOIBESSOT <jul...@ar...>
Date: Fri Apr 8 16:03:02 2016 +0200
[BUILDROOT] Add imxregs to most APF6 configs
commit ce93f9267fd340675b48913689a260b807d1fc44
Author: Julien BOIBESSOT <jul...@ar...>
Date: Fri Apr 8 15:58:44 2016 +0200
[TOOLS] Add some i.MX6 IPU registers to imxregs
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf6_defconfig | 1 +
buildroot/configs/apf6failsafe_defconfig | 1 +
buildroot/configs/apf6legacy-preempt-rt_defconfig | 1 +
buildroot/configs/apf6legacy_defconfig | 1 +
buildroot/configs/apf6xenomai_defconfig | 1 +
target/linux/debug/imxregs/imx6regs.h | 76 +++++++++++++++++++-
6 files changed, 77 insertions(+), 4 deletions(-)
diff --git a/buildroot/configs/apf6_defconfig b/buildroot/configs/apf6_defconfig
index 8be3378..17c3244 100644
--- a/buildroot/configs/apf6_defconfig
+++ b/buildroot/configs/apf6_defconfig
@@ -37,6 +37,7 @@ BR2_LINUX_KERNEL_INTREE_DTS_NAME="imx6q-apf6dev imx6dl-apf6dev"
BR2_LINUX_KERNEL_INSTALL_TARGET=y
BR2_PACKAGE_BUSYBOX_CONFIG="$(ARMADEUS_PATH)/busybox.config"
BR2_PACKAGE_BUSYBOX_SHOW_OTHERS=y
+BR2_PACKAGE_IMXREGS=y
BR2_PACKAGE_ALSA_UTILS=y
BR2_PACKAGE_ALSA_UTILS_AMIXER=y
BR2_PACKAGE_ALSA_UTILS_APLAY=y
diff --git a/buildroot/configs/apf6failsafe_defconfig b/buildroot/configs/apf6failsafe_defconfig
index 56d2ea7..e278fa9 100644
--- a/buildroot/configs/apf6failsafe_defconfig
+++ b/buildroot/configs/apf6failsafe_defconfig
@@ -35,6 +35,7 @@ BR2_LINUX_KERNEL_ZIMAGE=y
BR2_LINUX_KERNEL_DTS_SUPPORT=y
BR2_LINUX_KERNEL_INTREE_DTS_NAME="imx6q-apf6dev imx6dl-apf6dev"
BR2_PACKAGE_BUSYBOX_CONFIG="$(ARMADEUS_PATH)/busybox.config"
+BR2_PACKAGE_IMXREGS=y
BR2_PACKAGE_PV=y
BR2_PACKAGE_E2FSPROGS=y
BR2_PACKAGE_E2FSPROGS_E4DEFRAG=y
diff --git a/buildroot/configs/apf6legacy-preempt-rt_defconfig b/buildroot/configs/apf6legacy-preempt-rt_defconfig
index 926aed4..5d3b9ad 100644
--- a/buildroot/configs/apf6legacy-preempt-rt_defconfig
+++ b/buildroot/configs/apf6legacy-preempt-rt_defconfig
@@ -37,6 +37,7 @@ BR2_LINUX_KERNEL_DTS_SUPPORT=y
BR2_LINUX_KERNEL_INTREE_DTS_NAME="imx6q-apf6dev imx6dl-apf6dev imx6q-wandboard imx6dl-wandboard"
BR2_LINUX_KERNEL_INSTALL_TARGET=y
BR2_PACKAGE_BUSYBOX_CONFIG="$(ARMADEUS_PATH)/busybox.config"
+BR2_PACKAGE_IMXREGS=y
BR2_PACKAGE_ALSA_UTILS=y
BR2_PACKAGE_ALSA_UTILS_AMIXER=y
BR2_PACKAGE_ALSA_UTILS_APLAY=y
diff --git a/buildroot/configs/apf6legacy_defconfig b/buildroot/configs/apf6legacy_defconfig
index 71642b8..5c8f932 100644
--- a/buildroot/configs/apf6legacy_defconfig
+++ b/buildroot/configs/apf6legacy_defconfig
@@ -37,6 +37,7 @@ BR2_LINUX_KERNEL_DTS_SUPPORT=y
BR2_LINUX_KERNEL_INTREE_DTS_NAME="imx6q-apf6dev imx6dl-apf6dev imx6q-wandboard imx6dl-wandboard"
BR2_LINUX_KERNEL_INSTALL_TARGET=y
BR2_PACKAGE_BUSYBOX_CONFIG="$(ARMADEUS_PATH)/busybox.config"
+BR2_PACKAGE_IMXREGS=y
BR2_PACKAGE_ALSA_UTILS=y
BR2_PACKAGE_ALSA_UTILS_AMIXER=y
BR2_PACKAGE_ALSA_UTILS_APLAY=y
diff --git a/buildroot/configs/apf6xenomai_defconfig b/buildroot/configs/apf6xenomai_defconfig
index 2d920db..1d665df 100644
--- a/buildroot/configs/apf6xenomai_defconfig
+++ b/buildroot/configs/apf6xenomai_defconfig
@@ -38,6 +38,7 @@ BR2_LINUX_KERNEL_INSTALL_TARGET=y
BR2_PACKAGE_BUSYBOX_CONFIG="$(ARMADEUS_PATH)/busybox.config"
BR2_LINUX_KERNEL_EXT_XENOMAI=y
BR2_LINUX_KERNEL_EXT_XENOMAI_ADEOS_PATCH_URL="http://download.gna.org/adeos/patches/v3.x/arm/ipipe-core-3.10.32-arm-7.patch"
+BR2_PACKAGE_IMXREGS=y
BR2_PACKAGE_ALSA_UTILS=y
BR2_PACKAGE_ALSA_UTILS_AMIXER=y
BR2_PACKAGE_ALSA_UTILS_APLAY=y
diff --git a/target/linux/debug/imxregs/imx6regs.h b/target/linux/debug/imxregs/imx6regs.h
index b058aae..246b97a 100644
--- a/target/linux/debug/imxregs/imx6regs.h
+++ b/target/linux/debug/imxregs/imx6regs.h
@@ -1,8 +1,8 @@
/*
- * imx6qdlregs.h - i.MX6 registers definition
+ * imx6regs.h - i.MX6 registers definition
*
- * Copyright (C) 2015 Armadeus Systems
- * Author: Sébastien Szymanski
+ * Copyright (C) 2015-2016 Armadeus Systems
+ * Authors: Sébastien Szymanski, Julien Boibessot
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -29,7 +29,75 @@ static struct reg_info regs[] =
{ "CCM_ANALOG_PLL_ENET", 0x020C80E0, 0, 0xffffffff, 'x', "CCM_ANALOG_PLL_ENET" },
{ "CCM_ANALOG_MISC1", 0x020C8160, 0, 0xffffffff, 'x', "CCM_ANALOG_MISC1" },
{ "PMU_MISC1", 0x020C8160, 0, 0xffffffff, 'x', "PMU_MISC1" },
-{ "PMU_MISC2", 0x020C8170, 0, 0xffffffff, 'x', "PMU_MISC2" }
+{ "PMU_MISC2", 0x020C8170, 0, 0xffffffff, 'x', "PMU_MISC2" },
+
+{ "CSI2IPU_SW_RST", 0x021dcf00, 0, 0xffffffff, 'x', "CSI 2 IPU Gasket Software Reset" },
+
+{ "IPU1_CONF", 0x02600000, 0, 0xffffffff, 'x', "IPU1 (#0) Configuration (S/Dl/D/Q)" },
+{ "IPU1_INT_CTRL_1", 0x0260003c, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 1" },
+{ "IPU1_INT_CTRL_2", 0x02600040, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 2" },
+{ "IPU1_INT_CTRL_3", 0x02600044, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 3" },
+{ "IPU1_INT_CTRL_4", 0x02600048, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 4" },
+{ "IPU1_INT_CTRL_5", 0x0260004c, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 5" },
+{ "IPU1_INT_CTRL_6", 0x02600050, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 6" },
+{ "IPU1_INT_CTRL_7", 0x02600054, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 7" },
+{ "IPU1_INT_CTRL_8", 0x02600058, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 8" },
+{ "IPU1_INT_CTRL_9", 0x0260005c, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 9" },
+{ "IPU1_INT_CTRL_10", 0x02600060, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 10" },
+{ "IPU1_INT_CTRL_11", 0x02600064, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 11" },
+{ "IPU1_INT_CTRL_12", 0x02600068, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 12" },
+{ "IPU1_INT_CTRL_13", 0x0260006c, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 13" },
+{ "IPU1_INT_CTRL_14", 0x02600070, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 14" },
+{ "IPU1_INT_CTRL_15", 0x02600074, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Control Register 15" },
+
+{ "IPU1_INT_STAT_1", 0x02600200, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 1" },
+{ "IPU1_INT_STAT_2", 0x02600204, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 2" },
+{ "IPU1_INT_STAT_3", 0x02600208, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 3" },
+{ "IPU1_INT_STAT_4", 0x0260020c, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 4" },
+{ "IPU1_INT_STAT_5", 0x02600210, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 5" },
+{ "IPU1_INT_STAT_6", 0x02600214, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 6" },
+{ "IPU1_INT_STAT_7", 0x02600218, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 7" },
+{ "IPU1_INT_STAT_8", 0x0260021c, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 8" },
+{ "IPU1_INT_STAT_9", 0x02600220, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 9" },
+{ "IPU1_INT_STAT_10", 0x02600224, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 10" },
+{ "IPU1_INT_STAT_11", 0x02600228, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 11" },
+{ "IPU1_INT_STAT_12", 0x0260022c, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 12" },
+{ "IPU1_INT_STAT_13", 0x02600230, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 13" },
+{ "IPU1_INT_STAT_14", 0x02600234, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 14" },
+{ "IPU1_INT_STAT_15", 0x02600238, 0, 0xffffffff, 'x', "IPU1 (#0) Interrupt Status Register 15" },
+
+{ "IPU1_IDMAC_CONF", 0x02608000, 0, 0xffffffff, 'x', "IPU1 (#0) IDMAC Configuration Register" },
+{ "IPU1_IDMAC_CH_EN_1", 0x02608004, 0, 0xffffffff, 'x', "IPU1 (#0) IDMAC Channel Enable 1 Register" },
+{ "IPU1_IDMAC_CH_EN_2", 0x02608008, 0, 0xffffffff, 'x', "IPU1 (#0) IDMAC Channel Enable 2 Register" },
+{ "IPU1_IDMAC_CH_PRI_1", 0x02608014, 0, 0xffffffff, 'x', "IPU1 (#0) IDMAC Channel Priority 1 Register" },
+{ "IPU1_IDMAC_CH_PRI_2", 0x02608018, 0, 0xffffffff, 'x', "IPU1 (#0) IDMAC Channel Priority 2 Register" },
+{ "IPU1_IDMAC_BNDM_EN_1", 0x02608040, 0, 0xffffffff, 'x', "IPU1 (#0) IDMAC Band Mode Enable 1 Register" },
+{ "IPU1_IDMAC_BNDM_EN_2", 0x02608044, 0, 0xffffffff, 'x', "IPU1 (#0) IDMAC Band Mode Enable 2 Register" },
+
+{ "IPU1_FS_PROC_FLOW_1", 0x026000a8, 0, 0xffffffff, 'x', "IPU1 (#0) FSU Processing Flow 1 Register" },
+{ "IPU1_FS_PROC_FLOW_2", 0x026000ac, 0, 0xffffffff, 'x', "IPU1 (#0) FSU Processing Flow 2 Register" },
+{ "IPU1_FS_PROC_FLOW_3", 0x026000b0, 0, 0xffffffff, 'x', "IPU1 (#0) FSU Processing Flow 3 Register" },
+{ "IPU1_FS_DISP_FLOW_1", 0x026000b4, 0, 0xffffffff, 'x', "IPU1 (#0) FSU Displaying Flow 1 Register" },
+{ "IPU1_FS_DISP_FLOW_2", 0x026000b8, 0, 0xffffffff, 'x', "IPU1 (#0) FSU Displaying Flow 2 Register" },
+
+{ "IPU1_IC_CONF", 0x02620000, 0, 0xffffffff, 'x', "IPU1 (#0) IC Configuration Register" },
+
+{ "IPU1_CSI0_SENS_CONF", 0x02630000, 0, 0xffffffff, 'x', "IPU1 (#0) CSI0 Sensor Configuration Register" },
+{ "IPU1_CSI0_SENS_FRM_SIZE", 0x02630004, 0, 0xffffffff, 'x', "IPU1 (#0) CSI0 Sensor Frame Size Register" },
+{ "IPU1_CSI0_ACT_FRM_SIZE", 0x02630008, 0, 0xffffffff, 'x', "IPU1 (#0) CSI0 Actual Frame Size Register" },
+{ "IPU1_CSI0_OUT_FRM_CTRL", 0x0263000c, 0, 0xffffffff, 'x', "IPU1 (#0) CSI0 Output Control Register" },
+{ "IPU1_CSI0_TST_CTRL", 0x02630010, 0, 0xffffffff, 'x', "IPU1 (#0) CSI0 Test Control Register" },
+{ "IPU1_CSI0_DI", 0x02630020, 0, 0xffffffff, 'x', "IPU1 (#0) CSI0 Data Identifier Register" },
+
+{ "IPU1_CSI1_SENS_CONF", 0x02638000, 0, 0xffffffff, 'x', "IPU1 (#0) CSI1 Sensor Configuration Register" },
+{ "IPU1_CSI1_SENS_FRM_SIZE", 0x02638004, 0, 0xffffffff, 'x', "IPU1 (#0) CSI1 Sensor Frame Size Register" },
+{ "IPU1_CSI1_ACT_FRM_SIZE", 0x02638008, 0, 0xffffffff, 'x', "IPU1 (#0) CSI1 Actual Frame Size Register" },
+{ "IPU1_CSI1_OUT_FRM_CTRL", 0x0263800c, 0, 0xffffffff, 'x', "IPU1 (#0) CSI1 Output Control Register" },
+{ "IPU1_CSI1_TST_CTRL", 0x02638010, 0, 0xffffffff, 'x', "IPU1 (#0) CSI1 Test Control Register" },
+{ "IPU1_CSI1_DI", 0x02638020, 0, 0xffffffff, 'x', "IPU1 (#0) CSI1 Data Identifier Register" },
+
+{ "IPU2_CONF", 0x02a00000, 0, 0xffffffff, 'x', "IPU2 (#1) Configuration (D/Q)" },
+{ "IPU2_IC_CONF", 0x02a20000, 0, 0xffffffff, 'x', "IPU2 (#1) IC Configuration Register" },
// The following registers have to be tested
//{ "AUDMUX_PDCR1", 0x021D8004, 0, 0xffffffff, 'x', "AUDMUX_PDCR1" },
hooks/post-receive
--
armadeus
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