[Armadeus-commitlog] armadeus branch, master, updated. armadeus-6.0-45-g386909e
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-6.0-45-g386909e
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From: Fabien M <fa...@us...> - 2016-03-21 13:59:04
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The branch, master has been updated
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via e11f40c6a00a7ef186c980e0291657608cd0a0fd (commit)
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- Log -----------------------------------------------------------------
commit 386909eb94da650dc40504cb2c9ac686d731b47b
Merge: e11f40c bd12409
Author: Fabien Marteau <fab...@ar...>
Date: Mon Mar 21 14:58:32 2016 +0100
Merge branch 'master' of ssh://git.code.sf.net/p/armadeus/code
commit e11f40c6a00a7ef186c980e0291657608cd0a0fd
Author: Fabien Marteau <fab...@ar...>
Date: Mon Mar 21 14:57:50 2016 +0100
firmware: simple blinking led example for apf6sp code
-----------------------------------------------------------------------
Summary of changes:
.../blinking_led/src/cycloneV/led_pcie_pll.vhd | 55 ++++++++++++
.../leds/blinking_led/src/cycloneV/pcie_pll.vhd | 40 +++++++++
.../leds/blinking_led/src/cycloneV/pcie_pll_0002.v | 87 ++++++++++++++++++++
firmware/leds/blinking_led/src/cycloneV/pinout.tcl | 7 ++
4 files changed, 189 insertions(+), 0 deletions(-)
create mode 100644 firmware/leds/blinking_led/src/cycloneV/led_pcie_pll.vhd
create mode 100644 firmware/leds/blinking_led/src/cycloneV/pcie_pll.vhd
create mode 100644 firmware/leds/blinking_led/src/cycloneV/pcie_pll_0002.v
create mode 100644 firmware/leds/blinking_led/src/cycloneV/pinout.tcl
diff --git a/firmware/leds/blinking_led/src/cycloneV/led_pcie_pll.vhd b/firmware/leds/blinking_led/src/cycloneV/led_pcie_pll.vhd
new file mode 100644
index 0000000..587a190
--- /dev/null
+++ b/firmware/leds/blinking_led/src/cycloneV/led_pcie_pll.vhd
@@ -0,0 +1,55 @@
+library IEEE;
+ use IEEE.STD_LOGIC_1164.ALL;
+ use IEEE.numeric_std.all;
+
+ entity led is
+ Port (
+ clk : in std_logic;
+ led : out std_logic
+ );
+ end led;
+
+ architecture RTL of led is
+ constant max_count : natural := 48000000;
+ signal Rst : std_logic;
+ signal gclk : std_logic;
+
+ component pcie_pll
+ port (
+ refclk : in std_logic;
+ rst : in std_logic;
+ outclk_0 : out std_logic
+ );
+ end component pcie_pll;
+
+ begin
+
+ connect_pcie_pll : pcie_pll
+ port map (
+ refclk => clk,
+ rst => Rst,
+ outclk_0 => gclk);
+
+ Rst <= '0';
+
+ -- 0 to max_count counter
+ compteur : process(gclk, Rst)
+ variable count : natural range 0 to max_count;
+ begin
+ if Rst = '1' then
+ count := 0;
+ led <= '0';
+ elsif rising_edge(gclk) then
+ if count < max_count/2 then
+ count := count + 1;
+ led <= '1';
+ elsif count < max_count then
+ count := count + 1;
+ led <= '0';
+ else
+ count := 0;
+ led <= '0';
+ end if;
+ end if;
+ end process compteur;
+ end RTL;
diff --git a/firmware/leds/blinking_led/src/cycloneV/pcie_pll.vhd b/firmware/leds/blinking_led/src/cycloneV/pcie_pll.vhd
new file mode 100644
index 0000000..4452c72
--- /dev/null
+++ b/firmware/leds/blinking_led/src/cycloneV/pcie_pll.vhd
@@ -0,0 +1,40 @@
+-- megafunction wizard: %Altera PLL v15.1%
+-- GENERATION: XML
+-- pcie_pll.vhd
+
+-- Generated using ACDS version 15.1 189
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity pcie_pll is
+ port (
+ refclk : in std_logic := '0'; -- refclk.clk
+ rst : in std_logic := '0'; -- reset.reset
+ outclk_0 : out std_logic -- outclk0.clk
+ );
+end entity pcie_pll;
+
+architecture rtl of pcie_pll is
+ component pcie_pll_0002 is
+ port (
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X'; -- reset
+ outclk_0 : out std_logic; -- clk
+ locked : out std_logic -- export
+ );
+ end component pcie_pll_0002;
+
+begin
+
+ pcie_pll_inst : component pcie_pll_0002
+ port map (
+ refclk => refclk, -- refclk.clk
+ rst => rst, -- reset.reset
+ outclk_0 => outclk_0, -- outclk0.clk
+ locked => open -- (terminated)
+ );
+
+end architecture rtl; -- of pcie_pll
+
diff --git a/firmware/leds/blinking_led/src/cycloneV/pcie_pll_0002.v b/firmware/leds/blinking_led/src/cycloneV/pcie_pll_0002.v
new file mode 100644
index 0000000..4cee86c
--- /dev/null
+++ b/firmware/leds/blinking_led/src/cycloneV/pcie_pll_0002.v
@@ -0,0 +1,87 @@
+`timescale 1ns/10ps
+module pcie_pll_0002(
+
+ // interface 'refclk'
+ input wire refclk,
+
+ // interface 'reset'
+ input wire rst,
+
+ // interface 'outclk0'
+ output wire outclk_0,
+
+ // interface 'locked'
+ output wire locked
+);
+
+ altera_pll #(
+ .fractional_vco_multiplier("false"),
+ .reference_clock_frequency("125.0 MHz"),
+ .operation_mode("direct"),
+ .number_of_clocks(1),
+ .output_clock_frequency0("62.500000 MHz"),
+ .phase_shift0("0 ps"),
+ .duty_cycle0(50),
+ .output_clock_frequency1("0 MHz"),
+ .phase_shift1("0 ps"),
+ .duty_cycle1(50),
+ .output_clock_frequency2("0 MHz"),
+ .phase_shift2("0 ps"),
+ .duty_cycle2(50),
+ .output_clock_frequency3("0 MHz"),
+ .phase_shift3("0 ps"),
+ .duty_cycle3(50),
+ .output_clock_frequency4("0 MHz"),
+ .phase_shift4("0 ps"),
+ .duty_cycle4(50),
+ .output_clock_frequency5("0 MHz"),
+ .phase_shift5("0 ps"),
+ .duty_cycle5(50),
+ .output_clock_frequency6("0 MHz"),
+ .phase_shift6("0 ps"),
+ .duty_cycle6(50),
+ .output_clock_frequency7("0 MHz"),
+ .phase_shift7("0 ps"),
+ .duty_cycle7(50),
+ .output_clock_frequency8("0 MHz"),
+ .phase_shift8("0 ps"),
+ .duty_cycle8(50),
+ .output_clock_frequency9("0 MHz"),
+ .phase_shift9("0 ps"),
+ .duty_cycle9(50),
+ .output_clock_frequency10("0 MHz"),
+ .phase_shift10("0 ps"),
+ .duty_cycle10(50),
+ .output_clock_frequency11("0 MHz"),
+ .phase_shift11("0 ps"),
+ .duty_cycle11(50),
+ .output_clock_frequency12("0 MHz"),
+ .phase_shift12("0 ps"),
+ .duty_cycle12(50),
+ .output_clock_frequency13("0 MHz"),
+ .phase_shift13("0 ps"),
+ .duty_cycle13(50),
+ .output_clock_frequency14("0 MHz"),
+ .phase_shift14("0 ps"),
+ .duty_cycle14(50),
+ .output_clock_frequency15("0 MHz"),
+ .phase_shift15("0 ps"),
+ .duty_cycle15(50),
+ .output_clock_frequency16("0 MHz"),
+ .phase_shift16("0 ps"),
+ .duty_cycle16(50),
+ .output_clock_frequency17("0 MHz"),
+ .phase_shift17("0 ps"),
+ .duty_cycle17(50),
+ .pll_type("General"),
+ .pll_subtype("General")
+ ) altera_pll_i (
+ .rst (rst),
+ .outclk ({outclk_0}),
+ .locked (locked),
+ .fboutclk ( ),
+ .fbclk (1'b0),
+ .refclk (refclk)
+ );
+endmodule
+
diff --git a/firmware/leds/blinking_led/src/cycloneV/pinout.tcl b/firmware/leds/blinking_led/src/cycloneV/pinout.tcl
new file mode 100644
index 0000000..6888a18
--- /dev/null
+++ b/firmware/leds/blinking_led/src/cycloneV/pinout.tcl
@@ -0,0 +1,7 @@
+# HSMC_D0 -> PIN_M10
+set_location_assignment PIN_M10 -to led
+
+# PCIE_CLK
+set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to clk
+set_location_assignment PIN_V4 -to clk
+set_location_assignment PIN_U4 -to "clk(n)"
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armadeus
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