[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-741-g00938a7
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-741-g00938a7
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From: Sébastien S. <ss...@us...> - 2015-05-19 10:07:16
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 00938a7708df22802bed7dabafbdb99bc143ae61 (commit)
via 5bb741d06c88866be2bc43267ca34e3744c7fe6b (commit)
from 6e2814c011f731e1cc692dc4fbd43ca73ab720c3 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 00938a7708df22802bed7dabafbdb99bc143ae61
Author: Sébastien Szymanski <seb...@ar...>
Date: Tue May 19 12:12:26 2015 +0200
[DEBUG] imxregs: add apf6 support
commit 5bb741d06c88866be2bc43267ca34e3744c7fe6b
Author: Sébastien Szymanski <seb...@ar...>
Date: Mon May 18 19:13:12 2015 +0200
[LINUX] 3.19: apf6: enable sata_ref_100M clock.
-----------------------------------------------------------------------
Summary of changes:
buildroot/package/armadeus/imxregs/imxregs.mk | 16 +-
.../0700-armadeus-pcie_clk_defined_in_uboot.patch | 25 +-
target/linux/debug/imxregs/Makefile | 5 +-
target/linux/debug/imxregs/imx6regs.h | 1185 ++++++++++++++++++++
target/linux/debug/imxregs/imxregs.c | 10 +-
5 files changed, 1213 insertions(+), 28 deletions(-)
create mode 100644 target/linux/debug/imxregs/imx6regs.h
diff --git a/buildroot/package/armadeus/imxregs/imxregs.mk b/buildroot/package/armadeus/imxregs/imxregs.mk
index ad071a0..a0bcdeb 100644
--- a/buildroot/package/armadeus/imxregs/imxregs.mk
+++ b/buildroot/package/armadeus/imxregs/imxregs.mk
@@ -4,13 +4,9 @@
#
#############################################################
-IMXREGS_VERSION = 2013.05
+IMXREGS_VERSION = 2015.05
IMXREGS_SITE = $(TOPDIR)/../target/linux/debug/imxregs/
-ifeq ($(generic-package), )
-IMXREGS_SITE_METHOD = copy
-else
IMXREGS_SITE_METHOD = local
-endif
IMXREGS_LICENSE = GPLv2+
IMXREGS_LICENSE_FILES = COPYING
@@ -26,14 +22,4 @@ define IMXREGS_INSTALL_TARGET_CMDS
install -D $(@D)/$(IMXREGS_BINARY) $(IMXREGS_TARGET_BINARY)
endef
-define IMXREGS_CLEAN_CMDS
- rm -f $(IMXREGS_TARGET_BINARY)
- $(MAKE) -C $(@D) clean
-endef
-
-ifeq ($(generic-package), )
-$(eval $(call GENTARGETS))
-else
$(eval $(generic-package))
-endif
-
diff --git a/patches/linux/3.19/0700-armadeus-pcie_clk_defined_in_uboot.patch b/patches/linux/3.19/0700-armadeus-pcie_clk_defined_in_uboot.patch
index 28395fd..0590740 100644
--- a/patches/linux/3.19/0700-armadeus-pcie_clk_defined_in_uboot.patch
+++ b/patches/linux/3.19/0700-armadeus-pcie_clk_defined_in_uboot.patch
@@ -1,21 +1,28 @@
Do not configure PCIe clock with Linux. PCIe Frequency clock is configured
under U-Boot.
+Enable sata_ref_100M clock. It's needed to have PCIe registers access.
-Signed-off-by: Fabien Marteau <fab...@ar...>
+Signed-off-by: Fabien Marteau <fab...@ar...>
+Signed-off-by: Sébastien Szymanski <seb...@ar...>
---
-Index: linux-4.0-rc1/arch/arm/mach-imx/clk-imx6q.c
+Index: linux-3.19.3/arch/arm/mach-imx/clk-imx6q.c
===================================================================
---- linux-4.0-rc1.orig/arch/arm/mach-imx/clk-imx6q.c 2015-04-22 16:21:27.538399032 +0200
-+++ linux-4.0-rc1/arch/arm/mach-imx/clk-imx6q.c 2015-04-22 16:23:15.822395833 +0200
-@@ -522,7 +522,9 @@
+--- linux-3.19.3.orig/arch/arm/mach-imx/clk-imx6q.c
++++ linux-3.19.3/arch/arm/mach-imx/clk-imx6q.c
+@@ -522,8 +522,13 @@ static void __init imx6q_clocks_init(str
clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]);
/* All existing boards with PCIe use LVDS1 */
- if (IS_ENABLED(CONFIG_PCI_IMX6))
-+ if ( IS_ENABLED(CONFIG_PCI_IMX6)
-+ && !of_machine_is_compatible("armadeus,imx6dl-apf6")
-+ && !of_machine_is_compatible("armadeus,imx6q-apf6"))
- clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
+- clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
++ if (IS_ENABLED(CONFIG_PCI_IMX6)) {
++ if (of_machine_is_compatible("armadeus,imx6dl-apf6") ||
++ of_machine_is_compatible("armadeus,imx6q-apf6"))
++ clk_prepare_enable(clk[IMX6QDL_CLK_SATA_REF_100M]);
++ else
++ clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]);
++ }
/* Set initial power mode */
+ imx6q_set_lpm(WAIT_CLOCKED);
diff --git a/target/linux/debug/imxregs/Makefile b/target/linux/debug/imxregs/Makefile
index 7ddb6f0..3b4fe9f 100644
--- a/target/linux/debug/imxregs/Makefile
+++ b/target/linux/debug/imxregs/Makefile
@@ -3,7 +3,7 @@ ARMADEUS_BASE_DIR=../../../..
CC = $(ARMADEUS_TOOLCHAIN_PATH)/$(ARMADEUS_TOOLCHAIN_PREFIX)gcc
-EXECS = imxlregs imx27regs imx28regs imx51regs imx53regs
+EXECS = imxlregs imx27regs imx28regs imx51regs imx53regs imx6regs
all: $(EXECS)
@@ -22,6 +22,9 @@ imx51regs: imxregs.c imx5regs.h definitions.h
imx53regs: imxregs.c imx5regs.h definitions.h
$(CC) -DIMX53 imxregs.c -o $@
+imx6regs: imxregs.c imx6regs.h definitions.h
+ $(CC) -DIMX6 imxregs.c -o $@
+
clean:
rm -f *.o
rm -f $(EXECS)
diff --git a/target/linux/debug/imxregs/imx6regs.h b/target/linux/debug/imxregs/imx6regs.h
new file mode 100644
index 0000000..b058aae
--- /dev/null
+++ b/target/linux/debug/imxregs/imx6regs.h
@@ -0,0 +1,1185 @@
+/*
+ * imx6qdlregs.h - i.MX6 registers definition
+ *
+ * Copyright (C) 2015 Armadeus Systems
+ * Author: Sébastien Szymanski
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include "definitions.h"
+
+#define IMX_TYPE "i.MX6"
+
+static struct reg_info regs[] =
+{
+{ "CCM_ANALOG_PLL_ENET", 0x020C80E0, 0, 0xffffffff, 'x', "CCM_ANALOG_PLL_ENET" },
+{ "CCM_ANALOG_MISC1", 0x020C8160, 0, 0xffffffff, 'x', "CCM_ANALOG_MISC1" },
+{ "PMU_MISC1", 0x020C8160, 0, 0xffffffff, 'x', "PMU_MISC1" },
+{ "PMU_MISC2", 0x020C8170, 0, 0xffffffff, 'x', "PMU_MISC2" }
+
+// The following registers have to be tested
+//{ "AUDMUX_PDCR1", 0x021D8004, 0, 0xffffffff, 'x', "AUDMUX_PDCR1" },
+//{ "AUDMUX_PDCR2", 0x021D800C, 0, 0xffffffff, 'x', "AUDMUX_PDCR2" },
+//{ "AUDMUX_PDCR3", 0x021D8014, 0, 0xffffffff, 'x', "AUDMUX_PDCR3" },
+//{ "AUDMUX_PDCR4", 0x021D801C, 0, 0xffffffff, 'x', "AUDMUX_PDCR4" },
+//{ "AUDMUX_PDCR5", 0x021D8024, 0, 0xffffffff, 'x', "AUDMUX_PDCR5" },
+//{ "AUDMUX_PDCR6", 0x021D802C, 0, 0xffffffff, 'x', "AUDMUX_PDCR6" },
+//{ "AUDMUX_PDCR7", 0x021D8034, 0, 0xffffffff, 'x', "AUDMUX_PDCR7" },
+//{ "AUDMUX_PTCR1", 0x021D8000, 0, 0xffffffff, 'x', "AUDMUX_PTCR1" },
+//{ "AUDMUX_PTCR2", 0x021D8008, 0, 0xffffffff, 'x', "AUDMUX_PTCR2" },
+//{ "AUDMUX_PTCR3", 0x021D8010, 0, 0xffffffff, 'x', "AUDMUX_PTCR3" },
+//{ "DCIC_DCICC", 0x020E4000, 0, 0xffffffff, 'x', "DCIC_DCICC" },
+//{ "DCIC_DCICIC", 0x020E4004, 0, 0xffffffff, 'x', "DCIC_DCICIC" },
+//{ "DCIC_DCICRC", 0x020E4010, 0, 0xffffffff, 'x', "DCIC_DCICRC" },
+//{ "DCIC_DCICRCS", 0x020E401C, 0, 0xffffffff, 'x', "DCIC_DCICRCS" },
+//{ "DCIC_DCICRRS", 0x020E4018, 0, 0xffffffff, 'x', "DCIC_DCICRRS" },
+//{ "DCIC_DCICRS", 0x020E4014, 0, 0xffffffff, 'x', "DCIC_DCICRS" },
+//{ "DCIC_DCICS", 0x020E4008, 0, 0xffffffff, 'x', "DCIC_DCICS" },
+//{ "DVFSC_DVFSCNTR", 0x020DC020, 0, 0xffffffff, 'x', "DVFSC_DVFSCNTR" },
+//{ "DVFSC_DVFSCOUN", 0x020DC004, 0, 0xffffffff, 'x', "DVFSC_DVFSCOUN" },
+//{ "DVFSC_DVFSEMAC", 0x020DC01C, 0, 0xffffffff, 'x', "DVFSC_DVFSEMAC" },
+//{ "DVFSC_DVFSGPBT", 0x020DC018, 0, 0xffffffff, 'x', "DVFSC_DVFSGPBT" },
+//{ "DVFSC_DVFSGPC0", 0x020DC010, 0, 0xffffffff, 'x', "DVFSC_DVFSGPC0" },
+//{ "DVFSC_DVFSGPC1", 0x020DC014, 0, 0xffffffff, 'x', "DVFSC_DVFSGPC1" },
+//{ "DVFSC_DVFSLTR0_0", 0x020DC024, 0, 0xffffffff, 'x', "DVFSC_DVFSLTR0_0" },
+//{ "DVFSC_DVFSLTR0_1", 0x020DC028, 0, 0xffffffff, 'x', "DVFSC_DVFSLTR0_1" },
+//{ "DVFSC_DVFSLTR1_0", 0x020DC02C, 0, 0xffffffff, 'x', "DVFSC_DVFSLTR1_0" },
+//{ "DVFSC_DVFSLTR1_1", 0x020DC030, 0, 0xffffffff, 'x', "DVFSC_DVFSLTR1_1" },
+//{ "DVFSC_DVFSPT0", 0x020DC034, 0, 0xffffffff, 'x', "DVFSC_DVFSPT0" },
+//{ "DVFSC_DVFSPT1", 0x020DC038, 0, 0xffffffff, 'x', "DVFSC_DVFSPT1" },
+//{ "DVFSC_DVFSPT2", 0x020DC03C, 0, 0xffffffff, 'x', "DVFSC_DVFSPT2" },
+//{ "DVFSC_DVFSPT3", 0x020DC040, 0, 0xffffffff, 'x', "DVFSC_DVFSPT3" },
+//{ "DVFSC_DVFSSIG0", 0x020DC00C, 0, 0xffffffff, 'x', "DVFSC_DVFSSIG0" },
+//{ "DVFSC_DVFSSIG1", 0x020DC008, 0, 0xffffffff, 'x', "DVFSC_DVFSSIG1" },
+//{ "DVFSC_DVFSTHRS", 0x020DC000, 0, 0xffffffff, 'x', "DVFSC_DVFSTHRS" },
+//{ "ECSPI1_CONFIGREG", 0x0200800c, 0, 0xffffffff, 'x', "ECSPI1_CONFIGREG" },
+//{ "ECSPI1_CONREG", 0x02008008, 0, 0xffffffff, 'x', "ECSPI1_CONREG" },
+//{ "ECSPI2_CONFIGREG", 0x0200C00c, 0, 0xffffffff, 'x', "ECSPI2_CONFIGREG" },
+//{ "ECSPI2_CONREG", 0x0200C008, 0, 0xffffffff, 'x', "ECSPI2_CONREG" },
+//{ "ECSPI3_CONFIGREG", 0x0201000c, 0, 0xffffffff, 'x', "ECSPI3_CONFIGREG" },
+//{ "ECSPI3_CONREG", 0x02010008, 0, 0xffffffff, 'x', "ECSPI3_CONREG" },
+//{ "ECSPI4_CONFIGREG", 0x0201400c, 0, 0xffffffff, 'x', "ECSPI4_CONFIGREG" },
+//{ "ECSPI4_CONREG", 0x02014008, 0, 0xffffffff, 'x', "ECSPI4_CONREG" },
+//{ "EIM_EAR", 0x021BA098, 0, 0xffffffff, 'x', "EIM_EAR" },
+//{ "EIM_WCR", 0x021BA090, 0, 0xffffffff, 'x', "EIM_WCR" },
+//{ "EIM_WIAR", 0x021BA094, 0, 0xffffffff, 'x', "EIM_WIAR" },
+//{ "ENET_ATCOR", 0x02188410, 0, 0xffffffff, 'x', "ENET_ATCOR" },
+//{ "ENET_ATCR", 0x02188400, 0, 0xffffffff, 'x', "ENET_ATCR" },
+//{ "ENET_ATINC", 0x02188414, 0, 0xffffffff, 'x', "ENET_ATINC" },
+//{ "ENET_ATOFF", 0x02188408, 0, 0xffffffff, 'x', "ENET_ATOFF" },
+//{ "ENET_ATPER", 0x0218840C, 0, 0xffffffff, 'x', "ENET_ATPER" },
+//{ "ENET_ATSTMP", 0x02188418, 0, 0xffffffff, 'x', "ENET_ATSTMP" },
+//{ "ENET_ATVR", 0x02188404, 0, 0xffffffff, 'x', "ENET_ATVR" },
+//{ "ENET_ECR", 0x02188024, 0, 0xffffffff, 'x', "ENET_ECR" },
+//{ "ENET_EIMR", 0x02188008, 0, 0xffffffff, 'x', "ENET_EIMR" },
+//{ "ENET_EIR", 0x02188004, 0, 0xffffffff, 'x', "ENET_EIR" },
+//{ "ENET_FTRL", 0x021881B0, 0, 0xffffffff, 'x', "ENET_FTRL" },
+//{ "ENET_GALR", 0x02188124, 0, 0xffffffff, 'x', "ENET_GALR" },
+//{ "ENET_GAUR", 0x02188120, 0, 0xffffffff, 'x', "ENET_GAUR" },
+//{ "ENET_IALR", 0x0218811C, 0, 0xffffffff, 'x', "ENET_IALR" },
+//{ "ENET_IAUR", 0x02188118, 0, 0xffffffff, 'x', "ENET_IAUR" },
+//{ "ENET_IEEE_R_ALIGN", 0x021882D4, 0, 0xffffffff, 'x', "ENET_IEEE_R_ALIGN" },
+//{ "ENET_IEEE_R_CRC", 0x021882D0, 0, 0xffffffff, 'x', "ENET_IEEE_R_CRC" },
+//{ "ENET_IEEE_R_DROP", 0x021882C8, 0, 0xffffffff, 'x', "ENET_IEEE_R_DROP" },
+//{ "ENET_IEEE_R_FDXFC", 0x021882DC, 0, 0xffffffff, 'x', "ENET_IEEE_R_FDXFC" },
+//{ "ENET_IEEE_R_FRAME_OK", 0x021882CC, 0, 0xffffffff, 'x', "ENET_IEEE_R_FRAME_OK" },
+//{ "ENET_IEEE_R_MACERR", 0x021882D8, 0, 0xffffffff, 'x', "ENET_IEEE_R_MACERR" },
+//{ "ENET_IEEE_R_OCTETS_OK", 0x021882E0, 0, 0xffffffff, 'x', "ENET_IEEE_R_OCTETS_OK" },
+//{ "ENET_IEEE_T_1COL", 0x02188250, 0, 0xffffffff, 'x', "ENET_IEEE_T_1COL" },
+//{ "ENET_IEEE_T_CSERR", 0x02188268, 0, 0xffffffff, 'x', "ENET_IEEE_T_CSERR" },
+//{ "ENET_IEEE_T_DEF", 0x02188258, 0, 0xffffffff, 'x', "ENET_IEEE_T_DEF" },
+//{ "ENET_IEEE_T_DROP", 0x02188248, 0, 0xffffffff, 'x', "ENET_IEEE_T_DROP" },
+//{ "ENET_IEEE_T_EXCOL", 0x02188260, 0, 0xffffffff, 'x', "ENET_IEEE_T_EXCOL" },
+//{ "ENET_IEEE_T_FDXFC", 0x02188270, 0, 0xffffffff, 'x', "ENET_IEEE_T_FDXFC" },
+//{ "ENET_IEEE_T_FRAME_OK", 0x0218824C, 0, 0xffffffff, 'x', "ENET_IEEE_T_FRAME_OK" },
+//{ "ENET_IEEE_T_LCOL", 0x0218825C, 0, 0xffffffff, 'x', "ENET_IEEE_T_LCOL" },
+//{ "ENET_IEEE_T_MACERR", 0x02188264, 0, 0xffffffff, 'x', "ENET_IEEE_T_MACERR" },
+//{ "ENET_IEEE_T_MCOL", 0x02188254, 0, 0xffffffff, 'x', "ENET_IEEE_T_MCOL" },
+//{ "ENET_IEEE_T_OCTETS_OK", 0x02188274, 0, 0xffffffff, 'x', "ENET_IEEE_T_OCTETS_OK" },
+//{ "ENET_IEEE_T_SQE", 0x0218826C, 0, 0xffffffff, 'x', "ENET_IEEE_T_SQE" },
+//{ "ENET_MIBC", 0x02188064, 0, 0xffffffff, 'x', "ENET_MIBC" },
+//{ "ENET_MMFR", 0x02188040, 0, 0xffffffff, 'x', "ENET_MMFR" },
+//{ "ENET_MRBR", 0x02188188, 0, 0xffffffff, 'x', "ENET_MRBR" },
+//{ "ENET_MSCR", 0x02188044, 0, 0xffffffff, 'x', "ENET_MSCR" },
+//{ "ENET_OPD", 0x021880EC, 0, 0xffffffff, 'x', "ENET_OPD" },
+//{ "ENET_PALR", 0x021880E4, 0, 0xffffffff, 'x', "ENET_PALR" },
+//{ "ENET_PAUR", 0x021880E8, 0, 0xffffffff, 'x', "ENET_PAUR" },
+//{ "ENET_RACC", 0x021881C4, 0, 0xffffffff, 'x', "ENET_RACC" },
+//{ "ENET_RAEM", 0x02188198, 0, 0xffffffff, 'x', "ENET_RAEM" },
+//{ "ENET_RAFL", 0x0218819C, 0, 0xffffffff, 'x', "ENET_RAFL" },
+//{ "ENET_RCR", 0x02188084, 0, 0xffffffff, 'x', "ENET_RCR" },
+//{ "ENET_RDAR", 0x02188010, 0, 0xffffffff, 'x', "ENET_RDAR" },
+//{ "ENET_RDSR", 0x02188180, 0, 0xffffffff, 'x', "ENET_RDSR" },
+//{ "ENET_RMON_R_BC_PKT", 0x02188288, 0, 0xffffffff, 'x', "ENET_RMON_R_BC_PKT" },
+//{ "ENET_RMON_R_CRC_ALIGN", 0x02188290, 0, 0xffffffff, 'x', "ENET_RMON_R_CRC_ALIGN" },
+//{ "ENET_RMON_R_FRAG", 0x0218829C, 0, 0xffffffff, 'x', "ENET_RMON_R_FRAG" },
+//{ "ENET_RMON_R_JAB", 0x021882A0, 0, 0xffffffff, 'x', "ENET_RMON_R_JAB" },
+//{ "ENET_RMON_R_MC_PKT", 0x0218828C, 0, 0xffffffff, 'x', "ENET_RMON_R_MC_PKT" },
+//{ "ENET_RMON_R_OCTETS", 0x021882C4, 0, 0xffffffff, 'x', "ENET_RMON_R_OCTETS" },
+//{ "ENET_RMON_R_OVERSIZE", 0x02188298, 0, 0xffffffff, 'x', "ENET_RMON_R_OVERSIZE" },
+//{ "ENET_RMON_R_P1024TO2047", 0x021882BC, 0, 0xffffffff, 'x', "ENET_RMON_R_P1024TO2047" },
+//{ "ENET_RMON_R_P128TO255", 0x021882B0, 0, 0xffffffff, 'x', "ENET_RMON_R_P128TO255" },
+//{ "ENET_RMON_R_P256TO511", 0x021882B4, 0, 0xffffffff, 'x', "ENET_RMON_R_P256TO511" },
+//{ "ENET_RMON_R_P512TO1023", 0x021882B8, 0, 0xffffffff, 'x', "ENET_RMON_R_P512TO1023" },
+//{ "ENET_RMON_R_P64", 0x021882A8, 0, 0xffffffff, 'x', "ENET_RMON_R_P64" },
+//{ "ENET_RMON_R_P65TO127", 0x021882AC, 0, 0xffffffff, 'x', "ENET_RMON_R_P65TO127" },
+//{ "ENET_RMON_R_PACKETS", 0x02188284, 0, 0xffffffff, 'x', "ENET_RMON_R_PACKETS" },
+//{ "ENET_RMON_R_P_GTE2048", 0x021882C0, 0, 0xffffffff, 'x', "ENET_RMON_R_P_GTE2048" },
+//{ "ENET_RMON_R_RESVD_0", 0x021882A4, 0, 0xffffffff, 'x', "ENET_RMON_R_RESVD_0" },
+//{ "ENET_RMON_R_UNDERSIZE", 0x02188294, 0, 0xffffffff, 'x', "ENET_RMON_R_UNDERSIZE" },
+//{ "ENET_RMON_T_BC_PKT", 0x02188208, 0, 0xffffffff, 'x', "ENET_RMON_T_BC_PKT" },
+//{ "ENET_RMON_T_COL", 0x02188224, 0, 0xffffffff, 'x', "ENET_RMON_T_COL" },
+//{ "ENET_RMON_T_CRC_ALIGN", 0x02188210, 0, 0xffffffff, 'x', "ENET_RMON_T_CRC_ALIGN" },
+//{ "ENET_RMON_T_DROP", 0x02188200, 0, 0xffffffff, 'x', "ENET_RMON_T_DROP" },
+//{ "ENET_RMON_T_FRAG", 0x0218821C, 0, 0xffffffff, 'x', "ENET_RMON_T_FRAG" },
+//{ "ENET_RMON_T_JAB", 0x02188220, 0, 0xffffffff, 'x', "ENET_RMON_T_JAB" },
+//{ "ENET_RMON_T_MC_PKT", 0x0218820C, 0, 0xffffffff, 'x', "ENET_RMON_T_MC_PKT" },
+//{ "ENET_RMON_T_OCTETS", 0x02188244, 0, 0xffffffff, 'x', "ENET_RMON_T_OCTETS" },
+//{ "ENET_RMON_T_OVERSIZE", 0x02188218, 0, 0xffffffff, 'x', "ENET_RMON_T_OVERSIZE" },
+//{ "ENET_RMON_T_P1024TO2047", 0x0218823C, 0, 0xffffffff, 'x', "ENET_RMON_T_P1024TO2047" },
+//{ "ENET_RMON_T_P128TO255n", 0x02188230, 0, 0xffffffff, 'x', "ENET_RMON_T_P128TO255n" },
+//{ "ENET_RMON_T_P256TO511", 0x02188234, 0, 0xffffffff, 'x', "ENET_RMON_T_P256TO511" },
+//{ "ENET_RMON_T_P512TO1023", 0x02188238, 0, 0xffffffff, 'x', "ENET_RMON_T_P512TO1023" },
+//{ "ENET_RMON_T_P64", 0x02188228, 0, 0xffffffff, 'x', "ENET_RMON_T_P64" },
+//{ "ENET_RMON_T_P65TO127n", 0x0218822C, 0, 0xffffffff, 'x', "ENET_RMON_T_P65TO127n" },
+//{ "ENET_RMON_T_PACKETS", 0x02188204, 0, 0xffffffff, 'x', "ENET_RMON_T_PACKETS" },
+//{ "ENET_RMON_T_P_GTE2048", 0x02188240, 0, 0xffffffff, 'x', "ENET_RMON_T_P_GTE2048" },
+//{ "ENET_RMON_T_UNDERSIZE", 0x02188214, 0, 0xffffffff, 'x', "ENET_RMON_T_UNDERSIZE" },
+//{ "ENET_RSEM", 0x02188194, 0, 0xffffffff, 'x', "ENET_RSEM" },
+//{ "ENET_RSFL", 0x02188190, 0, 0xffffffff, 'x', "ENET_RSFL" },
+//{ "ENET_TACC", 0x021881C0, 0, 0xffffffff, 'x', "ENET_TACC" },
+//{ "ENET_TAEM", 0x021881A4, 0, 0xffffffff, 'x', "ENET_TAEM" },
+//{ "ENET_TAFL", 0x021881A8, 0, 0xffffffff, 'x', "ENET_TAFL" },
+//{ "ENET_TCCR0", 0x0218860C, 0, 0xffffffff, 'x', "ENET_TCCR0" },
+//{ "ENET_TCCR1", 0x02188614, 0, 0xffffffff, 'x', "ENET_TCCR1" },
+//{ "ENET_TCCR2", 0x0218861C, 0, 0xffffffff, 'x', "ENET_TCCR2" },
+//{ "ENET_TCCR3", 0x02188624, 0, 0xffffffff, 'x', "ENET_TCCR3" },
+//{ "ENET_TCR", 0x021880C4, 0, 0xffffffff, 'x', "ENET_TCR" },
+//{ "ENET_TCSR0", 0x02188608, 0, 0xffffffff, 'x', "ENET_TCSR0" },
+//{ "ENET_TCSR1", 0x02188610, 0, 0xffffffff, 'x', "ENET_TCSR1" },
+//{ "ENET_TCSR2", 0x02188618, 0, 0xffffffff, 'x', "ENET_TCSR2" },
+//{ "ENET_TCSR3", 0x02188620, 0, 0xffffffff, 'x', "ENET_TCSR3" },
+//{ "ENET_TDAR", 0x02188014, 0, 0xffffffff, 'x', "ENET_TDAR" },
+//{ "ENET_TDSR", 0x02188184, 0, 0xffffffff, 'x', "ENET_TDSR" },
+//{ "ENET_TFWR", 0x02188144, 0, 0xffffffff, 'x', "ENET_TFWR" },
+//{ "ENET_TGSR", 0x02188604, 0, 0xffffffff, 'x', "ENET_TGSR" },
+//{ "ENET_TIPG", 0x021881AC, 0, 0xffffffff, 'x', "ENET_TIPG" },
+//{ "ENET_TSEM", 0x021881A0, 0, 0xffffffff, 'x', "ENET_TSEM" },
+//{ "ESAI_ECR", 0x02024008, 0, 0xffffffff, 'x', "ESAI_ECR" },
+//{ "ESAI_ECR", 0x02024010, 0, 0xffffffff, 'x', "ESAI_ECR" },
+//{ "ESAI_ERDR", 0x02024004, 0, 0xffffffff, 'x', "ESAI_ERDR" },
+//{ "ESAI_ESR", 0x0202400C, 0, 0xffffffff, 'x', "ESAI_ESR" },
+//{ "ESAI_ETDR", 0x02024000, 0, 0xffffffff, 'x', "ESAI_ETDR" },
+//{ "ESAI_PCRC", 0x020240FC, 0, 0xffffffff, 'x', "ESAI_PCRC" },
+//{ "ESAI_PCRC", 0x020240f8, 0, 0xffffffff, 'x', "ESAI_PCRC" },
+//{ "ESAI_PRRC", 0x020240F8, 0, 0xffffffff, 'x', "ESAI_PRRC" },
+//{ "ESAI_PRRC", 0x020240f8, 0, 0xffffffff, 'x', "ESAI_PRRC" },
+//{ "ESAI_RCCR", 0x020240E0, 0, 0xffffffff, 'x', "ESAI_RCCR" },
+//{ "ESAI_RCCR", 0x020240e0, 0, 0xffffffff, 'x', "ESAI_RCCR" },
+//{ "ESAI_RCR", 0x020240DC, 0, 0xffffffff, 'x', "ESAI_RCR" },
+//{ "ESAI_RCR", 0x020240dc, 0, 0xffffffff, 'x', "ESAI_RCR" },
+//{ "ESAI_RFCR", 0x02024018, 0, 0xffffffff, 'x', "ESAI_RFCR" },
+//{ "ESAI_RFCR", 0x02024018, 0, 0xffffffff, 'x', "ESAI_RFCR" },
+//{ "ESAI_RFSR", 0x0202401C, 0, 0xffffffff, 'x', "ESAI_RFSR" },
+//{ "ESAI_RSMA", 0x020240EC, 0, 0xffffffff, 'x', "ESAI_RSMA" },
+//{ "ESAI_RSMB", 0x020240F0, 0, 0xffffffff, 'x', "ESAI_RSMB" },
+//{ "ESAI_SAICR", 0x020240D0, 0, 0xffffffff, 'x', "ESAI_SAICR" },
+//{ "ESAI_SAICR", 0x020240d0, 0, 0xffffffff, 'x', "ESAI_SAICR" },
+//{ "ESAI_SAISR", 0x020240CC, 0, 0xffffffff, 'x', "ESAI_SAISR" },
+//{ "ESAI_TCCR", 0x020240D8, 0, 0xffffffff, 'x', "ESAI_TCCR" },
+//{ "ESAI_TCCR", 0x020240d8, 0, 0xffffffff, 'x', "ESAI_TCCR" },
+//{ "ESAI_TCR", 0x020240D4, 0, 0xffffffff, 'x', "ESAI_TCR" },
+//{ "ESAI_TCR", 0x020240d4, 0, 0xffffffff, 'x', "ESAI_TCR" },
+//{ "ESAI_TFCR", 0x02024010, 0, 0xffffffff, 'x', "ESAI_TFCR" },
+//{ "ESAI_TFCR", 0x02024010, 0, 0xffffffff, 'x', "ESAI_TFCR" },
+//{ "ESAI_TFSR", 0x02024014, 0, 0xffffffff, 'x', "ESAI_TFSR" },
+//{ "ESAI_TSMA", 0x020240E4, 0, 0xffffffff, 'x', "ESAI_TSMA" },
+//{ "ESAI_TSMB", 0x020240E8, 0, 0xffffffff, 'x', "ESAI_TSMB" },
+//{ "ESAI_TSR", 0x02024098, 0, 0xffffffff, 'x', "ESAI_TSR" },
+//{ "GPC_CNTR", 0x020DC000, 0, 0xffffffff, 'x', "GPC_CNTR" },
+//{ "GPC_IMR1", 0x020DC008, 0, 0xffffffff, 'x', "GPC_IMR1" },
+//{ "GPC_IMR2", 0x020DC00C, 0, 0xffffffff, 'x', "GPC_IMR2" },
+//{ "GPC_IMR3", 0x020DC010, 0, 0xffffffff, 'x', "GPC_IMR3" },
+//{ "GPC_IMR4", 0x020DC014, 0, 0xffffffff, 'x', "GPC_IMR4" },
+//{ "GPC_ISR1", 0x020DC018, 0, 0xffffffff, 'x', "GPC_ISR1" },
+//{ "GPC_ISR2", 0x020DC01C, 0, 0xffffffff, 'x', "GPC_ISR2" },
+//{ "GPC_ISR3", 0x020DC020, 0, 0xffffffff, 'x', "GPC_ISR3" },
+//{ "GPC_ISR4", 0x020DC024, 0, 0xffffffff, 'x', "GPC_ISR4" },
+//{ "GPC_PGR", 0x020DC004, 0, 0xffffffff, 'x', "GPC_PGR" },
+//{ "GPIO1_DR", 0x0209C000, 0, 0xffffffff, 'x', "GPIO1_DR" },
+//{ "GPIO1_EDGE_SEL", 0x0209C01C, 0, 0xffffffff, 'x', "GPIO1_EDGE_SEL" },
+//{ "GPIO1_GDIR", 0x0209C004, 0, 0xffffffff, 'x', "GPIO1_GDIR" },
+//{ "GPIO1_ICR1", 0x0209C00C, 0, 0xffffffff, 'x', "GPIO1_ICR1" },
+//{ "GPIO1_ICR2", 0x0209C010, 0, 0xffffffff, 'x', "GPIO1_ICR2" },
+//{ "GPIO1_IMR", 0x0209C014, 0, 0xffffffff, 'x', "GPIO1_IMR" },
+//{ "GPIO1_ISR", 0x0209C018, 0, 0xffffffff, 'x', "GPIO1_ISR" },
+//{ "GPIO1_PSR", 0x0209C008, 0, 0xffffffff, 'x', "GPIO1_PSR" },
+//{ "GPIO2_DR", 0x020A0000, 0, 0xffffffff, 'x', "GPIO2_DR" },
+//{ "GPIO2_EDGE_SEL", 0x020A001C, 0, 0xffffffff, 'x', "GPIO2_EDGE_SEL" },
+//{ "GPIO2_GDIR", 0x020A0004, 0, 0xffffffff, 'x', "GPIO2_GDIR" },
+//{ "GPIO2_ICR1", 0x020A000C, 0, 0xffffffff, 'x', "GPIO2_ICR1" },
+//{ "GPIO2_ICR2", 0x020A0010, 0, 0xffffffff, 'x', "GPIO2_ICR2" },
+//{ "GPIO2_IMR", 0x020A0014, 0, 0xffffffff, 'x', "GPIO2_IMR" },
+//{ "GPIO2_ISR", 0x020A0018, 0, 0xffffffff, 'x', "GPIO2_ISR" },
+//{ "GPIO2_PSR", 0x020A0008, 0, 0xffffffff, 'x', "GPIO2_PSR" },
+//{ "GPIO3_DR", 0x020A4000, 0, 0xffffffff, 'x', "GPIO3_DR" },
+//{ "GPIO3_EDGE_SEL", 0x020A401C, 0, 0xffffffff, 'x', "GPIO3_EDGE_SEL" },
+//{ "GPIO3_GDIR", 0x020A4004, 0, 0xffffffff, 'x', "GPIO3_GDIR" },
+//{ "GPIO3_ICR1", 0x020A400C, 0, 0xffffffff, 'x', "GPIO3_ICR1" },
+//{ "GPIO3_ICR2", 0x020A4010, 0, 0xffffffff, 'x', "GPIO3_ICR2" },
+//{ "GPIO3_IMR", 0x020A4014, 0, 0xffffffff, 'x', "GPIO3_IMR" },
+//{ "GPIO3_ISR", 0x020A4018, 0, 0xffffffff, 'x', "GPIO3_ISR" },
+//{ "GPIO3_PSR", 0x020A4008, 0, 0xffffffff, 'x', "GPIO3_PSR" },
+//{ "GPIO4_DR", 0x020A8000, 0, 0xffffffff, 'x', "GPIO4_DR" },
+//{ "GPIO4_EDGE_SEL", 0x020A801C, 0, 0xffffffff, 'x', "GPIO4_EDGE_SEL" },
+//{ "GPIO4_GDIR", 0x020A8004, 0, 0xffffffff, 'x', "GPIO4_GDIR" },
+//{ "GPIO4_ICR1", 0x020A800C, 0, 0xffffffff, 'x', "GPIO4_ICR1" },
+//{ "GPIO4_ICR2", 0x020A8010, 0, 0xffffffff, 'x', "GPIO4_ICR2" },
+//{ "GPIO4_IMR", 0x020A8014, 0, 0xffffffff, 'x', "GPIO4_IMR" },
+//{ "GPIO4_ISR", 0x020A8018, 0, 0xffffffff, 'x', "GPIO4_ISR" },
+//{ "GPIO4_PSR", 0x020A8008, 0, 0xffffffff, 'x', "GPIO4_PSR" },
+//{ "GPIO5_DR", 0x020AC000, 0, 0xffffffff, 'x', "GPIO5_DR" },
+//{ "GPIO5_EDGE_SEL", 0x020AC01C, 0, 0xffffffff, 'x', "GPIO5_EDGE_SEL" },
+//{ "GPIO5_GDIR", 0x020AC004, 0, 0xffffffff, 'x', "GPIO5_GDIR" },
+//{ "GPIO5_ICR1", 0x020AC00C, 0, 0xffffffff, 'x', "GPIO5_ICR1" },
+//{ "GPIO5_ICR2", 0x020AC010, 0, 0xffffffff, 'x', "GPIO5_ICR2" },
+//{ "GPIO5_IMR", 0x020AC014, 0, 0xffffffff, 'x', "GPIO5_IMR" },
+//{ "GPIO5_ISR", 0x020AC018, 0, 0xffffffff, 'x', "GPIO5_ISR" },
+//{ "GPIO5_PSR", 0x020AC008, 0, 0xffffffff, 'x', "GPIO5_PSR" },
+//{ "GPIO6_DR", 0x020B0000, 0, 0xffffffff, 'x', "GPIO6_DR" },
+//{ "GPIO6_EDGE_SEL", 0x020B001C, 0, 0xffffffff, 'x', "GPIO6_EDGE_SEL" },
+//{ "GPIO6_GDIR", 0x020B0004, 0, 0xffffffff, 'x', "GPIO6_GDIR" },
+//{ "GPIO6_ICR1", 0x020B000C, 0, 0xffffffff, 'x', "GPIO6_ICR1" },
+//{ "GPIO6_ICR2", 0x020B0010, 0, 0xffffffff, 'x', "GPIO6_ICR2" },
+//{ "GPIO6_IMR", 0x020B0014, 0, 0xffffffff, 'x', "GPIO6_IMR" },
+//{ "GPIO6_ISR", 0x020B0018, 0, 0xffffffff, 'x', "GPIO6_ISR" },
+//{ "GPIO6_PSR", 0x020B0008, 0, 0xffffffff, 'x', "GPIO6_PSR" },
+//{ "GPIO7_DR", 0x020B4000, 0, 0xffffffff, 'x', "GPIO7_DR" },
+//{ "GPIO7_EDGE_SEL", 0x020B401C, 0, 0xffffffff, 'x', "GPIO7_EDGE_SEL" },
+//{ "GPIO7_GDIR", 0x020B4004, 0, 0xffffffff, 'x', "GPIO7_GDIR" },
+//{ "GPIO7_ICR1", 0x020B400C, 0, 0xffffffff, 'x', "GPIO7_ICR1" },
+//{ "GPIO7_ICR2", 0x020B4010, 0, 0xffffffff, 'x', "GPIO7_ICR2" },
+//{ "GPIO7_IMR", 0x020B4014, 0, 0xffffffff, 'x', "GPIO7_IMR" },
+//{ "GPIO7_ISR", 0x020B4018, 0, 0xffffffff, 'x', "GPIO7_ISR" },
+//{ "GPIO7_PSR", 0x020B4008, 0, 0xffffffff, 'x', "GPIO7_PSR" },
+//{ "GPMI_HW_GPMI_AUXILIARY", 0x00112050, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_AUXILIARY" },
+//{ "GPMI_HW_GPMI_COMPARE", 0x00112010, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_COMPARE" },
+//{ "GPMI_HW_GPMI_DATA", 0x001120A0, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_DATA" },
+//{ "GPMI_HW_GPMI_DEBUG", 0x001120C0, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_DEBUG" },
+//{ "GPMI_HW_GPMI_DEBUG2", 0x001120E0, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_DEBUG2" },
+//{ "GPMI_HW_GPMI_DEBUG3", 0x001120F0, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_DEBUG3" },
+//{ "GPMI_HW_GPMI_ECCCOUNT", 0x00112030, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_ECCCOUNT" },
+//{ "GPMI_HW_GPMI_PAYLOAD", 0x00112040, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_PAYLOAD" },
+//{ "GPMI_HW_GPMI_READ_DDR_DLL_CTRL", 0x00112100, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_READ_DDR_DLL_CTRL" },
+//{ "GPMI_HW_GPMI_READ_DDR_DLL_STS", 0x00112120, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_READ_DDR_DLL_STS" },
+//{ "GPMI_HW_GPMI_STAT", 0x001120B0, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_STAT" },
+//{ "GPMI_HW_GPMI_TIMING0", 0x00112070, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_TIMING0" },
+//{ "GPMI_HW_GPMI_TIMING1", 0x00112080, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_TIMING1" },
+//{ "GPMI_HW_GPMI_TIMING2", 0x00112090, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_TIMING2" },
+//{ "GPMI_HW_GPMI_VERSION", 0x001120D0, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_VERSION" },
+//{ "GPMI_HW_GPMI_WRITE_DDR_DLL_CTRL", 0x00112110, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_WRITE_DDR_DLL_CTRL" },
+//{ "GPMI_HW_GPMI_WRITE_DDR_DLL_STS", 0x00112130, 0, 0xffffffff, 'x', "GPMI_HW_GPMI_WRITE_DDR_DLL_STS" },
+//{ "GPT_CNT", 0x02098024, 0, 0xffffffff, 'x', "GPT_CNT" },
+//{ "GPT_CR", 0x02098000, 0, 0xffffffff, 'x', "GPT_CR" },
+//{ "GPT_ICR1", 0x0209801C, 0, 0xffffffff, 'x', "GPT_ICR1" },
+//{ "GPT_ICR2", 0x02098020, 0, 0xffffffff, 'x', "GPT_ICR2" },
+//{ "GPT_IR", 0x0209800C, 0, 0xffffffff, 'x', "GPT_IR" },
+//{ "GPT_OCR1", 0x02098010, 0, 0xffffffff, 'x', "GPT_OCR1" },
+//{ "GPT_OCR2", 0x02098014, 0, 0xffffffff, 'x', "GPT_OCR2" },
+//{ "GPT_OCR3", 0x02098018, 0, 0xffffffff, 'x', "GPT_OCR3" },
+//{ "GPT_PR", 0x02098004, 0, 0xffffffff, 'x', "GPT_PR" },
+//{ "GPT_SR", 0x02098008, 0, 0xffffffff, 'x', "GPT_SR" },
+//{ "HW_BCH_BLOCKNAME", 0x00114150, 0, 0xffffffff, 'x', "HW_BCH_BLOCKNAME" },
+//{ "HW_BCH_CTRL", 0x00114000, 0, 0xffffffff, 'x', "HW_BCH_CTRL" },
+//{ "HW_BCH_DATAPTR", 0x00114040, 0, 0xffffffff, 'x', "HW_BCH_DATAPTR" },
+//{ "HW_BCH_DBGAHBMREAD", 0x00114140, 0, 0xffffffff, 'x', "HW_BCH_DBGAHBMREAD" },
+//{ "HW_BCH_DBGCSFEREAD", 0x00114120, 0, 0xffffffff, 'x', "HW_BCH_DBGCSFEREAD" },
+//{ "HW_BCH_DBGKESREAD", 0x00114110, 0, 0xffffffff, 'x', "HW_BCH_DBGKESREAD" },
+//{ "HW_BCH_DBGSYNDGENREAD", 0x00114130, 0, 0xffffffff, 'x', "HW_BCH_DBGSYNDGENREAD" },
+//{ "HW_BCH_DEBUG0", 0x00114100, 0, 0xffffffff, 'x', "HW_BCH_DEBUG0" },
+//{ "HW_BCH_ENCODEPTR", 0x00114030, 0, 0xffffffff, 'x', "HW_BCH_ENCODEPTR" },
+//{ "HW_BCH_FLASH0LAYOUT0", 0x00114080, 0, 0xffffffff, 'x', "HW_BCH_FLASH0LAYOUT0" },
+//{ "HW_BCH_FLASH0LAYOUT1", 0x00114090, 0, 0xffffffff, 'x', "HW_BCH_FLASH0LAYOUT1" },
+//{ "HW_BCH_FLASH1LAYOUT0", 0x001140A0, 0, 0xffffffff, 'x', "HW_BCH_FLASH1LAYOUT0" },
+//{ "HW_BCH_FLASH1LAYOUT1", 0x001140B0, 0, 0xffffffff, 'x', "HW_BCH_FLASH1LAYOUT1" },
+//{ "HW_BCH_FLASH2LAYOUT0", 0x001140C0, 0, 0xffffffff, 'x', "HW_BCH_FLASH2LAYOUT0" },
+//{ "HW_BCH_FLASH2LAYOUT1", 0x001140D0, 0, 0xffffffff, 'x', "HW_BCH_FLASH2LAYOUT1" },
+//{ "HW_BCH_FLASH3LAYOUT0", 0x001140E0, 0, 0xffffffff, 'x', "HW_BCH_FLASH3LAYOUT0" },
+//{ "HW_BCH_FLASH3LAYOUT1", 0x001140F0, 0, 0xffffffff, 'x', "HW_BCH_FLASH3LAYOUT1" },
+//{ "HW_BCH_LAYOUTSELECT", 0x00114070, 0, 0xffffffff, 'x', "HW_BCH_LAYOUTSELECT" },
+//{ "HW_BCH_METAPTR", 0x00114050, 0, 0xffffffff, 'x', "HW_BCH_METAPTR" },
+//{ "HW_BCH_MODE", 0x00114020, 0, 0xffffffff, 'x', "HW_BCH_MODE" },
+//{ "HW_BCH_STATUS0", 0x00114010, 0, 0xffffffff, 'x', "HW_BCH_STATUS0" },
+//{ "HW_BCH_VERSION", 0x00114160, 0, 0xffffffff, 'x', "HW_BCH_VERSION" },
+//{ "IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT", 0x020E07B0, 0, 0xffffffff, 'x', "IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT" },
+//{ "IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT", 0x020E07B4, 0, 0xffffffff, 'x', "IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT" },
+//{ "IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT", 0x020E07B8, 0, 0xffffffff, 'x', "IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT" },
+//{ "IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT", 0x020E07BC, 0, 0xffffffff, 'x', "IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT" },
+//{ "IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT", 0x020E07C0, 0, 0xffffffff, 'x', "IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT" },
+//{ "IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT", 0x020E07C4, 0, 0xffffffff, 'x', "IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT" },
+//{ "IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT", 0x020E07C8, 0, 0xffffffff, 'x', "IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT" },
+//{ "IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT", 0x020E07CC, 0, 0xffffffff, 'x', "IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT" },
+//{ "IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT", 0x020E07D0, 0, 0xffffffff, 'x', "IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT" },
+//{ "IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT", 0x020E07D4, 0, 0xffffffff, 'x', "IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT" },
+//{ "IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT", 0x020E07D8, 0, 0xffffffff, 'x', "IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT" },
+//{ "IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT", 0x020E07DC, 0, 0xffffffff, 'x', "IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT" },
+//{ "IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT", 0x020E07E0, 0, 0xffffffff, 'x', "IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT" },
+//{ "IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT", 0x020E07E4, 0, 0xffffffff, 'x', "IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT" },
+//{ "IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT", 0x020E07E8, 0, 0xffffffff, 'x', "IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT" },
+//{ "IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT", 0x020E07EC, 0, 0xffffffff, 'x', "IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT" },
+//{ "IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT", 0x020E07F0, 0, 0xffffffff, 'x', "IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT", 0x020E07F4, 0, 0xffffffff, 'x', "IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT", 0x020E07F8, 0, 0xffffffff, 'x', "IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT", 0x020E07FC, 0, 0xffffffff, 'x', "IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT", 0x020E0800, 0, 0xffffffff, 'x', "IOMUXC_ECSPI1_IPP_IND_SS_B_0_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT", 0x020E0804, 0, 0xffffffff, 'x', "IOMUXC_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT", 0x020E0808, 0, 0xffffffff, 'x', "IOMUXC_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT", 0x020E080C, 0, 0xffffffff, 'x', "IOMUXC_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT", 0x020E0810, 0, 0xffffffff, 'x', "IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT", 0x020E0814, 0, 0xffffffff, 'x', "IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT", 0x020E0818, 0, 0xffffffff, 'x', "IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT", 0x020E081C, 0, 0xffffffff, 'x', "IOMUXC_ECSPI2_IPP_IND_SS_B_0_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT", 0x020E0820, 0, 0xffffffff, 'x', "IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI4_IPP_IND_SS_B_0_SELECT_INPUT", 0x020E0824, 0, 0xffffffff, 'x', "IOMUXC_ECSPI4_IPP_IND_SS_B_0_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT", 0x020E0828, 0, 0xffffffff, 'x', "IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT", 0x020E082C, 0, 0xffffffff, 'x', "IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT", 0x020E0830, 0, 0xffffffff, 'x', "IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI5_IPP_IND_SS_B_0_SELECT_INPUT", 0x020E0834, 0, 0xffffffff, 'x', "IOMUXC_ECSPI5_IPP_IND_SS_B_0_SELECT_INPUT" },
+//{ "IOMUXC_ECSPI5_IPP_IND_SS_B_1_SELECT_INPUT", 0x020E0838, 0, 0xffffffff, 'x', "IOMUXC_ECSPI5_IPP_IND_SS_B_1_SELECT_INPUT" },
+//{ "IOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT", 0x020E083C, 0, 0xffffffff, 'x', "IOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT" },
+//{ "IOMUXC_ENET_IPP_IND_MAC0_MDIO_SELECT_INPUT", 0x020E0840, 0, 0xffffffff, 'x', "IOMUXC_ENET_IPP_IND_MAC0_MDIO_SELECT_INPUT" },
+//{ "IOMUXC_ENET_IPP_IND_MAC0_RXCLK_SELECT_INPUT", 0x020E0844, 0, 0xffffffff, 'x', "IOMUXC_ENET_IPP_IND_MAC0_RXCLK_SELECT_INPUT" },
+//{ "IOMUXC_ENET_IPP_IND_MAC0_RXDATA_0_SELECT_INPUT", 0x020E0848, 0, 0xffffffff, 'x', "IOMUXC_ENET_IPP_IND_MAC0_RXDATA_0_SELECT_INPUT" },
+//{ "IOMUXC_ENET_IPP_IND_MAC0_RXDATA_1_SELECT_INPUT", 0x020E084C, 0, 0xffffffff, 'x', "IOMUXC_ENET_IPP_IND_MAC0_RXDATA_1_SELECT_INPUT" },
+//{ "IOMUXC_ENET_IPP_IND_MAC0_RXDATA_2_SELECT_INPUT", 0x020E0850, 0, 0xffffffff, 'x', "IOMUXC_ENET_IPP_IND_MAC0_RXDATA_2_SELECT_INPUT" },
+//{ "IOMUXC_ENET_IPP_IND_MAC0_RXDATA_3_SELECT_INPUT", 0x020E0854, 0, 0xffffffff, 'x', "IOMUXC_ENET_IPP_IND_MAC0_RXDATA_3_SELECT_INPUT" },
+//{ "IOMUXC_ENET_IPP_IND_MAC0_RXEN_SELECT_INPUT", 0x020E0858, 0, 0xffffffff, 'x', "IOMUXC_ENET_IPP_IND_MAC0_RXEN_SELECT_INPUT" },
+//{ "IOMUXC_ESAI1_IPP_IND_FSR_SELECT_INPUT", 0x020E085C, 0, 0xffffffff, 'x', "IOMUXC_ESAI1_IPP_IND_FSR_SELECT_INPUT" },
+//{ "IOMUXC_ESAI1_IPP_IND_FST_SELECT_INPUT", 0x020E0860, 0, 0xffffffff, 'x', "IOMUXC_ESAI1_IPP_IND_FST_SELECT_INPUT" },
+//{ "IOMUXC_ESAI1_IPP_IND_HCKR_SELECT_INPUT", 0x020E0864, 0, 0xffffffff, 'x', "IOMUXC_ESAI1_IPP_IND_HCKR_SELECT_INPUT" },
+//{ "IOMUXC_ESAI1_IPP_IND_HCKT_SELECT_INPUT", 0x020E0868, 0, 0xffffffff, 'x', "IOMUXC_ESAI1_IPP_IND_HCKT_SELECT_INPUT" },
+//{ "IOMUXC_ESAI1_IPP_IND_SCKR_SELECT_INPUT", 0x020E086C, 0, 0xffffffff, 'x', "IOMUXC_ESAI1_IPP_IND_SCKR_SELECT_INPUT" },
+//{ "IOMUXC_ESAI1_IPP_IND_SCKT_SELECT_INPUT", 0x020E0870, 0, 0xffffffff, 'x', "IOMUXC_ESAI1_IPP_IND_SCKT_SELECT_INPUT" },
+//{ "IOMUXC_ESAI1_IPP_IND_SDO0_SELECT_INPUT", 0x020E0874, 0, 0xffffffff, 'x', "IOMUXC_ESAI1_IPP_IND_SDO0_SELECT_INPUT" },
+//{ "IOMUXC_ESAI1_IPP_IND_SDO1_SELECT_INPUT", 0x020E0878, 0, 0xffffffff, 'x', "IOMUXC_ESAI1_IPP_IND_SDO1_SELECT_INPUT" },
+//{ "IOMUXC_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT", 0x020E087C, 0, 0xffffffff, 'x', "IOMUXC_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT" },
+//{ "IOMUXC_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT", 0x020E0880, 0, 0xffffffff, 'x', "IOMUXC_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT" },
+//{ "IOMUXC_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT", 0x020E0884, 0, 0xffffffff, 'x', "IOMUXC_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT" },
+//{ "IOMUXC_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT", 0x020E0888, 0, 0xffffffff, 'x', "IOMUXC_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT" },
+//{ "IOMUXC_GPR0", 0x020E0000, 0, 0xffffffff, 'x', "IOMUXC_GPR0" },
+//{ "IOMUXC_GPR1", 0x020E0004, 0, 0xffffffff, 'x', "IOMUXC_GPR1" },
+//{ "IOMUXC_GPR10", 0x020E0028, 0, 0xffffffff, 'x', "IOMUXC_GPR10" },
+//{ "IOMUXC_GPR11", 0x020E002C, 0, 0xffffffff, 'x', "IOMUXC_GPR11" },
+//{ "IOMUXC_GPR12", 0x020E0030, 0, 0xffffffff, 'x', "IOMUXC_GPR12" },
+//{ "IOMUXC_GPR13", 0x020E0034, 0, 0xffffffff, 'x', "IOMUXC_GPR13" },
+//{ "IOMUXC_GPR2", 0x020E0008, 0, 0xffffffff, 'x', "IOMUXC_GPR2" },
+//{ "IOMUXC_GPR3", 0x020E000C, 0, 0xffffffff, 'x', "IOMUXC_GPR3" },
+//{ "IOMUXC_GPR4", 0x020E0010, 0, 0xffffffff, 'x', "IOMUXC_GPR4" },
+//{ "IOMUXC_GPR5", 0x020E0014, 0, 0xffffffff, 'x', "IOMUXC_GPR5" },
+//{ "IOMUXC_GPR6", 0x020E0018, 0, 0xffffffff, 'x', "IOMUXC_GPR6" },
+//{ "IOMUXC_GPR7", 0x020E001C, 0, 0xffffffff, 'x', "IOMUXC_GPR7" },
+//{ "IOMUXC_GPR8", 0x020E0020, 0, 0xffffffff, 'x', "IOMUXC_GPR8" },
+//{ "IOMUXC_GPR9", 0x020E0024, 0, 0xffffffff, 'x', "IOMUXC_GPR9" },
+//{ "IOMUXC_HDMI_TX_ICECIN_SELECT_INPUT", 0x020E088C, 0, 0xffffffff, 'x', "IOMUXC_HDMI_TX_ICECIN_SELECT_INPUT" },
+//{ "IOMUXC_HDMI_TX_II2C_MSTH13TDDC_SCLIN_SELECT_INPUT", 0x020E0890, 0, 0xffffffff, 'x', "IOMUXC_HDMI_TX_II2C_MSTH13TDDC_SCLIN_SELECT_INPUT" },
+//{ "IOMUXC_HDMI_TX_II2C_MSTH13TDDC_SDAIN_SELECT_INPUT", 0x020E0894, 0, 0xffffffff, 'x', "IOMUXC_HDMI_TX_II2C_MSTH13TDDC_SDAIN_SELECT_INPUT" },
+//{ "IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT", 0x020E0898, 0, 0xffffffff, 'x', "IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT" },
+//{ "IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT", 0x020E089C, 0, 0xffffffff, 'x', "IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT" },
+//{ "IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT", 0x020E08A0, 0, 0xffffffff, 'x', "IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT" },
+//{ "IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT", 0x020E08A4, 0, 0xffffffff, 'x', "IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT" },
+//{ "IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT", 0x020E08A8, 0, 0xffffffff, 'x', "IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT" },
+//{ "IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT", 0x020E08AC, 0, 0xffffffff, 'x', "IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT" },
+//{ "IOMUXC_IPU2_IPP_IND_SENS1_DATA_10_SELECT_INPUT", 0x020E08B0, 0, 0xffffffff, 'x', "IOMUXC_IPU2_IPP_IND_SENS1_DATA_10_SELECT_INPUT" },
+//{ "IOMUXC_IPU2_IPP_IND_SENS1_DATA_11_SELECT_INPUT", 0x020E08B4, 0, 0xffffffff, 'x', "IOMUXC_IPU2_IPP_IND_SENS1_DATA_11_SELECT_INPUT" },
+//{ "IOMUXC_IPU2_IPP_IND_SENS1_DATA_12_SELECT_INPUT", 0x020E08B8, 0, 0xffffffff, 'x', "IOMUXC_IPU2_IPP_IND_SENS1_DATA_12_SELECT_INPUT" },
+//{ "IOMUXC_IPU2_IPP_IND_SENS1_DATA_13_SELECT_INPUT", 0x020E08BC, 0, 0xffffffff, 'x', "IOMUXC_IPU2_IPP_IND_SENS1_DATA_13_SELECT_INPUT" },
+//{ "IOMUXC_IPU2_IPP_IND_SENS1_DATA_14_SELECT_INPUT", 0x020E08C0, 0, 0xffffffff, 'x', "IOMUXC_IPU2_IPP_IND_SENS1_DATA_14_SELECT_INPUT" },
+//{ "IOMUXC_IPU2_IPP_IND_SENS1_DATA_15_SELECT_INPUT", 0x020E08C4, 0, 0xffffffff, 'x', "IOMUXC_IPU2_IPP_IND_SENS1_DATA_15_SELECT_INPUT" },
+//{ "IOMUXC_IPU2_IPP_IND_SENS1_DATA_16_SELECT_INPUT", 0x020E08C8, 0, 0xffffffff, 'x', "IOMUXC_IPU2_IPP_IND_SENS1_DATA_16_SELECT_INPUT" },
+//{ "IOMUXC_IPU2_IPP_IND_SENS1_DATA_17_SELECT_INPUT", 0x020E08CC, 0, 0xffffffff, 'x', "IOMUXC_IPU2_IPP_IND_SENS1_DATA_17_SELECT_INPUT" },
+//{ "IOMUXC_IPU2_IPP_IND_SENS1_DATA_18_SELECT_INPUT", 0x020E08D0, 0, 0xffffffff, 'x', "IOMUXC_IPU2_IPP_IND_SENS1_DATA_18_SELECT_INPUT" },
+//{ "IOMUXC_IPU2_IPP_IND_SENS1_DATA_19_SELECT_INPUT", 0x020E08D4, 0, 0xffffffff, 'x', "IOMUXC_IPU2_IPP_IND_SENS1_DATA_19_SELECT_INPUT" },
+//{ "IOMUXC_IPU2_IPP_IND_SENS1_DATA_EN_SELECT_INPUT", 0x020E08D8, 0, 0xffffffff, 'x', "IOMUXC_IPU2_IPP_IND_SENS1_DATA_EN_SELECT_INPUT" },
+//{ "IOMUXC_IPU2_IPP_IND_SENS1_HSYNC_SELECT_INPUT", 0x020E08DC, 0, 0xffffffff, 'x', "IOMUXC_IPU2_IPP_IND_SENS1_HSYNC_SELECT_INPUT" },
+//{ "IOMUXC_IPU2_IPP_IND_SENS1_PIX_CLK_SELECT_INPUT", 0x020E08E0, 0, 0xffffffff, 'x', "IOMUXC_IPU2_IPP_IND_SENS1_PIX_CLK_SELECT_INPUT" },
+//{ "IOMUXC_IPU2_IPP_IND_SENS1_VSYNC_SELECT_INPUT", 0x020E08E4, 0, 0xffffffff, 'x', "IOMUXC_IPU2_IPP_IND_SENS1_VSYNC_SELECT_INPUT" },
+//{ "IOMUXC_KPP_IPP_IND_COL_5_SELECT_INPUT", 0x020E08E8, 0, 0xffffffff, 'x', "IOMUXC_KPP_IPP_IND_COL_5_SELECT_INPUT" },
+//{ "IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT", 0x020E08EC, 0, 0xffffffff, 'x', "IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT" },
+//{ "IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT", 0x020E08F0, 0, 0xffffffff, 'x', "IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT" },
+//{ "IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT", 0x020E08F4, 0, 0xffffffff, 'x', "IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT" },
+//{ "IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT", 0x020E08F8, 0, 0xffffffff, 'x', "IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT" },
+//{ "IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT", 0x020E08FC, 0, 0xffffffff, 'x', "IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT" },
+//{ "IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT", 0x020E0900, 0, 0xffffffff, 'x', "IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT" },
+//{ "IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT", 0x020E0904, 0, 0xffffffff, 'x', "IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT" },
+//{ "IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT", 0x020E0908, 0, 0xffffffff, 'x', "IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT" },
+//{ "IOMUXC_OBSERVE_MUX_0", 0x020E0038, 0, 0xffffffff, 'x', "IOMUXC_OBSERVE_MUX_0" },
+//{ "IOMUXC_OBSERVE_MUX_1", 0x020E003C, 0, 0xffffffff, 'x', "IOMUXC_OBSERVE_MUX_1" },
+//{ "IOMUXC_OBSERVE_MUX_2", 0x020E0040, 0, 0xffffffff, 'x', "IOMUXC_OBSERVE_MUX_2" },
+//{ "IOMUXC_OBSERVE_MUX_3", 0x020E0044, 0, 0xffffffff, 'x', "IOMUXC_OBSERVE_MUX_3" },
+//{ "IOMUXC_OBSERVE_MUX_4", 0x020E0048, 0, 0xffffffff, 'x', "IOMUXC_OBSERVE_MUX_4" },
+//{ "IOMUXC_SDMA_EVENTS_14_SELECT_INPUT", 0x020E090C, 0, 0xffffffff, 'x', "IOMUXC_SDMA_EVENTS_14_SELECT_INPUT" },
+//{ "IOMUXC_SDMA_EVENTS_15_SELECT_INPUT", 0x020E0910, 0, 0xffffffff, 'x', "IOMUXC_SDMA_EVENTS_15_SELECT_INPUT" },
+//{ "IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT", 0x020E0914, 0, 0xffffffff, 'x', "IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT" },
+//{ "IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT", 0x020E0918, 0, 0xffffffff, 'x', "IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT10", 0x020E0280, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT10" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT11", 0x020E0284, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT11" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT12", 0x020E0288, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT12" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT13", 0x020E028C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT13" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT14", 0x020E0290, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT14" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT15", 0x020E0294, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT15" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT16", 0x020E0298, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT16" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT17", 0x020E029C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT17" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT18", 0x020E02A0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT18" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT19", 0x020E02A4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT19" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT4", 0x020E0268, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT4" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT5", 0x020E026C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT5" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT6", 0x020E0270, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT6" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT7", 0x020E0274, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT7" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT8", 0x020E0278, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT8" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT9", 0x020E027C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DAT9" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN", 0x020E0260, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_MCLK", 0x020E025C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_MCLK" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK", 0x020E0258, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC", 0x020E0264, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK", 0x020E015C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15", 0x020E0160, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DI0_PIN2", 0x020E0164, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DI0_PIN2" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DI0_PIN3", 0x020E0168, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DI0_PIN3" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DI0_PIN4", 0x020E016C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DI0_PIN4" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT0", 0x020E0170, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT1", 0x020E0174, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT10", 0x020E0198, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT10" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT11", 0x020E019C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT11" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT12", 0x020E01A0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT12" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT13", 0x020E01A4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT13" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT14", 0x020E01A8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT14" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT15", 0x020E01AC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT15" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT16", 0x020E01B0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT16" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT17", 0x020E01B4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT17" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT18", 0x020E01B8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT18" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT19", 0x020E01BC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT19" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT2", 0x020E0178, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT2" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT20", 0x020E01C0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT20" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT21", 0x020E01C4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT21" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT22", 0x020E01C8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT22" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT23", 0x020E01CC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT23" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT3", 0x020E017C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT3" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT4", 0x020E0180, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT4" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT5", 0x020E0184, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT5" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT6", 0x020E0188, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT6" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT7", 0x020E018C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT7" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT8", 0x020E0190, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT8" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT9", 0x020E0194, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_DISP0_DAT9" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_A16", 0x020E00F4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_A16" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_A17", 0x020E00F0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_A17" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_A18", 0x020E00EC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_A18" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_A19", 0x020E00E8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_A19" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_A20", 0x020E00E4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_A20" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_A21", 0x020E00E0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_A21" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_A22", 0x020E00DC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_A22" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_A23", 0x020E00D8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_A23" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_A24", 0x020E00D4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_A24" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_A25", 0x020E0088, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_A25" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK", 0x020E0158, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_CS0", 0x020E00F8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_CS0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_CS1", 0x020E00FC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_CS1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D16", 0x020E0090, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D16" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D17", 0x020E0094, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D17" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D18", 0x020E0098, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D18" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D19", 0x020E009C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D19" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D20", 0x020E00A0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D20" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D21", 0x020E00A4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D21" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D22", 0x020E00A8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D22" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D23", 0x020E00AC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D23" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D24", 0x020E00B4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D24" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D25", 0x020E00B8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D25" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D26", 0x020E00BC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D26" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D27", 0x020E00C0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D27" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D28", 0x020E00C4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D28" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D29", 0x020E00C8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D29" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D30", 0x020E00CC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D30" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_D31", 0x020E00D0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_D31" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA0", 0x020E0114, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA1", 0x020E0118, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA10", 0x020E013C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA10" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA11", 0x020E0140, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA11" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA12", 0x020E0144, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA12" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA13", 0x020E0148, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA13" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA14", 0x020E014C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA14" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA15", 0x020E0150, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA15" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA2", 0x020E011C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA2" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA3", 0x020E0120, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA3" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA4", 0x020E0124, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA4" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA5", 0x020E0128, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA5" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA6", 0x020E012C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA6" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA7", 0x020E0130, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA7" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA8", 0x020E0134, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA8" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_DA9", 0x020E0138, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_DA9" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_EB0", 0x020E010C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_EB0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_EB1", 0x020E0110, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_EB1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_EB2", 0x020E008C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_EB2" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_EB3", 0x020E00B0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_EB3" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_LBA", 0x020E0108, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_LBA" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_OE", 0x020E0100, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_OE" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_RW", 0x020E0104, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_RW" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT", 0x020E0154, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV", 0x020E01DC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_ENET_MDC", 0x020E01F4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_ENET_MDC" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO", 0x020E01D0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK", 0x020E01D4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_ENET_RXD0", 0x020E01E4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_ENET_RXD0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_ENET_RXD1", 0x020E01E0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_ENET_RXD1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER", 0x020E01D8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_ENET_TXD0", 0x020E01F0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_ENET_TXD0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_ENET_TXD1", 0x020E01EC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_ENET_TXD1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN", 0x020E01E8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_GPIO_0", 0x020E0220, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_GPIO_0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_GPIO_1", 0x020E0224, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_GPIO_1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_GPIO_16", 0x020E0248, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_GPIO_16" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_GPIO_17", 0x020E024C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_GPIO_17" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_GPIO_18", 0x020E0250, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_GPIO_18" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_GPIO_19", 0x020E0254, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_GPIO_19" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_GPIO_2", 0x020E0234, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_GPIO_2" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_GPIO_3", 0x020E022C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_GPIO_3" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_GPIO_4", 0x020E0238, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_GPIO_4" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_GPIO_5", 0x020E023C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_GPIO_5" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_GPIO_6", 0x020E0230, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_GPIO_6" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_GPIO_7", 0x020E0240, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_GPIO_7" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_GPIO_8", 0x020E0244, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_GPIO_8" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_GPIO_9", 0x020E0228, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_GPIO_9" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_KEY_COL0", 0x020E01F8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_KEY_COL0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_KEY_COL1", 0x020E0200, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_KEY_COL1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_KEY_COL2", 0x020E0208, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_KEY_COL2" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_KEY_COL3", 0x020E0210, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_KEY_COL3" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_KEY_COL4", 0x020E0218, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_KEY_COL4" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0", 0x020E01FC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1", 0x020E0204, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2", 0x020E020C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3", 0x020E0214, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4", 0x020E021C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE", 0x020E02D8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE", 0x020E02D4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0", 0x020E02E4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1", 0x020E02E8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2", 0x020E02EC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3", 0x020E02F0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_D0", 0x020E02FC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_D0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_D1", 0x020E0300, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_D1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_D2", 0x020E0304, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_D2" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_D3", 0x020E0308, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_D3" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_D4", 0x020E030C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_D4" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_D5", 0x020E0310, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_D5" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_D6", 0x020E0314, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_D6" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_D7", 0x020E0318, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_D7" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0", 0x020E02E0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B", 0x020E02DC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0", 0x020E0070, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1", 0x020E0078, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2", 0x020E007C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3", 0x020E0080, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC", 0x020E0084, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL", 0x020E006C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0", 0x020E005C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1", 0x020E0060, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2", 0x020E0064, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3", 0x020E0068, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC", 0x020E0058, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL", 0x020E0074, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD1_CLK", 0x020E0350, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD1_CLK" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD1_CMD", 0x020E0348, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD1_CMD" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD1_DAT0", 0x020E0340, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD1_DAT0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD1_DAT1", 0x020E033C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD1_DAT1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD1_DAT2", 0x020E034C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD1_DAT2" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD1_DAT3", 0x020E0344, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD1_DAT3" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD2_CLK", 0x020E0354, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD2_CLK" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD2_CMD", 0x020E0358, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD2_CMD" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD2_DAT0", 0x020E0054, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD2_DAT0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD2_DAT1", 0x020E004C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD2_DAT1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD2_DAT2", 0x020E0050, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD2_DAT2" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD2_DAT3", 0x020E035C, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD2_DAT3" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD3_CLK", 0x020E02BC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD3_CLK" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD3_CMD", 0x020E02B8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD3_CMD" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD3_DAT0", 0x020E02C0, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD3_DAT0" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD3_DAT1", 0x020E02C4, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD3_DAT1" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD3_DAT2", 0x020E02C8, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD3_DAT2" },
+//{ "IOMUXC_SW_MUX_CTL_PAD_SD3_DAT3", 0x020E02CC, 0, 0xffffffff, 'x', "IOMUXC_SW_MUX_CTL_PAD_SD3_DAT3...
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