[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-696-g2d999f7
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-696-g2d999f7
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From: Sébastien S. <ss...@us...> - 2015-04-09 08:47:55
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 2d999f705bf170b1b63431d725ad2c69c9b64c91 (commit)
from 3d1d84432b8697156e216fb0c1ad604a116718c6 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 2d999f705bf170b1b63431d725ad2c69c9b64c91
Author: Sébastien Szymanski <seb...@ar...>
Date: Thu Apr 9 10:50:40 2015 +0200
[LINUX] 3.19/4.0: apf6: dts: Update some muxing configs...
Done by Nicolas ;)
-----------------------------------------------------------------------
Summary of changes:
...rmadeus-add-apf6q-and-apf6dl-device-trees.patch | 179 ++++++++++----------
...rmadeus-add-apf6q-and-apf6dl-device-trees.patch | 179 ++++++++++----------
2 files changed, 180 insertions(+), 178 deletions(-)
diff --git a/patches/linux/3.19/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch b/patches/linux/3.19/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch
index 62b078a..92ff286 100644
--- a/patches/linux/3.19/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch
+++ b/patches/linux/3.19/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch
@@ -1,10 +1,10 @@
-Index: linux-3.18-rc5/arch/arm/boot/dts/imx6q-apf6dev.dts
+Index: linux-3.19.3/arch/arm/boot/dts/imx6q-apf6dev.dts
===================================================================
--- /dev/null
-+++ linux-3.18-rc5/arch/arm/boot/dts/imx6q-apf6dev.dts
++++ linux-3.19.3/arch/arm/boot/dts/imx6q-apf6dev.dts
@@ -0,0 +1,28 @@
+/*
-+ * Copyright 2014 Armadeus Systems
++ * Copyright 2015 Armadeus Systems
+ *
+ * Author: Armadeus Systems <su...@ar...>
+ *
@@ -24,20 +24,20 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6q-apf6dev.dts
+ compatible = "armadeus,imx6q-apf6dev", "armadeus,imx6q-apf6", "fsl,imx6q";
+
+ memory {
-+ reg = <0x10000000 0x80000000>;
++ reg = <0x10000000 0x40000000>;
+ };
+};
+
+&sata {
+ status = "okay";
+};
-Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+Index: linux-3.19.3/arch/arm/boot/dts/imx6qdl-apf6.dtsi
===================================================================
--- /dev/null
-+++ linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6.dtsi
++++ linux-3.19.3/arch/arm/boot/dts/imx6qdl-apf6.dtsi
@@ -0,0 +1,133 @@
+/*
-+ * Copyright 2014 Armadeus Systems
++ * Copyright 2015 Armadeus Systems
+ *
+ * Author: Armadeus Systems <su...@ar...>
+ *
@@ -77,7 +77,7 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-duration = <10>;
-+ phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
++ phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
@@ -110,33 +110,33 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+ apf6 {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
-+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
++ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
-+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
-+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
-+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030
-+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
-+ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x80000000
-+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
-+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
-+ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
-+ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
-+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
-+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* BT_EN */
++ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0
++ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0
++ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0
++ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0
++ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */
+ >;
+ };
+
@@ -148,8 +148,8 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
-+ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x80000000 /* WL_EN */
-+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x80000000 /* WL_IRQ */
++ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* WL_EN */
++ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* WL_IRQ */
+ >;
+ };
+
@@ -169,13 +169,13 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+ };
+ };
+};
-Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+Index: linux-3.19.3/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
===================================================================
--- /dev/null
-+++ linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
-@@ -0,0 +1,521 @@
++++ linux-3.19.3/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+@@ -0,0 +1,522 @@
+/*
-+ * Copyright 2014 Armadeus Systems
++ * Copyright 2015 Armadeus Systems
+ *
+ * Author: Armadeus Systems <su...@ar...>
+ *
@@ -336,9 +336,9 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ fsl,spi-num-chipselects = <3>;
-+ cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>,
-+ <&gpio4 10 GPIO_ACTIVE_HIGH>,
-+ <&gpio4 11 GPIO_ACTIVE_HIGH>;
++ cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>,
++ <&gpio4 10 GPIO_ACTIVE_LOW>,
++ <&gpio4 11 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
@@ -493,7 +493,7 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
-+ cd-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
++ cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ status = "okay";
+};
@@ -516,10 +516,10 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+ apf6dev {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
-+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
-+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
-+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
++ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
++ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
++ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
++ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ >;
+ };
@@ -537,16 +537,16 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
-+ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x80000000
-+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000
-+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000
++ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
++ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
++ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
-+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
-+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
++ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
++ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
+ >;
+ };
+
@@ -555,29 +555,31 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
++
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0
+ >;
+ };
+
+ pinctrl_gpios: gpiosgrp {
+ fsl,pins = <
-+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x80000000
-+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x80000000
-+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x80000000
-+ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
-+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x80000000
-+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000
-+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x80000000
-+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000
++ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
++ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
++ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
++ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
++ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
++ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
++ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
++ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
++ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
+ >;
+ };
+
+ pinctrl_gsm: gsmgrp {
+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* GSM_POKIN */
-+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* GSM_PWR_EN */
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* GSM_POKIN */
++ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */
+ >;
+ };
+
@@ -604,35 +606,34 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+
+ pinctrl_ipu1_disp1: ipu1disp1grp {
+ fsl,pins = <
-+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
-+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
-+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
-+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
-+ MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
-+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
-+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
-+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
-+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
-+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
-+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
-+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
-+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
-+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
-+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
-+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
-+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
-+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
-+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
-+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
-+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
-+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
-+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
++ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1
++ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1
++ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100b1
++ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100b1
++ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100b1
++ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100b1
++ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100b1
++ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100b1
++ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100b1
++ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100b1
++ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100b1
++ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100b1
++ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100b1
++ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100b1
++ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100b1
++ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100b1
++ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100b1
++ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100b1
++ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100b1
++ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100b1
++ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100b1
++ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100b1
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x80000000
++ MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0
+ >;
+ };
+
@@ -644,30 +645,30 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
-+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0
++ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
-+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
-+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
-+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
-+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
++ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b0
++ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
++ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
++ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
-+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0
++ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0
+ >;
+ };
+
@@ -690,18 +691,18 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+
+ pinctrl_touchscreen: touchscreengrp {
+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x80000000
++ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0
+ >;
+ };
+ };
+};
-Index: linux-3.18-rc5/arch/arm/boot/dts/imx6dl-apf6dev.dts
+Index: linux-3.19.3/arch/arm/boot/dts/imx6dl-apf6dev.dts
===================================================================
--- /dev/null
-+++ linux-3.18-rc5/arch/arm/boot/dts/imx6dl-apf6dev.dts
++++ linux-3.19.3/arch/arm/boot/dts/imx6dl-apf6dev.dts
@@ -0,0 +1,24 @@
+/*
-+ * Copyright 2014 Armadeus Systems
++ * Copyright 2015 Armadeus Systems
+ *
+ * Author: Armadeus Systems <su...@ar...>
+ *
@@ -717,10 +718,10 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6dl-apf6dev.dts
+#include "imx6qdl-apf6dev.dtsi"
+
+/ {
-+ model = "Armadeus APF6 i.MX6 Dual Lite Module on APF6Dev Board";
++ model = "Armadeus APF6 i.MX6 Solo Module on APF6Dev Board";
+ compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl";
+
+ memory {
-+ reg = <0x10000000 0x40000000>;
++ reg = <0x10000000 0x20000000>;
+ };
+};
diff --git a/patches/linux/4.0/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch b/patches/linux/4.0/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch
index 62b078a..92ff286 100644
--- a/patches/linux/4.0/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch
+++ b/patches/linux/4.0/0450-armadeus-add-apf6q-and-apf6dl-device-trees.patch
@@ -1,10 +1,10 @@
-Index: linux-3.18-rc5/arch/arm/boot/dts/imx6q-apf6dev.dts
+Index: linux-3.19.3/arch/arm/boot/dts/imx6q-apf6dev.dts
===================================================================
--- /dev/null
-+++ linux-3.18-rc5/arch/arm/boot/dts/imx6q-apf6dev.dts
++++ linux-3.19.3/arch/arm/boot/dts/imx6q-apf6dev.dts
@@ -0,0 +1,28 @@
+/*
-+ * Copyright 2014 Armadeus Systems
++ * Copyright 2015 Armadeus Systems
+ *
+ * Author: Armadeus Systems <su...@ar...>
+ *
@@ -24,20 +24,20 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6q-apf6dev.dts
+ compatible = "armadeus,imx6q-apf6dev", "armadeus,imx6q-apf6", "fsl,imx6q";
+
+ memory {
-+ reg = <0x10000000 0x80000000>;
++ reg = <0x10000000 0x40000000>;
+ };
+};
+
+&sata {
+ status = "okay";
+};
-Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+Index: linux-3.19.3/arch/arm/boot/dts/imx6qdl-apf6.dtsi
===================================================================
--- /dev/null
-+++ linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6.dtsi
++++ linux-3.19.3/arch/arm/boot/dts/imx6qdl-apf6.dtsi
@@ -0,0 +1,133 @@
+/*
-+ * Copyright 2014 Armadeus Systems
++ * Copyright 2015 Armadeus Systems
+ *
+ * Author: Armadeus Systems <su...@ar...>
+ *
@@ -77,7 +77,7 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii";
+ phy-reset-duration = <10>;
-+ phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
++ phy-reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
@@ -110,33 +110,33 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+ apf6 {
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
-+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x130b0
++ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x130b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
-+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
-+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x13030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
-+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1f030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1f030
-+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
-+ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x80000000
-+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
-+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
-+ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
-+ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
-+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
-+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* BT_EN */
++ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b0
++ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b0
++ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b0
++ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b0
++ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x130b0 /* BT_EN */
+ >;
+ };
+
@@ -148,8 +148,8 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
-+ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x80000000 /* WL_EN */
-+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x80000000 /* WL_IRQ */
++ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 /* WL_EN */
++ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* WL_IRQ */
+ >;
+ };
+
@@ -169,13 +169,13 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+ };
+ };
+};
-Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+Index: linux-3.19.3/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
===================================================================
--- /dev/null
-+++ linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
-@@ -0,0 +1,521 @@
++++ linux-3.19.3/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+@@ -0,0 +1,522 @@
+/*
-+ * Copyright 2014 Armadeus Systems
++ * Copyright 2015 Armadeus Systems
+ *
+ * Author: Armadeus Systems <su...@ar...>
+ *
@@ -336,9 +336,9 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ fsl,spi-num-chipselects = <3>;
-+ cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>,
-+ <&gpio4 10 GPIO_ACTIVE_HIGH>,
-+ <&gpio4 11 GPIO_ACTIVE_HIGH>;
++ cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>,
++ <&gpio4 10 GPIO_ACTIVE_LOW>,
++ <&gpio4 11 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
@@ -493,7 +493,7 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
-+ cd-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
++ cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ status = "okay";
+};
@@ -516,10 +516,10 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+ apf6dev {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
-+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
-+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
-+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
++ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
++ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
++ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
++ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ >;
+ };
@@ -537,16 +537,16 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+ MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
-+ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x80000000
-+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x80000000
-+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000
++ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
++ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
++ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
-+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
-+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
++ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
++ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
+ >;
+ };
+
@@ -555,29 +555,31 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
++
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x130b0
+ >;
+ };
+
+ pinctrl_gpios: gpiosgrp {
+ fsl,pins = <
-+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x80000000
-+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x80000000
-+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x80000000
-+ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
-+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x80000000
-+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000
-+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x80000000
-+ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000
++ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x100b1
++ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
++ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x100b1
++ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x100b1
++ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x100b1
++ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x100b1
++ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x100b1
++ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x100b1
++ MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x100b1
+ >;
+ };
+
+ pinctrl_gsm: gsmgrp {
+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* GSM_POKIN */
-+ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* GSM_PWR_EN */
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x130b0 /* GSM_POKIN */
++ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x130b0 /* GSM_PWR_EN */
+ >;
+ };
+
@@ -604,35 +606,34 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+
+ pinctrl_ipu1_disp1: ipu1disp1grp {
+ fsl,pins = <
-+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
-+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
-+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
-+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
-+ MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
-+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
-+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
-+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
-+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
-+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
-+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
-+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
-+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
-+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
-+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
-+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
-+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
-+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
-+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
-+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
-+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
-+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
-+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
++ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100b1
++ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x100b1
++ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x100b1
++ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x100b1
++ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x100b1
++ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x100b1
++ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x100b1
++ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x100b1
++ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x100b1
++ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x100b1
++ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100b1
++ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x100b1
++ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x100b1
++ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x100b1
++ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x100b1
++ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x100b1
++ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x100b1
++ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x100b1
++ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x100b1
++ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x100b1
++ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x100b1
++ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x100b1
+ >;
+ };
+
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x80000000
++ MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x130b0
+ >;
+ };
+
@@ -644,30 +645,30 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
-+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b0
++ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
-+ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
-+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
-+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
-+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
++ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b0
++ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b0
++ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b0
++ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b0
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
-+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b0
++ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x1b0b0
+ >;
+ };
+
@@ -690,18 +691,18 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+
+ pinctrl_touchscreen: touchscreengrp {
+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x80000000
++ MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0
+ >;
+ };
+ };
+};
-Index: linux-3.18-rc5/arch/arm/boot/dts/imx6dl-apf6dev.dts
+Index: linux-3.19.3/arch/arm/boot/dts/imx6dl-apf6dev.dts
===================================================================
--- /dev/null
-+++ linux-3.18-rc5/arch/arm/boot/dts/imx6dl-apf6dev.dts
++++ linux-3.19.3/arch/arm/boot/dts/imx6dl-apf6dev.dts
@@ -0,0 +1,24 @@
+/*
-+ * Copyright 2014 Armadeus Systems
++ * Copyright 2015 Armadeus Systems
+ *
+ * Author: Armadeus Systems <su...@ar...>
+ *
@@ -717,10 +718,10 @@ Index: linux-3.18-rc5/arch/arm/boot/dts/imx6dl-apf6dev.dts
+#include "imx6qdl-apf6dev.dtsi"
+
+/ {
-+ model = "Armadeus APF6 i.MX6 Dual Lite Module on APF6Dev Board";
++ model = "Armadeus APF6 i.MX6 Solo Module on APF6Dev Board";
+ compatible = "armadeus,imx6dl-apf6dev", "armadeus,imx6dl-apf6", "fsl,imx6dl";
+
+ memory {
-+ reg = <0x10000000 0x40000000>;
++ reg = <0x10000000 0x20000000>;
+ };
+};
hooks/post-receive
--
armadeus
|