[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-569-ga31edb2
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-569-ga31edb2
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From: jorasse <jo...@us...> - 2015-02-05 19:08:36
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via a31edb2a533dbd82d67a203ec919c6e23dc088b9 (commit)
from ddaf6ce5fb03c550abd86d5959f833343653a826 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit a31edb2a533dbd82d67a203ec919c6e23dc088b9
Author: Eric Jarrige <eri...@ar...>
Date: Thu Feb 5 20:07:51 2015 +0100
[UBOOT] 2015.01: add patchwork to support U-Boot 2015.01
-----------------------------------------------------------------------
Summary of changes:
...-restore-command-env-param-compatitbility.patch | 0
...02-arm-support-continuous-mmu-mem-mapping.patch | 97 ++
.../003-nand_large_file_download.patch} | 0
.../004-i2c-mxc-fix-mx51-i2c-declaration.patch | 40 +
patches/u-boot/2015.01/100-apf9328-Kconfig.patch | 26 +
.../101-mx1-timer.patch} | 0
.../u-boot/{2013.04 => 2015.01}/102-mx1-i2c.patch | 0
patches/u-boot/2015.01/103-apf9328.patch | 1185 +++++++++++++++++++
.../{2014.04 => 2015.01}/106-mx1-pllclk.patch | 0
.../107-mx1-pllclk-debug.patch | 0
.../u-boot/{2014.04 => 2015.01}/108-DM9000.patch | 0
.../300-imx27-fix_dcache_boot_issue.patch | 0
.../2015.01/301-apf27-support-boot-from-RAM.patch | 27 +
.../u-boot/2015.01/302-imx-nand-lock-unlock.patch | 98 ++
.../303-spartan.patch} | 0
.../304-apf27-misc-commands.patch} | 0
patches/u-boot/2015.01/400-imx51.patch | 522 +++++++++
patches/u-boot/2015.01/401-apf51.patch | 1025 +++++++++++++++++
patches/u-boot/2015.01/402-apf51-Kconfig.patch | 27 +
patches/u-boot/2015.01/403-apf51-nand-spl-NG.patch | 361 ++++++
patches/u-boot/2015.01/500-apf28-Kconfig.patch | 28 +
.../u-boot/2015.01/501-imx28-update-and-fix.patch | 60 +
patches/u-boot/2015.01/502-add-apf28.patch | 1208 ++++++++++++++++++++
patches/u-boot/2015.01/600-add-apf6.patch | 986 ++++++++++++++++
..._bootstrap_get_uboot_image_on_serial_port.patch | 17 +
25 files changed, 5707 insertions(+), 0 deletions(-)
copy patches/u-boot/{2014.07 => 2015.01}/001-restore-command-env-param-compatitbility.patch (100%)
create mode 100644 patches/u-boot/2015.01/002-arm-support-continuous-mmu-mem-mapping.patch
copy patches/u-boot/{2014.04/350-nand_large_file_download.patch => 2015.01/003-nand_large_file_download.patch} (100%)
create mode 100644 patches/u-boot/2015.01/004-i2c-mxc-fix-mx51-i2c-declaration.patch
create mode 100644 patches/u-boot/2015.01/100-apf9328-Kconfig.patch
copy patches/u-boot/{2014.04/111-mx1-timer.patch => 2015.01/101-mx1-timer.patch} (100%)
copy patches/u-boot/{2013.04 => 2015.01}/102-mx1-i2c.patch (100%)
create mode 100644 patches/u-boot/2015.01/103-apf9328.patch
copy patches/u-boot/{2014.04 => 2015.01}/106-mx1-pllclk.patch (100%)
copy patches/u-boot/{2014.04 => 2015.01}/107-mx1-pllclk-debug.patch (100%)
copy patches/u-boot/{2014.04 => 2015.01}/108-DM9000.patch (100%)
copy patches/u-boot/{2014.07 => 2015.01}/300-imx27-fix_dcache_boot_issue.patch (100%)
create mode 100644 patches/u-boot/2015.01/301-apf27-support-boot-from-RAM.patch
create mode 100644 patches/u-boot/2015.01/302-imx-nand-lock-unlock.patch
copy patches/u-boot/{2014.07/320-spartan.patch => 2015.01/303-spartan.patch} (100%)
copy patches/u-boot/{2014.04/340-apf27-misc-commands.patch => 2015.01/304-apf27-misc-commands.patch} (100%)
create mode 100644 patches/u-boot/2015.01/400-imx51.patch
create mode 100644 patches/u-boot/2015.01/401-apf51.patch
create mode 100644 patches/u-boot/2015.01/402-apf51-Kconfig.patch
create mode 100644 patches/u-boot/2015.01/403-apf51-nand-spl-NG.patch
create mode 100644 patches/u-boot/2015.01/500-apf28-Kconfig.patch
create mode 100644 patches/u-boot/2015.01/501-imx28-update-and-fix.patch
create mode 100644 patches/u-boot/2015.01/502-add-apf28.patch
create mode 100644 patches/u-boot/2015.01/600-add-apf6.patch
create mode 100644 patches/u-boot/2015.01/601-apf6-in_bootstrap_get_uboot_image_on_serial_port.patch
diff --git a/patches/u-boot/2014.07/001-restore-command-env-param-compatitbility.patch b/patches/u-boot/2015.01/001-restore-command-env-param-compatitbility.patch
similarity index 100%
copy from patches/u-boot/2014.07/001-restore-command-env-param-compatitbility.patch
copy to patches/u-boot/2015.01/001-restore-command-env-param-compatitbility.patch
diff --git a/patches/u-boot/2015.01/002-arm-support-continuous-mmu-mem-mapping.patch b/patches/u-boot/2015.01/002-arm-support-continuous-mmu-mem-mapping.patch
new file mode 100644
index 0000000..e462a7d
--- /dev/null
+++ b/patches/u-boot/2015.01/002-arm-support-continuous-mmu-mem-mapping.patch
@@ -0,0 +1,97 @@
+ARM: support continuous MMU memory mapping beside the regular identity mapping.
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
+index 939de10..25f0ff1 100644
+--- a/arch/arm/lib/cache-cp15.c
++++ b/arch/arm/lib/cache-cp15.c
+@@ -32,14 +32,14 @@ static void cp_delay (void)
+ asm volatile("" : : : "memory");
+ }
+
+-void set_section_dcache(int section, enum dcache_option option)
++void set_section_dcache(int section, int section_index, enum dcache_option option)
+ {
+ u32 *page_table = (u32 *)gd->arch.tlb_addr;
+ u32 value;
+
+ value = (section << MMU_SECTION_SHIFT) | (3 << 10);
+ value |= option;
+- page_table[section] = value;
++ page_table[section_index] = value;
+ }
+
+ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
+@@ -58,11 +58,11 @@ void mmu_set_region_dcache_behaviour(u32
+ debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
+ option);
+ for (upto = start; upto < end; upto++)
+- set_section_dcache(upto, option);
++ set_section_dcache(upto, upto, option);
+ mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+ }
+
+-__weak void dram_bank_mmu_setup(int bank)
++__weak void dram_bank_mmu_setup(int bank, int page_offset)
+ {
+ bd_t *bd = gd->bd;
+ int i;
+@@ -72,11 +72,11 @@ __weak void dram_bank_mmu_setup(int bank
+ i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20);
+ i++) {
+ #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+- set_section_dcache(i, DCACHE_WRITETHROUGH);
++ set_section_dcache(i, page_offset++, DCACHE_WRITETHROUGH);
+ #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
+- set_section_dcache(i, DCACHE_WRITEALLOC);
++ set_section_dcache(i, page_offset++, DCACHE_WRITEALLOC);
+ #else
+- set_section_dcache(i, DCACHE_WRITEBACK);
++ set_section_dcache(i, page_offset++, DCACHE_WRITEBACK);
+ #endif
+ }
+ }
+@@ -86,14 +86,22 @@ static inline void mmu_setup(void)
+ {
+ int i;
+ u32 reg;
++ bd_t *bd = gd->bd;
++ int page_offset, continuity_offset;
+
+ arm_init_before_mmu();
+ /* Set up an identity-mapping for all 4GB, rw for everyone */
+ for (i = 0; i < 4096; i++)
+- set_section_dcache(i, DCACHE_OFF);
++ set_section_dcache(i, i, DCACHE_OFF);
+
++ continuity_offset = bd->bi_dram[0].start >> 20;
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+- dram_bank_mmu_setup(i);
++ page_offset = (bd->bi_dram[i].start) >> 20;
++ /* direct identity mapping */
++ dram_bank_mmu_setup(i, page_offset);
++ /* secondary mapping to build a continous memory space */
++ dram_bank_mmu_setup(i, continuity_offset);
++ continuity_offset = (bd->bi_dram[i].start + bd->bi_dram[i].size) >> 20;
+ }
+
+ /* Copy the page table address to cp15 */
+diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
+--- a/arch/arm/include/asm/cache.h
++++ b/arch/arm/include/asm/cache.h
+@@ -27,12 +27,12 @@ static inline void invalidate_l2_cache(v
+
+ void l2_cache_enable(void);
+ void l2_cache_disable(void);
+-void set_section_dcache(int section, enum dcache_option option);
++void set_section_dcache(int section, int section_index, enum dcache_option option);
+
+ void arm_init_before_mmu(void);
+ void arm_init_domains(void);
+ void cpu_cache_initialization(void);
+-void dram_bank_mmu_setup(int bank);
++void dram_bank_mmu_setup(int bank, int page_offset);
+
+ #endif
+
diff --git a/patches/u-boot/2014.04/350-nand_large_file_download.patch b/patches/u-boot/2015.01/003-nand_large_file_download.patch
similarity index 100%
copy from patches/u-boot/2014.04/350-nand_large_file_download.patch
copy to patches/u-boot/2015.01/003-nand_large_file_download.patch
diff --git a/patches/u-boot/2015.01/004-i2c-mxc-fix-mx51-i2c-declaration.patch b/patches/u-boot/2015.01/004-i2c-mxc-fix-mx51-i2c-declaration.patch
new file mode 100644
index 0000000..04f72f5
--- /dev/null
+++ b/patches/u-boot/2015.01/004-i2c-mxc-fix-mx51-i2c-declaration.patch
@@ -0,0 +1,40 @@
+From 8cc45b2a0332154b9ef2deaa3085da90f4397da7 Mon Sep 17 00:00:00 2001
+From: Eric Jarrige <eri...@ar...>
+Date: Tue, 13 May 2014 14:22:51 +0200
+Subject: [PATCH 1/1] i2c: mxc: fix mx51 i2c declaration
+
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+ drivers/i2c/mxc_i2c.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
+index 595019b..a4280b4 100644
+--- a/drivers/i2c/mxc_i2c.c
++++ b/drivers/i2c/mxc_i2c.c
+@@ -410,8 +410,11 @@ static void * const i2c_bases[] = {
+ #elif defined(CONFIG_MX27)
+ (void *)IMX_I2C1_BASE,
+ (void *)IMX_I2C2_BASE
++#elif defined(CONFIG_MX51)
++ (void *)I2C1_BASE_ADDR,
++ (void *)I2C2_BASE_ADDR,
+ #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
+- defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
++ defined(CONFIG_MX53) || \
+ defined(CONFIG_MX6) || defined(CONFIG_LS102XA)
+ (void *)I2C1_BASE_ADDR,
+ (void *)I2C2_BASE_ADDR,
+@@ -544,7 +547,7 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
+ CONFIG_SYS_MXC_I2C2_SPEED,
+ CONFIG_SYS_MXC_I2C2_SLAVE, 1)
+ #if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
+- defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
++ defined(CONFIG_MX53) ||\
+ defined(CONFIG_MX6) || defined(CONFIG_LS102XA)
+ U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
+ mxc_i2c_read, mxc_i2c_write,
+--
+1.7.9.5
+
diff --git a/patches/u-boot/2015.01/100-apf9328-Kconfig.patch b/patches/u-boot/2015.01/100-apf9328-Kconfig.patch
new file mode 100644
index 0000000..5db05c1
--- /dev/null
+++ b/patches/u-boot/2015.01/100-apf9328-Kconfig.patch
@@ -0,0 +1,26 @@
+apf9328: add apf9328 in Kconfig
+
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -260,6 +260,10 @@ config TARGET_APF27
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
++config TARGET_APF9328
++ bool "Support apf9328"
++ select CPU_ARM920T
++
+ config TARGET_IMX27LITE
+ bool "Support imx27lite"
+ select CPU_ARM926EJS
+@@ -852,6 +856,7 @@ source "board/Marvell/gplugd/Kconfig"
+ source "board/afeb9260/Kconfig"
+ source "board/altera/socfpga/Kconfig"
+ source "board/armadeus/apf27/Kconfig"
++source "board/armadeus/apf9328/Kconfig"
+ source "board/armltd/integrator/Kconfig"
+ source "board/armltd/vexpress/Kconfig"
+ source "board/armltd/vexpress64/Kconfig"
diff --git a/patches/u-boot/2014.04/111-mx1-timer.patch b/patches/u-boot/2015.01/101-mx1-timer.patch
similarity index 100%
copy from patches/u-boot/2014.04/111-mx1-timer.patch
copy to patches/u-boot/2015.01/101-mx1-timer.patch
diff --git a/patches/u-boot/2013.04/102-mx1-i2c.patch b/patches/u-boot/2015.01/102-mx1-i2c.patch
similarity index 100%
copy from patches/u-boot/2013.04/102-mx1-i2c.patch
copy to patches/u-boot/2015.01/102-mx1-i2c.patch
diff --git a/patches/u-boot/2015.01/103-apf9328.patch b/patches/u-boot/2015.01/103-apf9328.patch
new file mode 100644
index 0000000..0f9bdac
--- /dev/null
+++ b/patches/u-boot/2015.01/103-apf9328.patch
@@ -0,0 +1,1185 @@
+apf9328: Add Armadeus Project board APF9328
+
+Add Armadeus Project board APF9328
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Nicolas Colombain <nic...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Nicolas Colombain <nic...@ar...>
+---
+ board/armadeus/apf9328/Makefile | 51 ++++
+ board/armadeus/apf9328/apf9328.c | 106 +++++++
+ board/armadeus/apf9328/apf9328fpga.c | 100 +++++++
+ board/armadeus/apf9328/apf9328fpga.h | 31 ++
+ board/armadeus/apf9328/eeprom.c | 88 ++++++
+ board/armadeus/apf9328/fpga.c | 121 ++++++++
+ board/armadeus/apf9328/fpga.h | 30 ++
+ board/armadeus/apf9328/i2c.c | 276 +++++++++++++++++++
+ board/armadeus/apf9328/lowlevel_init.S | 469 ++++++++++++++++++++++++++++++++
+ 9 files changed, 1272 insertions(+), 0 deletions(-)
+ create mode 100644 board/armadeus/apf9328/Makefile
+ create mode 100644 board/armadeus/apf9328/apf9328.c
+ create mode 100644 board/armadeus/apf9328/apf9328fpga.c
+ create mode 100644 board/armadeus/apf9328/apf9328fpga.h
+ create mode 100644 board/armadeus/apf9328/eeprom.c
+ create mode 100644 board/armadeus/apf9328/fpga.c
+ create mode 100644 board/armadeus/apf9328/fpga.h
+ create mode 100644 board/armadeus/apf9328/i2c.c
+ create mode 100644 board/armadeus/apf9328/lowlevel_init.S
+
+diff --git a/board/armadeus/apf9328/Makefile b/board/armadeus/apf9328/Makefile
+new file mode 100644
+index 0000000..0f097cd
+--- /dev/null
++++ b/board/armadeus/apf9328/Makefile
+@@ -0,0 +1,10 @@
++#
++# (C) Copyright 2000-2004
++# Wolfgang Denk, DENX Software Engineering, wd...@de....
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y := apf9328.o i2c.o eeprom.o
++obj-y += lowlevel_init.o
++obj-$(CONFIG_FPGA) += apf9328fpga.o fpga.o
+diff --git a/board/armadeus/apf9328/apf9328.c b/board/armadeus/apf9328/apf9328.c
+new file mode 100644
+index 0000000..280f749
+--- /dev/null
++++ b/board/armadeus/apf9328/apf9328.c
+@@ -0,0 +1,61 @@
++/*
++ * Copyright (C) 2005-2015
++ * Nicolas Colombain <nic...@ar...>
++ * Eric Jarrige <eri...@ar...>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/arch/imx-regs.h>
++#include <flash.h>
++#include <netdev.h>
++#include "apf9328fpga.h"
++
++extern void imx_gpio_mode(int gpio_mode);
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int board_init(void)
++{
++
++ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
++
++#ifdef CONFIG_DRIVER_DM9000
++ imx_gpio_mode(GPIO_PORTB | GPIO_DR | GPIO_IN | 14);
++#endif
++
++#ifdef CONFIG_FPGA
++ apf9328_init_fpga();
++#endif
++
++ return 0;
++}
++
++int dram_init(void)
++{
++ /* dram_init must store complete ramsize in gd->ram_size */
++ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
++ PHYS_SDRAM_1_SIZE);
++ return 0;
++}
++
++void enable_caches(void)
++{
++#ifndef CONFIG_SYS_DCACHE_OFF
++ /* Enable D-cache. I-cache is already enabled in start.S */
++ dcache_enable();
++#endif
++}
++
++void show_boot_progress(int status)
++{
++ return;
++}
++
++#ifdef CONFIG_DRIVER_DM9000
++int board_eth_init(bd_t *bis)
++{
++ return dm9000_initialize(bis);
++}
++#endif
+diff --git a/board/armadeus/apf9328/apf9328fpga.c b/board/armadeus/apf9328/apf9328fpga.c
+new file mode 100644
+index 0000000..9782115
+--- /dev/null
++++ b/board/armadeus/apf9328/apf9328fpga.c
+@@ -0,0 +1,65 @@
++/*
++ * Copyright (C) 2005-2015
++ * Nicolas Colombain <nic...@ar...>
++ * Eric Jarrige <eri...@ar...>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++/*
++ * Spartan 3 FPGA configuration support for the APF9328 daughter board
++ */
++
++#include <common.h>
++#include <spartan3.h>
++#include <command.h>
++#include <jffs2/jffs2.h>
++#include <asm/arch/imx-regs.h>
++#include <asm/io.h>
++#include "apf9328fpga.h"
++
++#ifdef CONFIG_FPGA
++DECLARE_GLOBAL_DATA_PTR;
++/* Note that these are pointers to code that is in Flash. They will be
++ * relocated at runtime.
++ * Spartan3 code is used to download our Spartan 3 :) code is compatible.
++ * Just take care about the file size
++*/
++xilinx_spartan3_slave_serial_fns fpga_fns = {
++ fpga_pre_fn,
++ fpga_pgm_fn,
++ fpga_clk_fn,
++ fpga_init_fn,
++ fpga_done_fn,
++ fpga_wr_fn,
++ fpga_post_fn,
++ NULL,
++ fpga_abort_fn,
++};
++
++xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
++ {xilinx_spartan3,
++ slave_serial,
++ XILINX_XC3S400_SIZE,
++ (void *)&fpga_fns,
++ 0,
++ &spartan3_op }
++};
++
++/*
++ * Initialize the fpga. Return 1 on success, 0 on failure.
++ */
++int apf9328_init_fpga(void)
++{
++ int i;
++
++ fpga_init();
++
++ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
++ fpga_add(fpga_xilinx, &fpga[i]);
++ }
++
++ return 0;
++}
++
++#endif /* CONFIG_FPGA */
+diff --git a/board/armadeus/apf9328/apf9328fpga.h b/board/armadeus/apf9328/apf9328fpga.h
+new file mode 100644
+index 0000000..2a15443
+--- /dev/null
++++ b/board/armadeus/apf9328/apf9328fpga.h
+@@ -0,0 +1,10 @@
++/*
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++/*
++ * Spartan 3 FPGA configuration support for the APF9328 daughter board
++ */
++
++#include "fpga.h"
++extern int apf9328_init_fpga(void);
+diff --git a/board/armadeus/apf9328/eeprom.c b/board/armadeus/apf9328/eeprom.c
+new file mode 100644
+index 0000000..c8165ea
+--- /dev/null
++++ b/board/armadeus/apf9328/eeprom.c
+@@ -0,0 +1,72 @@
++/*
++ * Copyright (C) 2008-2015 Armadeus Project
++ * Copyright (C) 2007
++ * Stefano Babic, DENX Software Engineering, sb...@de....
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <command.h>
++#include <dm9000.h>
++
++static int do_read_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
++ char * const argv[])
++{
++ unsigned int i;
++ u8 data[2];
++
++ for (i = 0; i < 0x40; i++) {
++ if (!(i % 0x10))
++ printf("\n%08x:", i);
++ dm9000_read_srom_word(i, data);
++ printf(" %02x%02x", data[1], data[0]);
++ }
++ printf("\n");
++ return 0;
++}
++
++static int do_write_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
++ char * const argv[])
++{
++ unsigned long offset, value;
++
++ if (argc < 4) {
++ cmd_usage(cmdtp);
++ return 1;
++ }
++
++ strict_strtoul(argv[2], 16, &offset);
++ strict_strtoul(argv[3], 16, &value);
++ if (offset > 0x40) {
++ printf("Wrong offset : 0x%lx\n", offset);
++ cmd_usage(cmdtp);
++ return 1;
++ }
++ dm9000_write_srom_word(offset, value);
++ return 0;
++}
++
++int do_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
++{
++ if (argc < 2) {
++ cmd_usage(cmdtp);
++ return 1;
++ }
++
++ if (strcmp(argv[1], "read") == 0) {
++ return do_read_dm9000_eeprom(cmdtp, flag, argc, argv);
++ } else if (strcmp(argv[1], "write") == 0) {
++ return do_write_dm9000_eeprom(cmdtp, flag, argc, argv);
++ } else {
++ cmd_usage(cmdtp);
++ return 1;
++ }
++}
++
++U_BOOT_CMD(dm9000ee, 4, 1, do_dm9000_eeprom,
++ "Read/Write eeprom connected to Ethernet Controller",
++ "\ndm9000ee write <word offset> <value>\n"
++ "\tdm9000ee read\n"
++ "\tword:\t\t00-02 : MAC Address\n"
++ "\t\t\t03-07 : DM9000 Configuration\n" "\t\t\t08-63 : User data");
+diff --git a/board/armadeus/apf9328/fpga.c b/board/armadeus/apf9328/fpga.c
+new file mode 100644
+index 0000000..f3d4f03
+--- /dev/null
++++ b/board/armadeus/apf9328/fpga.c
+@@ -0,0 +1,116 @@
++/*
++ * Copyright (C) 2007
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++#include <common.h>
++
++#ifdef CONFIG_FPGA
++
++#include <asm/arch/imx-regs.h>
++#include <asm/io.h>
++#include <config.h>
++
++extern void imx_gpio_mode(int gpio_mode);
++
++#define GPIO_PORT(x) ((x >> 5) & 3)
++#define GPIO_SET(x) (DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
++#define GPIO_CLEAR(x) (DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
++#define GPIO_WRITE(x, y) (y ? GPIO_SET(x) : GPIO_CLEAR(x))
++#define GPIO_READ(x) ((SSR(GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK))))
++
++/*
++ * Port bit numbers for the serial slave controls
++ */
++#define FPGA_INIT CONFIG_SYS_FPGA_INIT
++#define FPGA_DONE CONFIG_SYS_FPGA_DONE
++#define FPGA_DIN CONFIG_SYS_FPGA_DATA
++#define FPGA_PROGRAM CONFIG_SYS_FPGA_PRG
++#define FPGA_CLOCK CONFIG_SYS_FPGA_CLK
++
++/* Note that these are pointers to code that is in Flash. They will be
++ * relocated at runtime.
++ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
++ * Just take care about the file size
++*/
++
++/*
++ * nitialize GPIO port B before download
++ */
++int fpga_pre_fn(int cookie)
++{
++ debug("%s:%d: FPGA PRE ", __func__, __LINE__);
++
++ /* Initialize GPIO pins */
++ imx_gpio_mode(FPGA_INIT | GPIO_DR | GPIO_IN);
++ imx_gpio_mode(FPGA_DONE | GPIO_DR | GPIO_IN);
++ imx_gpio_mode(FPGA_DIN | GPIO_DR | GPIO_OUT);
++ imx_gpio_mode(FPGA_PROGRAM | GPIO_DR | GPIO_OUT);
++ imx_gpio_mode(FPGA_CLOCK | GPIO_DR | GPIO_OUT);
++ return cookie;
++}
++
++/*
++ * Set the FPGA's active-low program line to the specified level
++ */
++int fpga_pgm_fn(int assert, int flush, int cookie)
++{
++ debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
++ assert ? "high" : "low");
++ GPIO_WRITE(FPGA_PROGRAM, !assert);
++ return assert;
++}
++
++/*
++ * Set the FPGA's active-high clock line to the specified level
++ */
++int fpga_clk_fn(int assert_clk, int flush, int cookie)
++{
++ debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
++ assert_clk ? "high" : "low");
++ GPIO_WRITE(FPGA_CLOCK, assert_clk);
++ return assert_clk;
++}
++
++/*
++ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
++ * asserted (low).
++ */
++int fpga_init_fn(int cookie)
++{
++ debug("%s:%d: INIT check... ", __func__, __LINE__);
++ return !GPIO_READ(FPGA_INIT);
++}
++
++/*
++ * Test the state of the active-high FPGA DONE pin
++ */
++int fpga_done_fn(int cookie)
++{
++ debug("%s:%d: DONE check... ", __func__, __LINE__);
++ return GPIO_READ(FPGA_DONE);
++}
++
++/*
++ * Set the FPGA's data line to the specified level
++ */
++int fpga_wr_fn(int assert_write, int flush, int cookie)
++{
++ debug("%s:%d: DATA write... ", __func__, __LINE__);
++ GPIO_WRITE(FPGA_DIN, assert_write);
++ return assert_write;
++}
++
++int fpga_post_fn(int cookie)
++{
++ return cookie;
++}
++
++int fpga_abort_fn(int cookie)
++{
++ return fpga_post_fn(cookie);
++}
++
++#endif /* CONFIG_FPGA */
+diff --git a/board/armadeus/apf9328/fpga.h b/board/armadeus/apf9328/fpga.h
+new file mode 100644
+index 0000000..3b226d7
+--- /dev/null
++++ b/board/armadeus/apf9328/fpga.h
+@@ -0,0 +1,15 @@
++/*
++ * Copyright (C) 2002
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++extern int fpga_pre_fn(int cookie);
++extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
++extern int fpga_init_fn(int cookie);
++extern int fpga_done_fn(int cookie);
++extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
++extern int fpga_wr_fn(int assert_write, int flush, int cookie);
++extern int fpga_post_fn(int cookie);
++extern int fpga_abort_fn(int cookie);
+diff --git a/board/armadeus/apf9328/i2c.c b/board/armadeus/apf9328/i2c.c
+new file mode 100644
+index 0000000..0ba0a8d
+--- /dev/null
++++ b/board/armadeus/apf9328/i2c.c
+@@ -0,0 +1,260 @@
++/*
++ * Copyright (C) 2005-2015 Eric Jarrige <eri...@ar...>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++
++#ifdef CONFIG_HARD_I2C
++
++#include <asm/io.h>
++#include <asm/arch/imx-regs.h>
++#include <i2c.h>
++
++extern void imx_gpio_mode(int gpio_mode);
++
++/*-----------------------------------------------------------------------
++ * Definitions
++ */
++
++#define I2C_ACK 0 /* level to ack a byte */
++#define I2C_NOACK 1 /* level to noack a byte */
++
++/*-----------------------------------------------------------------------
++ * Local functions
++ */
++
++/*-----------------------------------------------------------------------
++ * START: High -> Low on SDA while SCL is High
++ * after check for a bus free
++ */
++static void imxi2c_send_start(void)
++{
++ while (I2SR & I2SR_IBB)
++ udelay(1);
++
++ I2CR |= I2CR_MSTA;
++ I2SR &= ~I2SR_IIF;
++}
++
++/*-----------------------------------------------------------------------
++ * STOP: Low -> High on SDA while SCL is High
++ * after the end of previous transfer
++ */
++static void imxi2c_send_stop(void)
++{
++ while (!(I2SR & I2SR_ICF))
++ udelay(1);
++
++ I2CR &= ~I2CR_MSTA;
++}
++
++/*-----------------------------------------------------------------------
++ * Send 8 bits and look for an acknowledgement.
++ */
++static int imxi2c_write_byte(uchar data)
++{
++ while (!(I2SR & I2SR_ICF)) /* Wait end of transfer */
++ udelay(1);
++
++ I2CR |= I2CR_MTX;
++ I2SR &= ~I2SR_IIF;
++ I2DR = data;
++
++ while (!(I2SR & I2SR_IIF)) /* checking IIF before ICF: FIXME */
++ udelay(1);
++
++ I2SR &= ~I2SR_IIF;
++
++ while (!(I2SR & I2SR_ICF)) /* Wait end of transfer */
++ udelay(1);
++
++ return I2SR & I2SR_RXAK; /* not a nack is an ack */
++}
++
++/*-----------------------------------------------------------------------
++ * if ack == I2C_ACK, ACK the byte so can continue reading, else
++ * send I2C_NOACK to end the read.
++ */
++static uchar imxi2c_read_byte(int ack)
++{
++ int data;
++
++ while (!(I2SR & I2SR_ICF))
++ udelay(1);
++
++ I2CR &= ~I2CR_MTX;
++
++ if (ack)
++ I2CR |= I2CR_TXAK;
++ else
++ I2CR &= ~I2CR_TXAK;
++
++ data = I2DR;
++ return data;
++}
++
++/* ------------------------------------------------------------------------
++ * API Functions
++ * ------------------------------------------------------------------------
++ */
++
++/*-----------------------------------------------------------------------
++ * i2c_init compute the i2c divider to reach the requested speed
++ * see mxl reference manual
++ */
++void i2c_init(int speed, int slaveaddr)
++{
++ int hclk_dividers[] = {
++ 30, 32, 36, 42, 48, 52, 60, 72,
++ 80, 88, 104, 128, 144, 160, 192, 240,
++ 288, 320, 384, 480, 576, 640, 768, 960,
++ 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840,
++ 22, 24, 26, 26, 32, 36, 40, 44,
++ 48, 56, 64, 72, 80, 96, 112, 128,
++ 160, 192, 224, 256, 320, 384, 448, 512,
++ 640, 768, 896, 1024, 1280, 1536, 1792, 2048
++ };
++ int refDiv = get_HCLK() / speed;
++ int i, tmpIC;
++
++ imx_gpio_mode(PA15_PF_I2C_SDA);
++ imx_gpio_mode(PA16_PF_I2C_SCL);
++
++ tmpIC = (sizeof(hclk_dividers) / sizeof(int)) - 1;
++ for (i = tmpIC; i >= 0; i--) {
++ if ((hclk_dividers[i] >= refDiv)
++ && (hclk_dividers[i] < hclk_dividers[tmpIC])) {
++ tmpIC = i;
++ }
++ }
++
++ IFDR = tmpIC;
++ IADR = slaveaddr << 1;
++
++ if (I2SR & I2SR_IBB)
++ imxi2c_send_stop();
++
++ I2CR |= I2CR_IEN;
++}
++
++/*-----------------------------------------------------------------------
++ * Probe to see if a chip is present. Also good for checking for the
++ * completion of EEPROM writes since the chip stops responding until
++ * the write completes (typically 10mSec).
++ * probe sends a read command to probe a an address
++ */
++int i2c_probe(uchar addr)
++{
++ int rc;
++
++ imxi2c_send_start();
++ rc = imxi2c_write_byte((addr << 1) | 0);
++ imxi2c_send_stop();
++
++ return rc ? 1 : 0;
++}
++
++/*-----------------------------------------------------------------------
++ * Read bytes
++ */
++int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
++{
++ int shift;
++ debug("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
++ chip, addr, alen, buffer, len);
++
++#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
++ /*
++ * EEPROM chips that implement "address overflow" are ones
++ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
++ * address and the extra bits end up in the "chip address"
++ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
++ * four 256 byte chips.
++ *
++ * Note that we consider the length of the address field to
++ * still be one byte because the extra address bits are
++ * hidden in the chip address.
++ */
++ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
++
++ debug("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
++ chip, addr);
++#endif
++
++ /*
++ * Do the addressing portion of a write cycle to set the
++ * chip's address pointer. If the address length is zero,
++ * don't do the normal write cycle to set the address pointer,
++ * there is no address pointer in this chip.
++ */
++ imxi2c_send_start();
++ if (alen > 0) {
++ if (imxi2c_write_byte(chip << 1)) { /* write cycle */
++ imxi2c_send_stop();
++ debug("i2c_read, no chip responded %02X\n", chip);
++ return 1;
++ }
++ shift = (alen - 1) * 8;
++ while (alen-- > 0) {
++ if (imxi2c_write_byte(addr >> shift)) {
++ debug("i2c_read, address not <ACK>ed\n");
++ return 1;
++ }
++ shift -= 8;
++ }
++
++ /* reportedly some chips need a full stop */
++ imxi2c_send_stop();
++ imxi2c_send_start();
++ }
++ /*
++ * Send the chip address again, this time for a read cycle.
++ * Then read the data. On the last byte, we do a NACK instead
++ * of an ACK(len == 0) to terminate the read.
++ */
++ imxi2c_write_byte((chip << 1) | 1); /* read cycle */
++ imxi2c_read_byte(len <= 2);
++ while (len-- > 1)
++ *buffer++ = imxi2c_read_byte(len == 1);
++
++ imxi2c_send_stop();
++ *buffer++ = imxi2c_read_byte(0);
++ return 0;
++}
++
++/*-----------------------------------------------------------------------
++ * Write bytes
++ */
++int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
++{
++ int shift, failures = 0;
++
++ debug("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
++ chip, addr, alen, buffer, len);
++
++ imxi2c_send_start();
++ if (imxi2c_write_byte(chip << 1)) { /* write cycle */
++ imxi2c_send_stop();
++ debug("i2c_write, no chip responded %02X\n", chip);
++ return 1;
++ }
++ shift = (alen - 1) * 8;
++ while (alen-- > 0) {
++ if (imxi2c_write_byte(addr >> shift)) {
++ debug("i2c_write, address not <ACK>ed\n");
++ return 1;
++ }
++ shift -= 8;
++ }
++
++ while (len-- > 0) {
++ if (imxi2c_write_byte(*buffer++))
++ failures++;
++ }
++ imxi2c_send_stop();
++ return failures;
++}
++
++#endif /* CONFIG_HARD_I2C */
+diff --git a/board/armadeus/apf9328/lowlevel_init.S b/board/armadeus/apf9328/lowlevel_init.S
+new file mode 100644
+index 0000000..f080423
+--- /dev/null
++++ b/board/armadeus/apf9328/lowlevel_init.S
+@@ -0,0 +1,458 @@
++/*
++ * Copyright (C) 2005-2015 Eric Jarrige <eri...@ar...>
++ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <config.h>
++#include <version.h>
++#include <asm/arch/imx-regs.h>
++
++.globl lowlevel_init
++lowlevel_init:
++/* Change PERCLK1DIV to 14 ie 14+1 */
++ ldr r0, =PCDR
++ ldr r1, =CONFIG_SYS_PCDR_VAL
++ str r1, [r0]
++
++/* set MCU PLL Control Register 0 */
++
++ ldr r0, =MPCTL0
++ ldr r1, =CONFIG_SYS_MPCTL0_VAL
++ str r1, [r0]
++
++/* set MCU PLL Control Register 1 */
++
++ ldr r0, =MPCTL1
++ ldr r1, =CONFIG_SYS_MPCTL1_VAL
++ str r1, [r0]
++
++/* set mpll restart bit */
++ ldr r0, =CSCR
++ ldr r1, [r0]
++ orr r1,r1,#(1<<21)
++ str r1, [r0]
++
++ mov r2,#0x10
++1:
++ mov r3,#0x2000
++2:
++ subs r3,r3,#1
++ bne 2b
++
++ subs r2,r2,#1
++ bne 1b
++
++/* set System PLL Control Register 0 */
++
++ ldr r0, =SPCTL0
++ ldr r1, =CONFIG_SYS_SPCTL0_VAL
++ str r1, [r0]
++
++/* set System PLL Control Register 1 */
++
++ ldr r0, =SPCTL1
++ ldr r1, =CONFIG_SYS_SPCTL1_VAL
++ str r1, [r0]
++
++/* set spll restart bit */
++ ldr r0, =CSCR
++ ldr r1, [r0]
++ orr r1,r1,#(1<<22)
++ str r1, [r0]
++
++ mov r2,#0x10
++1:
++ mov r3,#0x2000
++2:
++ subs r3,r3,#1
++ bne 2b
++
++ subs r2,r2,#1
++ bne 1b
++
++ ldr r0, =CSCR
++ ldr r1, =CONFIG_SYS_CSCR_VAL
++ str r1, [r0]
++
++ ldr r0, =GPCR
++ ldr r1, =CONFIG_SYS_GPCR_VAL
++ str r1, [r0]
++
++/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
++ *this.....
++ *
++ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
++ * register 1, this stops it using the output of the PLL and thus runs at the
++ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
++ * use the value set in the CM_OSC registers...regardless of what you set it
++ * too! Thus, although i thought i was running at 140MHz, i'm actually running
++ * at 40!..
++
++ * Slapping this into my bootloader does the trick...
++
++ * MRC p15,0,r0,c1,c0,0 ; read core configuration register
++ * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
++ * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
++ * register
++ */
++ MRC p15,0,r0,c1,c0,0
++ ORR r0,r0,#0xC0000000
++ MCR p15,0,r0,c1,c0,0
++
++/* ldr r0, =GPR(0)
++ ldr r1, =CONFIG_SYS_GPR_A_VAL
++ str r1, [r0]
++*/
++
++ ldr r0, =DR(0)
++ ldr r1, =CONFIG_SYS_DR_A_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR1(0)
++ ldr r1, =CONFIG_SYS_OCR1_A_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR2(0)
++ ldr r1, =CONFIG_SYS_OCR2_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA1(0)
++ ldr r1, =CONFIG_SYS_ICFA1_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA2(0)
++ ldr r1, =CONFIG_SYS_ICFA2_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB1(0)
++ ldr r1, =CONFIG_SYS_ICFB1_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB2(0)
++ ldr r1, =CONFIG_SYS_ICFB2_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR1(0)
++ ldr r1, =CONFIG_SYS_ICR1_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR2(0)
++ ldr r1, =CONFIG_SYS_ICR2_A_VAL
++ str r1, [r0]
++
++ ldr r0, =IMR(0)
++ ldr r1, =CONFIG_SYS_IMR_A_VAL
++ str r1, [r0]
++
++ ldr r0, =DDIR(0)
++ ldr r1, =CONFIG_SYS_DDIR_A_VAL
++ str r1, [r0]
++
++ ldr r0, =GPR(0)
++ ldr r1, =CONFIG_SYS_GPR_A_VAL
++ str r1, [r0]
++
++ ldr r0, =PUEN(0)
++ ldr r1, =CONFIG_SYS_PUEN_A_VAL
++ str r1, [r0]
++
++ ldr r0, =GIUS(0)
++ ldr r1, =CONFIG_SYS_GIUS_A_VAL
++ str r1, [r0]
++
++ ldr r0, =DR(1)
++ ldr r1, =CONFIG_SYS_DR_B_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR1(1)
++ ldr r1, =CONFIG_SYS_OCR1_B_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR2(1)
++ ldr r1, =CONFIG_SYS_OCR2_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA1(1)
++ ldr r1, =CONFIG_SYS_ICFA1_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA2(1)
++ ldr r1, =CONFIG_SYS_ICFA2_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB1(1)
++ ldr r1, =CONFIG_SYS_ICFB1_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB2(1)
++ ldr r1, =CONFIG_SYS_ICFB2_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR1(1)
++ ldr r1, =CONFIG_SYS_ICR1_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR2(1)
++ ldr r1, =CONFIG_SYS_ICR2_B_VAL
++ str r1, [r0]
++
++ ldr r0, =IMR(1)
++ ldr r1, =CONFIG_SYS_IMR_B_VAL
++ str r1, [r0]
++
++ ldr r0, =DDIR(1)
++ ldr r1, =CONFIG_SYS_DDIR_B_VAL
++ str r1, [r0]
++
++ ldr r0, =GPR(1)
++ ldr r1, =CONFIG_SYS_GPR_B_VAL
++ str r1, [r0]
++
++ ldr r0, =PUEN(1)
++ ldr r1, =CONFIG_SYS_PUEN_B_VAL
++ str r1, [r0]
++
++ ldr r0, =GIUS(1)
++ ldr r1, =CONFIG_SYS_GIUS_B_VAL
++ str r1, [r0]
++
++ ldr r0, =DR(2)
++ ldr r1, =CONFIG_SYS_DR_C_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR1(2)
++ ldr r1, =CONFIG_SYS_OCR1_C_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR2(2)
++ ldr r1, =CONFIG_SYS_OCR2_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA1(2)
++ ldr r1, =CONFIG_SYS_ICFA1_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA2(2)
++ ldr r1, =CONFIG_SYS_ICFA2_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB1(2)
++ ldr r1, =CONFIG_SYS_ICFB1_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB2(2)
++ ldr r1, =CONFIG_SYS_ICFB2_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR1(2)
++ ldr r1, =CONFIG_SYS_ICR1_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR2(2)
++ ldr r1, =CONFIG_SYS_ICR2_C_VAL
++ str r1, [r0]
++
++ ldr r0, =IMR(2)
++ ldr r1, =CONFIG_SYS_IMR_C_VAL
++ str r1, [r0]
++
++ ldr r0, =DDIR(2)
++ ldr r1, =CONFIG_SYS_DDIR_C_VAL
++ str r1, [r0]
++
++ ldr r0, =GPR(2)
++ ldr r1, =CONFIG_SYS_GPR_C_VAL
++ str r1, [r0]
++
++ ldr r0, =PUEN(2)
++ ldr r1, =CONFIG_SYS_PUEN_C_VAL
++ str r1, [r0]
++
++ ldr r0, =GIUS(2)
++ ldr r1, =CONFIG_SYS_GIUS_C_VAL
++ str r1, [r0]
++
++ ldr r0, =DR(3)
++ ldr r1, =CONFIG_SYS_DR_D_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR1(3)
++ ldr r1, =CONFIG_SYS_OCR1_D_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR2(3)
++ ldr r1, =CONFIG_SYS_OCR2_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA1(3)
++ ldr r1, =CONFIG_SYS_ICFA1_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA2(3)
++ ldr r1, =CONFIG_SYS_ICFA2_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB1(3)
++ ldr r1, =CONFIG_SYS_ICFB1_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB2(3)
++ ldr r1, =CONFIG_SYS_ICFB2_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR1(3)
++ ldr r1, =CONFIG_SYS_ICR1_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR2(3)
++ ldr r1, =CONFIG_SYS_ICR2_D_VAL
++ str r1, [r0]
++
++ ldr r0, =IMR(3)
++ ldr r1, =CONFIG_SYS_IMR_D_VAL
++ str r1, [r0]
++
++ ldr r0, =DDIR(3)
++ ldr r1, =CONFIG_SYS_DDIR_D_VAL
++ str r1, [r0]
++
++ ldr r0, =GPR(3)
++ ldr r1, =CONFIG_SYS_GPR_D_VAL
++ str r1, [r0]
++
++ ldr r0, =PUEN(3)
++ ldr r1, =CONFIG_SYS_PUEN_D_VAL
++ str r1, [r0]
++
++ ldr r0, =GIUS(3)
++ ldr r1, =CONFIG_SYS_GIUS_D_VAL
++ str r1, [r0]
++
++/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
++
++ ldr r0, =FMCR
++ ldr r1, =CONFIG_SYS_FMCR_VAL
++ str r1, [r0]
++
++ ldr r0, =CS0U
++ ldr r1, =CONFIG_SYS_CS0U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS0L
++ ldr r1, =CONFIG_SYS_CS0L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS1U
++ ldr r1, =CONFIG_SYS_CS1U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS1L
++ ldr r1, =CONFIG_SYS_CS1L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS2U
++ ldr r1, =CONFIG_SYS_CS2U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS2L
++ ldr r1, =CONFIG_SYS_CS2L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS3U
++ ldr r1, =CONFIG_SYS_CS3U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS3L
++ ldr r1, =CONFIG_SYS_CS3L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS4U
++ ldr r1, =CONFIG_SYS_CS4U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS4L
++ ldr r1, =CONFIG_SYS_CS4L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS5U
++ ldr r1, =CONFIG_SYS_CS5U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS5L
++ ldr r1, =CONFIG_SYS_CS5L_VAL
++ str r1, [r0]
++
++ adr r0, sdramsetup /* r0 <- current position of code */
++ /* test if we run from flash or RAM */
++ ldr r1, =PHYS_SDRAM_1
++ cmp r1, r0 /* don't reloc during debug*/
++ bhi sdramsetup
++ /* test if we run from flash or RAM */
++ ldr r1, =CONFIG_SYS_FLASH_BASE
++ cmp r0, r1 /* don't reloc during debug */
++ bmi copy2ram
++
++/* SDRAM Setup */
++sdramsetup:
++ ldr r0, =SDCTL0
++ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
++ str r1, [r0]
++
++ ldr r1, =PHYS_SDRAM_1 \
++ +CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
++ ldr r2, [r1]
++
++ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
++ str r1, [r0]
++
++ ldr r1, =PHYS_SDRAM_1
++ ldr r2, [r1] /* Issue AutoRefresh Command */
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++
++ ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD
++ str r1, [r0]
++
++ ldr r1, =PHYS_SDRAM_1 \
++ +CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
++ str r2, [r1]
++
++ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
++ str r1, [r0]
++/* make U-Boot runnable form "almost" anywhere */
++/* but SYS_TEXT_BASE should be in RAM */
++copy2ram: /* populate _TEXT_BASE with U-Boot from load addr */
++ ldr r0, _start_adr
++ ldr r1, _copy2ram
++ sub r1, r1, r0
++ adr r0, copy2ram
++ sub r0, r0, r1
++ ldr r1, =CONFIG_SYS_TEXT_BASE
++ cmp r0, r1
++ beq end_of_copy2ram /* skip U-Boot copy */
++ ldr r2, =CONFIG_SYS_MONITOR_LEN
++ add r2, r2, r0 /* r2 <- source end address */
++
++copy_loop:
++ ldmia r0!, {r9-r10} /* copy from source address [r0] */
++ stmia r1!, {r9-r10} /* copy to target address [r1] */
++ cmp r0, r2 /* until source end address [r2] */
++ blo copy_loop
++ ldr pc, =CONFIG_SYS_TEXT_BASE /* reboot from RAM */
++ nop
++ nop
++
++end_of_copy2ram:
++ mov pc,lr
++
++_copy2ram:
++ .word copy2ram
++_start_adr:
++ .word _start
+--- /dev/null
++++ b/configs/apf9328_defconfig
+@@ -0,0 +1,2 @@
++CONFIG_ARM=y
++CONFIG_TARGET_APF9328=y
+--- /dev/null
++++ b/board/armadeus/apf9328/Kconfig
+@@ -0,0 +1,15 @@
++if TARGET_APF9328
++
++config SYS_BOARD
++ default "apf9328"
++
++config SYS_VENDOR
++ default "armadeus"
++
++config SYS_SOC
++ default "imx"
++
++config SYS_CONFIG_NAME
++ default "apf9328"
++
++endif
+--- /dev/null
++++ b/board/armadeus/apf9328/MAINTAINERS
+@@ -0,0 +1,6 @@
++APF9328 BOARD
++M: Eric Jarrige <eri...@ar...>
++S: Maintained
++F: board/armadeus/apf9328/
++F: include/configs/apf9328.h
++F: configs/apf9328_defconfig
+--
+1.7.2.5
+
diff --git a/patches/u-boot/2014.04/106-mx1-pllclk.patch b/patches/u-boot/2015.01/106-mx1-pllclk.patch
similarity index 100%
copy from patches/u-boot/2014.04/106-mx1-pllclk.patch
copy to patches/u-boot/2015.01/106-mx1-pllclk.patch
diff --git a/patches/u-boot/2014.04/107-mx1-pllclk-debug.patch b/patches/u-boot/2015.01/107-mx1-pllclk-debug.patch
similarity index 100%
copy from patches/u-boot/2014.04/107-mx1-pllclk-debug.patch
copy to patches/u-boot/2015.01/107-mx1-pllclk-debug.patch
diff --git a/patches/u-boot/2014.04/108-DM9000.patch b/patches/u-boot/2015.01/108-DM9000.patch
similarity index 100%
copy from patches/u-boot/2014.04/108-DM9000.patch
copy to patches/u-boot/2015.01/108-DM9000.patch
diff --git a/patches/u-boot/2014.07/300-imx27-fix_dcache_boot_issue.patch b/patches/u-boot/2015.01/300-imx27-fix_dcache_boot_issue.patch
similarity index 100%
copy from patches/u-boot/2014.07/300-imx27-fix_dcache_boot_issue.patch
copy to patches/u-boot/2015.01/300-imx27-fix_dcache_boot_issue.patch
diff --git a/patches/u-boot/2015.01/301-apf27-support-boot-from-RAM.patch b/patches/u-boot/2015.01/301-apf27-support-boot-from-RAM.patch
new file mode 100644
index 0000000..a8da017
--- /dev/null
+++ b/patches/u-boot/2015.01/301-apf27-support-boot-from-RAM.patch
@@ -0,0 +1,27 @@
+apf27: Support boot from RAM
+This patch adds capabilites to start U-Boot directly from RAM
+to test a new version of U-Boot before being programmed in FLASH.
+here are two typical use cases:
+- Load and test U-Boot SPL from RAM to launch U-Boot from FLASH.
+ run download_uboot ; go a0000000
+- Load and run U-Boot from RAM
+ run download_uboot ; go a0000800
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+--- a/board/armadeus/apf27/lowlevel_init.S
++++ b/board/armadeus/apf27/lowlevel_init.S
+@@ -162,6 +162,13 @@ lowlevel_init:
+ init_aipi
+ init_clock
+ #ifdef CONFIG_SPL_BUILD
++ /* skip sdram initialization if we run from RAM */
++ cmp pc, #PHYS_SDRAM_1
++ bls 1f
++ cmp pc, #(PHYS_SDRAM_2+PHYS_SDRAM_2_SIZE)
++ bhi 1f
++ mov pc, lr
++1:
+ init_ddr
+ #endif
+
diff --git a/patches/u-boot/2015.01/302-imx-nand-lock-unlock.patch b/patches/u-boot/2015.01/302-imx-nand-lock-unlock.patch
new file mode 100644
index 0000000..101016e
--- /dev/null
+++ b/patches/u-boot/2015.01/302-imx-nand-lock-unlock.patch
@@ -0,0 +1,98 @@
+mxc_nand.c: Support nand lock/unlock
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+--
+ drivers/mtd/nand/mxc_nand.c | 66 +++++++++++++++++++++++++++++++++++++++++++
+ 1 files changed, 66 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
+index d0ded48..2bbc1fd 100644
+--- a/drivers/mtd/nand/mxc_nand.c
++++ b/drivers/mtd/nand/mxc_nand.c
+@@ -47,6 +47,28 @@ static struct mxc_nand_host *host = &mxc_host;
+ #define MAIN_SINGLEBIT_ERROR 0x4
+ #define SPARE_SINGLEBIT_ERROR 0x1
+
++#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
++/******************************************************************************
++ * Support for locking / unlocking feature of imx NFC controller
++ *****************************************************************************/
++
++#define NAND_CMD_LOCK 0x2a
++#define NAND_CMD_LOCK_TIGHT 0x2c
++#define NAND_CMD_UNLOCK1 0x23
++#define NAND_CMD_UNLOCK2 0x24
++#define NAND_CMD_LOCK_STATUS 0x7a
++
++/* NFC_WRPROT Control Register Bit Fields */
++#define NFC_WRPROT_UNLOCKBLK (4<<0) /* unlock block according to given address range */
++#define NFC_WRPROT_LOCKALL (2<<0) /* lock all */
++#define NFC_WRPROT_LOCKTIGHT (1<<0) /* lock-tight locked blocks */
++/* NFC_WRPR_STAT Status Register Bit Fields */
++#define NFC_WRPR_US (1<<2) /* Unlocked status */
++#define NFC_WRPR_LS (1<<1) /* Locked status */
++#define NFC_WRPR_LTS (1<<0) /* Lock-tight Status */
++
++#endif
++
+ /* OOB placement block for use with hardware ecc generation */
+ #if defined(MXC_NFC_V1)
+ #ifndef CONFIG_SYS_NAND_LARGEPAGE
+@@ -1083,6 +1095,53 @@ void mxc_nand_command(struct mtd_info *mtd, unsigned command,
+ }
+
+ break;
++#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK
++ case NAND_CMD_LOCK:
++ /* Blocks to be unlocked */
++ writew(-1, &host->regs->unlockstart_blkaddr);
++ writew(-1, &host->regs->unlockend_blkaddr);
++
++ /* Lock Block Command for given address range */
++ writew(NFC_WRPROT_LOCKALL, &host->regs->wrprot);
++ return;
++ case NAND_CMD_LOCK_TIGHT:
++ /* Blocks to be unlocked */
++ writew(-1, &host->regs->unlockstart_blkaddr);
++ writew(-1, &host->regs->unlockend_blkaddr);
++
++ /* Lock Block Command for given address range */
++ writew(NFC_WRPROT_LOCKTIGHT, &host->regs->wrprot);
++ return;
++ case NAND_CMD_UNLOCK1:
++ writew(page_addr>>6, &host->regs->unlockstart_blkaddr);
++ return;
++ case NAND_CMD_UNLOCK2:
++ writew(page_addr>>6, &host->regs->unlockend_blkaddr);
++
++ /* Lock Block Command for given address range */
++ writew(NFC_WRPROT_UNLOCKBLK, &host->regs->wrprot);
++ return;
++ case NAND_CMD_LOCK_STATUS:
++ host->col_addr = 0;
++ host->spare_only = false;
++
++ MTDDEBUG(MTD_DEBUG_LEVEL3,"get_lock_status %x\n", readw(&host->regs->nf_wrprst));
++
++ if ((readw(&host->regs->nf_wrprst) & NFC_WRPR_US)
++ && !(readw(&host->regs->nf_wrprst) & NFC_WRPR_LTS)
++ && ((readw(&host->regs->unlockend_blkaddr) >= page_addr>>6)
++ && (readw(&host->regs->unlockstart_blkaddr) <= page_addr>>6))) {
++ void __iomem *main_buf = host->regs->main_area[0];
++ writew(NFC_WRPR_US, main_buf);
++ } else if (readw(&host->regs->nf_wrprst) & NFC_WRPR_LTS) {
++ void __iomem *main_buf = host->regs->main_area[0];
++ writew(readw(&host->regs->nf_wrprst), main_buf);
++ } else {
++ void __iomem *main_buf = host->regs->main_area[0];
++ writew(readw(&host->regs->nf_wrprst) & ~NFC_WRPR_US, main_buf);
++ }
++ return;
++#endif
+ }
+
+ /* Write out the command to the device. */
+--
+1.7.2.5
+
diff --git a/patches/u-boot/2014.07/320-spartan.patch b/patches/u-boot/2015.01/303-spartan.patch
similarity index 100%
copy from patches/u-boot/2014.07/320-spartan.patch
copy to patches/u-boot/2015.01/303-spartan.patch
diff --git a/patches/u-boot/2014.04/340-apf27-misc-commands.patch b/patches/u-boot/2015.01/304-apf27-misc-commands.patch
similarity index 100%
copy from patches/u-boot/2014.04/340-apf27-misc-commands.patch
copy to patches/u-boot/2015.01/304-apf27-misc-commands.patch
diff --git a/patches/u-boot/2015.01/400-imx51.patch b/patches/u-boot/2015.01/400-imx51.patch
new file mode 100644
index 0000000..dc6fb93
--- /dev/null
+++ b/patches/u-boot/2015.01/400-imx51.patch
@@ -0,0 +1,522 @@
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+---
+ arch/arm/cpu/armv7/cpu.c
+ arch/arm/cpu/armv7/mx5/lowlevel_init.S
+ arch/arm/include/asm/arch-mx5/imx-regs.h
+ arch/arm/include/asm/arch-mx5/iomux-mx51.h
+ arch/arm/include/asm/arch-mx5/regs_esdctl.h
+
+diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
+index 39a8023..c8c2293 100644
+--- a/arch/arm/cpu/armv7/cpu.c
++++ b/arch/arm/cpu/armv7/cpu.c
+@@ -66,5 +66,9 @@ int cleanup_before_linux(void)
+ */
+ cpu_cache_initialization();
+
++#ifndef CONFIG_L2_OFF
++/* v7_outer_cache_enable();*/
++#endif
++
+ return 0;
+ }
+diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+index a40b84f..1ca9b22 100644
+--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
++++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+@@ -11,6 +11,34 @@
+ #include <generated/asm-offsets.h>
+ #include <linux/linkage.h>
+
++#ifndef CONFIG_SYS_PLL_DP_CTL
++/* use internal oscillator */
++#define CONFIG_SYS_PLL_DP_CTL 0x00001232
++#endif
++
++#ifndef CONFIG_SYS_CLKCTL_CCSR
++/* use internal oscillator */
++#define CONFIG_SYS_CLKCTL_CCSR 0x00000000
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CBCDR
++#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CBCMR
++/* Use lp_apm (24MHz) source for perclk */
++#define CONFIG_SYS_CLKTL_CBCMR 0x000020C2
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CSCDR1
++#define CONFIG_SYS_CLKTL_CSCDR1 0x00C30321
++#endif
++
++#ifndef CONFIG_SYS_CLKTL_CBCMR1
++/* Use PLL 2 for UART's, get 66.5MHz from it */
++#define CONFIG_SYS_CLKTL_CBCMR1 0xA5A2A020
++#endif
++
+ .section ".text.init", "x"
+
+ .macro init_arm_erratum
+@@ -107,7 +135,7 @@
+ #define W_DP_MFN 8
+
+ setup_pll_func:
+- ldr r1, =0x00001232
++ ldr r1, =CONFIG_SYS_PLL_DP_CTL
+ str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+ mov r1, #0x2
+ str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+@@ -124,7 +152,7 @@
+ str r1, [r0, #PLL_DP_MFN]
+ str r1, [r0, #PLL_DP_HFS_MFN]
+
+- ldr r1, =0x00001232
++ ldr r1, =CONFIG_SYS_PLL_DP_CTL
+ str r1, [r0, #PLL_DP_CTL]
+ 1: ldr r1, [r0, #PLL_DP_CTL]
+ ands r1, r1, #0x1
+@@ -136,7 +164,7 @@
+ .macro setup_pll_errata pll, freq
+ ldr r2, =\pll
+ str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
+- ldr r1, =0x00001236
++ ldr r1, =CONFIG_SYS_PLL_DP_CTL | 0x04
+ str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
+ 1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
+ ands r1, r1, #0x1
+@@ -165,6 +193,16 @@
+ #if defined (CONFIG_MX51)
+ ldr r0, =CCM_BASE_ADDR
+
++#ifdef CONFIG_SYS_CLKCTL_CCMR
++ ldr r1, =CONFIG_SYS_CLKCTL_CCMR
++ str r1, [r0, #CLKCTL_CCMR]
++
++ /* make sure clocks are ready */
++1: ldr r1, [r0, #CLKCTL_CSR]
++ cmp r1, #CONFIG_SYS_CLKCTL_CSR
++ bne 1b
++#endif
++
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+@@ -192,7 +230,7 @@
+ bne 1b
+
+ /* Switch ARM to step clock */
+- mov r1, #0x4
++ mov r1, #CONFIG_SYS_CLKCTL_CCSR | 0x04
+ str r1, [r0, #CLKCTL_CCSR]
+
+ #if defined(CONFIG_MX51_PLL_ERRATA)
+@@ -237,13 +275,14 @@
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1 */
++ mov r1, #CONFIG_SYS_CLKCTL_CCSR
+- str r4, [r0, #CLKCTL_CCSR]
++ str r1, [r0, #CLKCTL_CCSR]
+
+ /* setup the rest */
+- /* Use lp_apm (24MHz) source for perclk */
+- ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
++ /* select source for perclk */
++ ldr r1, =CONFIG_SYS_CLKTL_CBCMR | CONFIG_SYS_DDR_CLKSEL
+ str r1, [r0, #CLKCTL_CBCMR]
+- /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
++ /* ddr clock from PLL 1 */
+ ldr r1, =CONFIG_SYS_CLKTL_CBCDR
+ str r1, [r0, #CLKCTL_CBCDR]
+
+@@ -258,9 +297,9 @@
+ str r1, [r0, #CLKCTL_CCGR6]
+
+ /* Use PLL 2 for UART's, get 66.5MHz from it */
+- ldr r1, =0xA5A2A020
++ ldr r1, =CONFIG_SYS_CLKTL_CBCMR1
+ str r1, [r0, #CLKCTL_CSCMR1]
+- ldr r1, =0x00C30321
++ ldr r1, =CONFIG_SYS_CLKTL_CSCDR1
+ str r1, [r0, #CLKCTL_CSCDR1]
+ /* make sure divider effective */
+ 1: ldr r1, [r0, #CLKCTL_CDHIPR]
+diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
+index 46017f4..520bf98 100644
+--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
++++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
+@@ -250,6 +250,7 @@
+ #define M4IF_GENP_WEIM_MM_MASK 0x00000001
+ #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
+
++#ifndef DP_OP_800
+ /* Assuming 24MHz input clock with doubler ON */
+ /* MFI PDF */
+ #define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
+@@ -288,6 +289,7 @@
+ #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
+ #define DP_MFD_216 (4 - 1)
+ #define DP_MFN_216 3
++#endif /* DP_OP_800 */
+
+ #define CHIP_REV_1_0 0x10
+ #define CHIP_REV_1_1 0x11
+diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+--- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h
++++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h
+@@ -60,9 +60,17 @@ enum {
+ MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
++ MX51_PAD_EIM_D24__I2C2_SDA = IOMUX_PAD(0x410, 0x07c, 0x14, 0x9bc, 0, MX51_I2C_PAD_CTRL),
+ MX51_PAD_EIM_D25__UART3_RXD = IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL),
++ MX51_PAD_EIM_D25__UART2_CTS = IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL),
+ MX51_PAD_EIM_D26__UART3_TXD = IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL),
++ MX51_PAD_EIM_D26__UART2_RTS = IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL),
++ MX51_PAD_EIM_D27__I2C2_SCL = IOMUX_PAD(0x41c, 0x088, 0x14, 0x9b8, 0, MX51_I2C_PAD_CTRL),
+ MX51_PAD_EIM_D27__GPIO2_9 = IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_D28__AUD6_TXD = IOMUX_PAD(0x420, 0x08c, 5, 0x8f0, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_D29__AUD6_RXD = IOMUX_PAD(0x424, 0x090, 5, 0x8ec, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_D30__AUD6_TXC = IOMUX_PAD(0x428, 0x094, 5, 0x8fc, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_D31__AUD6_TXFS = IOMUX_PAD(0x42c, 0x098, 5, 0x900, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_A16__GPIO2_10 = IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A17__GPIO2_11 = IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_EIM_A20__GPIO2_14 = IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+@@ -73,16 +81,22 @@ enum {
+ MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, MX51_USBH_PAD_CTRL),
+ MX51_PAD_EIM_EB2__FEC_MDIO = IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, PAD_CTL_PUS_22K_UP | PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_HYS),
+- MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_EB2__AUD5_RXFS = IOMUX_PAD(0x468, 0x0d4, 6, 0x8e0, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_EB3__GPIO2_23 = IOMUX_PAD(0x46c, 0x0d8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_EB3__FEC_RDATA1 = IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_EB3__AUD5_RXC = IOMUX_PAD(0x46c, 0x0d8, 6, 0x8dc, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS0__GPIO2_25 = IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+- MX51_PAD_EIM_CS2__FEC_RDATA2 = IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS2__GPIO2_27 = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+- MX51_PAD_EIM_CS3__FEC_RDATA3 = IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_CS2__FEC_RDATA2 = IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_CS2__AUD5_TXD = IOMUX_PAD(0x47c, 0x0e8, 6, 0x8d8, 1, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
+- MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_EIM_CS3__FEC_RDATA3 = IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_CS3__AUD5_RXD = IOMUX_PAD(0x480, 0x0ec, 6, 0x8d4, 1, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_EIM_CS4__AUD5_TXC = IOMUX_PAD(0x484, 0x0f0, 6, 0x8e4, 1, NO_PAD_CTRL),
+ MX51_PAD_EIM_CS5__FEC_CRS = IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_EIM_CS5__AUD5_TXFS = IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL),
+ MX51_PAD_DRAM_RAS__DRAM_RAS = IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_CAS__DRAM_CAS = IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_SDWE__DRAM_SDWE = IOMUX_PAD(0x4ac, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+@@ -99,18 +113,31 @@ enum {
+ MX51_PAD_DRAM_DQM1__DRAM_DQM1 = IOMUX_PAD(0x4d8, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM2__DRAM_DQM2 = IOMUX_PAD(0x4dc, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_DRAM_DQM3__DRAM_DQM3 = IOMUX_PAD(0x4e0, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_WE_B__NANDF_WE_B = IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_WE_B__PATA_DIOW = IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_RE_B__NANDF_RE_B = IOMUX_PAD(0x4e8, 0x10c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RE_B__PATA_DIOR = IOMUX_PAD(0x4e8, 0x10c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_ALE__NANDF_ALE = IOMUX_PAD(0x4ec, 0x110, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_ALE__PATA_BUFFER_EN = IOMUX_PAD(0x4ec, 0x110, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_CLE__NANDF_CLE = IOMUX_PAD(0x4f0, 0x114, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CLE__PATA_RESET_B = IOMUX_PAD(0x4f0, 0x114, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_WP_B__NANDF_WP_B = IOMUX_PAD(0x4f4, 0x118, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_WP_B__PATA_DMACK = IOMUX_PAD(0x4f4, 0x118, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_RB0__NANDF_RB0 = IOMUX_PAD(0x4f8, 0x11c, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RB0__PATA_DMARQ = IOMUX_PAD(0x4f8, 0x11c, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_RB1__PATA_IORDY = IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_RB1__ECSPI2_RDY = IOMUX_PAD(0x4fc, 0x120, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_RB2__FEC_COL = IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_NANDF_RB2__ECSPI2_SCLK = IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_RB2__GPIO3_10 = IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_RB3__FEC_RX_CLK = IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2),
++ MX51_PAD_NANDF_RB3__ECSPI2_MISO = IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
+ MX51_PAD_NANDF_RB3__GPIO3_11 = IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_EIM_SDBA2__EIM_SDBA2 = IOMUX_PAD(0x508, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_SDODT1__EIM_SDODT1 = IOMUX_PAD(0x50C, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_EIM_SDODT0__EIM_SDODT0 = IOMUX_PAD(0x510, __NA_, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_CS0__NANDF_CS0 = IOMUX_PAD(0x518, 0x130, 0, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS2__FEC_TX_ER = IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS3__FEC_MDC = IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5),
+@@ -123,13 +150,17 @@ enum {
+ MX51_PAD_NANDF_CS6__PATA_DA_2 = IOMUX_PAD(0x530, 0x148, 1, __NA_, 0, NO_PAD_CTRL),
+ MX51_PAD_NANDF_CS7__FEC_TX_EN = IOMUX_PAD(0x534, 0x14c, 1, __NA_, 0, MX51_PAD_CTRL_5),
+ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK = IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4),
+- MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_D15__PATA_DATA15 = IOMUX_PAD(0x53c, 0x154, 1, __NA_, 0, NO_PAD_CTRL),
+- MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_NANDF_D15__ECSPI2_MOSI = IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
++ MX51_PAD_NANDF_D15__GPIO3_25 = IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_D14__PATA_DATA14 = IOMUX_PAD(0x540, 0x158, 1, __NA_, 0, NO_PAD_CTRL),
+- MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0x544, 0x15c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
++ MX51_PAD_NANDF_D14__ECSPI2_SS3 = IOMUX_PAD(0x540, 0x158, 2, 0x934, 0, MX51_ECSPI_PAD_CTRL),
++ MX51_PAD_NANDF_D14__GPIO3_26 = IOMUX_PAD(0x540, 0x158, 3, __NA_, 0, MX51_GPIO_PAD_CTRL),
+ MX51_PAD_NANDF_D13__PATA_DATA13 = IOMUX_PAD(0x544, 0x15c, 1, __NA_, 0, NO_PAD_CTRL),
++ MX51_PAD_NANDF_D13__ECSPI2_SS2 = IOMUX_PAD(0x544, 0x15c, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL),
++ MX51_PAD_NANDF_D13__GPIO3_27 = IOMUX_PAD(0...
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