[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-335-g24bba4b
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.3-335-g24bba4b
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From: Sébastien S. <ss...@us...> - 2014-07-16 16:04:55
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 24bba4b707f9f68b9a085bf76b0181a481faea87 (commit)
from cea7ad94611ad79dbd4407517ec2ff861da03afa (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 24bba4b707f9f68b9a085bf76b0181a481faea87
Author: Sébastien Szymanski <ss...@us...>
Date: Wed Jul 16 17:58:43 2014 +0200
[UBOOT] 2014.07: add preliminary apf6 support.
-----------------------------------------------------------------------
Summary of changes:
buildroot/configs/apf6_defconfig | 10 +
.../device/armadeus/apf6/apf6-u-boot-2014.07.h | 262 ++++++++
patches/u-boot/2014.07/503-add-apf6.patch | 649 ++++++++++++++++++++
3 files changed, 921 insertions(+), 0 deletions(-)
create mode 100644 buildroot/target/device/armadeus/apf6/apf6-u-boot-2014.07.h
create mode 100644 patches/u-boot/2014.07/503-add-apf6.patch
diff --git a/buildroot/configs/apf6_defconfig b/buildroot/configs/apf6_defconfig
index 9298fae..5e82ee9 100644
--- a/buildroot/configs/apf6_defconfig
+++ b/buildroot/configs/apf6_defconfig
@@ -59,3 +59,13 @@ BR2_PACKAGE_UTIL_LINUX_BINARIES=y
BR2_PACKAGE_UTIL_LINUX_FSCK=y
BR2_TARGET_ROOTFS_EXT2=y
BR2_TARGET_ROOTFS_EXT2_4=y
+BR2_TARGET_UBOOT=y
+BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
+BR2_TARGET_UBOOT_CUSTOM_VERSION=y
+BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2014.07"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2014.07"
+BR2_TARGET_UBOOT_USE_CUSTOM_CONFIG=y
+BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2014.07.h"
+BR2_TARGET_UBOOT_FORMAT_IMG=y
+BR2_TARGET_UBOOT_SPL=y
+BR2_TARGET_UBOOT_SPL_NAME="SPL"
diff --git a/buildroot/target/device/armadeus/apf6/apf6-u-boot-2014.07.h b/buildroot/target/device/armadeus/apf6/apf6-u-boot-2014.07.h
new file mode 100644
index 0000000..2691849
--- /dev/null
+++ b/buildroot/target/device/armadeus/apf6/apf6-u-boot-2014.07.h
@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) 2013 Armadeus Systems
+ *
+ * Configuration settings for the apf6.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+#define DEBUG
+*/
+
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* SPL */
+#define CONFIG_SPL_MMC_SUPPORT
+
+#include "imx6_spl.h"
+#include "mx6_common.h"
+
+#define CONFIG_MX6
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define MACH_TYPE_APF6 4412 /* has to be changed !! */
+#define CONFIG_MACH_TYPE MACH_TYPE_APF6
+
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+#include <linux/sizes.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE UART4_BASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
+#define CONFIG_BOOTDELAY 5
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+/* MMC Configuration */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_DOS_PARTITION
+
+/* Ethernet Configuration */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 1
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 260000000
+#define CONFIG_IMX_HDMI
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "uimage=uImage\0" \
+ "console=ttymxc3\0" \
+ "splashpos=m,m\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "fdt_addr=0x18000000\0" \
+ "boot_fdt=try\0" \
+ "ip_dyn=yes\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk0p2 ro\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
+ "update_sd_firmware_filename=u-boot.imx\0" \
+ "update_sd_firmware=" \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "if mmc dev ${mmcdev}; then " \
+ "if ${get_cmd} ${update_sd_firmware_filename}; then " \
+ "setexpr fw_sz ${filesize} / 0x200; " \
+ "setexpr fw_sz ${fw_sz} + 1; " \
+ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+ "fi; " \
+ "fi\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "${optargs} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype} " \
+ "video=${video}\0" \
+ "loadbootenv=load mmc ${mmcdev}:${mmcpart} ${loadaddr} uEnv.txt\0" \
+ "importbootenv=echo Importing environment from mmc (uEnv.txt)...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "loadzimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage\0" \
+ "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /dtbs/${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz ${loadaddr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz ${loadaddr}; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} zImage; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "if test ${boot_fdt} = try; then " \
+ "bootz ${loadaddr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "bootz ${loadaddr}; " \
+ "fi;"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "if mmc rescan; then " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "run importbootenv;" \
+ "fi;" \
+ "echo Checking if uenvcmd is set ...;" \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "echo Running default loadzimage ...;" \
+ "if run loadzimage; then " \
+ "run mmcboot;" \
+ "fi;" \
+ "fi;"
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif /* __CONFIG_H * */
diff --git a/patches/u-boot/2014.07/503-add-apf6.patch b/patches/u-boot/2014.07/503-add-apf6.patch
new file mode 100644
index 0000000..b2349bf
--- /dev/null
+++ b/patches/u-boot/2014.07/503-add-apf6.patch
@@ -0,0 +1,649 @@
+Index: uboot-2014.07/boards.cfg
+===================================================================
+--- uboot-2014.07.orig/boards.cfg
++++ uboot-2014.07/boards.cfg
+@@ -318,6 +318,7 @@ Active arm armv7 mx6
+ Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fab...@fr...>
+ Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fab...@fr...>
+ Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fab...@fr...>
++Active arm armv7 mx6 armadeus apf6 apf6 apf6:IMX_CONFIG=board/armadeus/apf6/apf6.cfg,MX6QDL,SPL Armadeus Systems <co...@ar...>
+ Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr...@de...>
+ Active arm armv7 mx6 boundary nitrogen6x mx6qsabrelite nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE Eric Nelson <eri...@bo...>
+ Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Eric Nelson <eri...@bo...>
+Index: uboot-2014.07/board/armadeus/apf6/Makefile
+===================================================================
+--- /dev/null
++++ uboot-2014.07/board/armadeus/apf6/Makefile
+@@ -0,0 +1,8 @@
++#
++# Copyright (C) 2014, ARMadeus Systems <su...@ar...>
++#
++# SPDX-License-Identifier: GPL-2.0+
++#
++
++obj-y := apf6.o
++obj-$(CONFIG_SPL_BUILD) += apf6_spl.o
+Index: uboot-2014.07/board/armadeus/apf6/apf6.c
+===================================================================
+--- /dev/null
++++ uboot-2014.07/board/armadeus/apf6/apf6.c
+@@ -0,0 +1,307 @@
++/*
++ * Copyright (C) 2013 Armadeus systems.
++ *
++ * Author: Nicolas Colombain <nic...@ar...>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <asm/arch/clock.h>
++#include <asm/arch/imx-regs.h>
++#include <asm/arch/iomux.h>
++#include <asm/arch/mx6-pins.h>
++#include <asm/arch/crm_regs.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/gpio.h>
++#include <asm/imx-common/iomux-v3.h>
++#include <asm/imx-common/mxc_i2c.h>
++#include <asm/imx-common/boot_mode.h>
++#include <hwconfig.h>
++#include <linux/ctype.h>
++#include <fdt_support.h>
++#include <fsl_esdhc.h>
++#include <miiphy.h>
++#include <mmc.h>
++#include <mtd_node.h>
++#include <netdev.h>
++#include <fdt_support.h>
++#include <ipu_pixfmt.h>
++#include <mmc.h>
++#include <linux/fb.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
++ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
++ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
++
++#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
++ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
++ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
++
++#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
++ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
++
++#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 2)
++#define ETH_PHY_RESET IMX_GPIO_NR(1, 24)
++
++static iomux_v3_cfg_t const uart4_pads[] = {
++ IOMUX_PADS(PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
++ IOMUX_PADS(PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
++};
++
++static iomux_v3_cfg_t const usdhc2_pads[] = {
++ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
++};
++
++static iomux_v3_cfg_t const usdhc3_pads[] = {
++ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++ IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
++};
++
++static iomux_v3_cfg_t const enet_pads[] = {
++ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
++ /* AR8035 PHY Reset */
++ IOMUX_PADS(PAD_ENET_RX_ER__GPIO1_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
++};
++
++static void setup_iomux_uart(void)
++{
++ SETUP_IOMUX_PADS(uart4_pads);
++}
++
++static void setup_iomux_enet(void)
++{
++ SETUP_IOMUX_PADS(enet_pads);
++
++ /* Reset AR8035 PHY */
++ gpio_direction_output(ETH_PHY_RESET, 0);
++ udelay(500);
++ gpio_set_value(ETH_PHY_RESET, 1);
++}
++
++static struct fsl_esdhc_cfg usdhc_cfg[2] = {
++ {USDHC2_BASE_ADDR},
++ {USDHC3_BASE_ADDR},
++};
++
++int board_mmc_getcd(struct mmc *mmc)
++{
++ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
++ int ret = 0;
++
++ switch (cfg->esdhc_base) {
++ case USDHC2_BASE_ADDR:
++ ret = !gpio_get_value(USDHC2_CD_GPIO);
++ break;
++ case USDHC3_BASE_ADDR:
++ ret = 1;
++ break;
++ }
++
++ return ret;
++}
++
++int board_mmc_init(bd_t *bis)
++{
++ s32 status = 0;
++ u32 index = 0;
++
++ for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
++ switch (index) {
++ case 1:
++ SETUP_IOMUX_PADS(usdhc3_pads);
++ usdhc_cfg[index].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
++ usdhc_cfg[index].max_bus_width = 8;
++ break;
++ case 0:
++ SETUP_IOMUX_PADS(usdhc2_pads);
++ usdhc_cfg[index].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
++ usdhc_cfg[index].max_bus_width = 4;
++ gpio_direction_input(USDHC2_CD_GPIO);
++ break;
++ default:
++ printf("Warning: you configured more USDHC controllers"
++ "(%d) then supported by the board (%d)\n",
++ index + 1, CONFIG_SYS_FSL_USDHC_NUM);
++ return status;
++ }
++
++ status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
++ }
++
++ return status;
++}
++
++static int mx6_rgmii_rework(struct phy_device *phydev)
++{
++ unsigned short val;
++
++ /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
++ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
++ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
++ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
++
++ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
++ val &= 0xffe3;
++ val |= 0x18;
++ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
++
++ /* introduce tx clock delay */
++ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
++ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
++ val |= 0x0100;
++ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
++
++ return 0;
++}
++
++int board_phy_config(struct phy_device *phydev)
++{
++ mx6_rgmii_rework(phydev);
++
++ if (phydev->drv->config)
++ phydev->drv->config(phydev);
++
++ return 0;
++}
++
++#if defined(CONFIG_VIDEO_IPUV3)
++static struct fb_videomode const hdmi = {
++ .name = "HDMI",
++ .refresh = 60,
++ .xres = 1024,
++ .yres = 768,
++ .pixclock = 15385,
++ .left_margin = 220,
++ .right_margin = 40,
++ .upper_margin = 21,
++ .lower_margin = 7,
++ .hsync_len = 60,
++ .vsync_len = 10,
++ .sync = FB_SYNC_EXT,
++ .vmode = FB_VMODE_NONINTERLACED
++};
++
++int board_video_skip(void)
++{
++ int ret;
++
++ ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24);
++
++ if (ret)
++ printf("HDMI cannot be configured: %d\n", ret);
++
++
++// imx_enable_hdmi_phy();
++
++ return ret;
++}
++
++static void setup_display(void)
++{
++ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
++ int reg;
++
++ enable_ipu_clock();
++ //imx_setup_hdmi();
++
++ reg = readl(&mxc_ccm->chsccdr);
++ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
++ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
++ writel(reg, &mxc_ccm->chsccdr);
++}
++#endif /* CONFIG_VIDEO_IPUV3 */
++
++int board_eth_init(bd_t *bis)
++{
++ int ret;
++
++ setup_iomux_enet();
++
++ ret = cpu_eth_init(bis);
++ if (ret)
++ printf("FEC MXC: %s:failed\n", __func__);
++
++ return 0;
++}
++
++int board_early_init_f(void)
++{
++ setup_iomux_uart();
++#if defined(CONFIG_VIDEO_IPUV3)
++ setup_display();
++#endif
++ return 0;
++}
++
++/*
++ * Do not overwrite the console
++ * Use always serial for U-Boot console
++ */
++int overwrite_console(void)
++{
++ return 1;
++}
++
++int board_late_init(void)
++{
++ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
++ setenv("fdt_file", "imx6q-apf6dev.dtb");
++ else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
++ setenv("fdt_file", "imx6dl-apf6dev.dtb");
++
++ return 0;
++}
++
++int dram_init(void)
++{
++ gd->ram_size = imx_ddr_size();
++
++ return 0;
++}
++
++int board_init(void)
++{
++ /* address of boot parameters */
++ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
++
++ return 0;
++}
++
++int checkboard(void)
++{
++ puts("Board: APF6\n");
++
++ return 0;
++}
+Index: uboot-2014.07/board/armadeus/apf6/apf6.cfg
+===================================================================
+--- /dev/null
++++ uboot-2014.07/board/armadeus/apf6/apf6.cfg
+@@ -0,0 +1,21 @@
++/*
++ * Copyright (C) 2014 ARMadeus Systems <su...@ar...>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ *
++ */
++
++/* image version */
++IMAGE_VERSION 2
++
++/*
++ * Boot Device : one of
++ * spi, sd (the board has no nand neither onenand)
++ */
++BOOT_FROM sd
++
++#define __ASSEMBLY__
++#include <config.h>
++#include "asm/arch/iomux.h"
++#include "asm/arch/crm_regs.h"
++#include "clocks.cfg"
+Index: uboot-2014.07/board/armadeus/apf6/apf6_spl.c
+===================================================================
+--- /dev/null
++++ uboot-2014.07/board/armadeus/apf6/apf6_spl.c
+@@ -0,0 +1,251 @@
++/*
++ * Copyright (C) 2014 ARMadeus systems <su...@ar...>
++ *
++ * SPDX-License-Identifier: GPL-2.0+
++ */
++
++#include <common.h>
++#include <asm/io.h>
++#include <asm/arch/iomux.h>
++#include <asm/arch/mx6-ddr.h>
++#include <asm/arch/mx6-pins.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/imx-common/boot_mode.h>
++#include <asm/imx-common/iomux-v3.h>
++#include <spl.h>
++
++DECLARE_GLOBAL_DATA_PTR;
++
++/* configure MX6Q/DUAL mmdc DDR io registers */
++struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
++ /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
++ .dram_sdclk_0 = 0x00020030,
++ .dram_sdclk_1 = 0x00020030,
++ .dram_cas = 0x00020030,
++ .dram_ras = 0x00020030,
++ .dram_reset = 0x00020030,
++ /* SDCKE[0:1]: 100k pull-up */
++ .dram_sdcke0 = 0x00003000,
++ .dram_sdcke1 = 0x00003000,
++ /* SDBA2: pull-up disabled */
++ .dram_sdba2 = 0x00000000,
++ /* SDODT[0:1]: 100k pull-up, 40 ohm */
++ .dram_sdodt0 = 0x00003030,
++ .dram_sdodt1 = 0x00003030,
++ /* SDQS[0:7]: Differential input, 40 ohm */
++ .dram_sdqs0 = 0x00000030,
++ .dram_sdqs1 = 0x00000030,
++ .dram_sdqs2 = 0x00000030,
++ .dram_sdqs3 = 0x00000030,
++ .dram_sdqs4 = 0x00000030,
++ .dram_sdqs5 = 0x00000030,
++ .dram_sdqs6 = 0x00000030,
++ .dram_sdqs7 = 0x00000030,
++
++ /* DQM[0:7]: Differential input, 40 ohm */
++ .dram_dqm0 = 0x00020030,
++ .dram_dqm1 = 0x00020030,
++ .dram_dqm2 = 0x00020030,
++ .dram_dqm3 = 0x00020030,
++ .dram_dqm4 = 0x00020030,
++ .dram_dqm5 = 0x00020030,
++ .dram_dqm6 = 0x00020030,
++ .dram_dqm7 = 0x00020030,
++};
++
++/* configure MX6Q/DUAL mmdc GRP io registers */
++struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
++ /* DDR3 */
++ .grp_ddr_type = 0x000c0000,
++ .grp_ddrmode_ctl = 0x00020000,
++ /* disable DDR pullups */
++ .grp_ddrpke = 0x00000000,
++ /* ADDR[00:16], SDBA[0:1]: 40 ohm */
++ .grp_addds = 0x00000030,
++ /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
++ .grp_ctlds = 0x00000030,
++ /* DATA[00:63]: Differential input, 40 ohm */
++ .grp_ddrmode = 0x00020000,
++ .grp_b0ds = 0x00000030,
++ .grp_b1ds = 0x00000030,
++ .grp_b2ds = 0x00000030,
++ .grp_b3ds = 0x00000030,
++ .grp_b4ds = 0x00000030,
++ .grp_b5ds = 0x00000030,
++ .grp_b6ds = 0x00000030,
++ .grp_b7ds = 0x00000030,
++};
++
++/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
++struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
++ /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
++ .dram_sdclk_0 = 0x00020030,
++ .dram_sdclk_1 = 0x00020030,
++ .dram_cas = 0x00020030,
++ .dram_ras = 0x00020030,
++ .dram_reset = 0x00020030,
++ /* SDCKE[0:1]: 100k pull-up */
++ .dram_sdcke0 = 0x00003000,
++ .dram_sdcke1 = 0x00003000,
++ /* SDBA2: pull-up disabled */
++ .dram_sdba2 = 0x00000000,
++ /* SDODT[0:1]: 100k pull-up, 40 ohm */
++ .dram_sdodt0 = 0x00003030,
++ .dram_sdodt1 = 0x00003030,
++ /* SDQS[0:7]: Differential input, 40 ohm */
++ .dram_sdqs0 = 0x00000030,
++ .dram_sdqs1 = 0x00000030,
++ .dram_sdqs2 = 0x00000030,
++ .dram_sdqs3 = 0x00000030,
++ .dram_sdqs4 = 0x00000030,
++ .dram_sdqs5 = 0x00000030,
++ .dram_sdqs6 = 0x00000030,
++ .dram_sdqs7 = 0x00000030,
++
++ /* DQM[0:7]: Differential input, 40 ohm */
++ .dram_dqm0 = 0x00020030,
++ .dram_dqm1 = 0x00020030,
++ .dram_dqm2 = 0x00020030,
++ .dram_dqm3 = 0x00020030,
++ .dram_dqm4 = 0x00020030,
++ .dram_dqm5 = 0x00020030,
++ .dram_dqm6 = 0x00020030,
++ .dram_dqm7 = 0x00020030,
++};
++
++/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
++struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
++ /* DDR3 */
++ .grp_ddr_type = 0x000c0000,
++ /* SDQS[0:7]: Differential input, 40 ohm */
++ .grp_ddrmode_ctl = 0x00020000,
++ /* disable DDR pullups */
++ .grp_ddrpke = 0x00000000,
++ /* ADDR[00:16], SDBA[0:1]: 40 ohm */
++ .grp_addds = 0x00000030,
++ /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
++ .grp_ctlds = 0x00000030,
++ /* DATA[00:63]: Differential input, 40 ohm */
++ .grp_ddrmode = 0x00020000,
++ .grp_b0ds = 0x00000030,
++ .grp_b1ds = 0x00000030,
++ .grp_b2ds = 0x00000030,
++ .grp_b3ds = 0x00000030,
++ .grp_b4ds = 0x00000030,
++ .grp_b5ds = 0x00000030,
++ .grp_b6ds = 0x00000030,
++ .grp_b7ds = 0x00000030,
++};
++
++/* MT41K128M16JT-125 */
++static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
++ .mem_speed = 1600,
++ .density = 2,
++ .width = 16,
++ .banks = 8,
++ .rowaddr = 14,
++ .coladdr = 10,
++ .pagesz = 2,
++ .trcd = 1375,
++ .trcmin = 4875,
++ .trasmin = 3500,
++};
++
++/* APF6Dev specific calibration */
++static struct mx6_mmdc_calibration apf6dev_mmdc_calib = {
++ /* write leveling calibration determine */
++ .p0_mpwldectrl0 = 0x001C0018,
++ .p0_mpwldectrl1 = 0x001F001C,
++ .p1_mpwldectrl0 = 0x00110022,
++ .p1_mpwldectrl1 = 0x00080018,
++ /* Read DQS Gating calibration */
++ .p0_mpdgctrl0 = 0x42580264,
++ .p0_mpdgctrl1 = 0x02590250,
++ .p1_mpdgctrl0 = 0x425C0260,
++ .p1_mpdgctrl1 = 0x02540240,
++ /* Read Calibration: DQS delay relative to DQ read access */
++ .p0_mprddlctl = 0x3632343A,
++ .p1_mprddlctl = 0x3436303E,
++ /* Write Calibration: DQ/DM delay relative to DQS write access */
++ .p0_mpwrdlctl = 0x38363E3A,
++ .p1_mpwrdlctl = 0x3C303C36,
++};
++
++static void spl_dram_init(int width)
++{
++ struct mx6_ddr3_cfg *mem = &mt41k128m16jt_125;
++ struct mx6_ddr_sysinfo sysinfo = {
++ /* width of data bus:0=16,1=32,2=64 */
++ .dsize = width/32,
++ /* config for full 4GB range so that get_mem_size() works */
++ .cs_density = 32, /* 32Gb per CS */
++ /* single chip select */
++ .ncs = 1,
++ .cs1_mirror = 1,
++ .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
++#ifdef RTT_NOM_120OHM
++ .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
++#else
++ .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
++#endif
++ .walat = 0, /* Write additional latency */
++ .ralat = 5, /* Read additional latency */
++ .mif3_mode = 3, /* Command prediction working mode */
++ .bi_on = 1, /* Bank interleaving enabled */
++ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
++ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
++ };
++
++ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
++ mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
++ &mx6dq_grp_ioregs);
++ else
++ mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
++ &mx6sdl_grp_ioregs);
++ mx6_dram_cfg(&sysinfo, &apf6dev_mmdc_calib, mem);
++}
++
++/*
++ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
++ * - we have a stack and a place to store GD, both in SRAM
++ * - no variable global data is available
++ */
++void board_init_f(ulong dummy)
++{
++ /*
++ * Zero out global data:
++ * - this shoudl be done by crt0.S
++ * - failure to zero it will cause i2c_setup to fail
++ */
++ memset((void *)gd, 0, sizeof(struct global_data));
++
++ /* setup AIPS and disable watchdog */
++ arch_cpu_init();
++
++ /* iomux */
++ board_early_init_f();
++
++ /* setup GP timer */
++ timer_init();
++
++ /* UART clocks enabled and gd valid - init serial console */
++ preloader_console_init();
++
++ /* configure MMDC for SDRAM width/size and per-model calibration */
++ if (is_cpu_type(MXC_CPU_MX6SOLO))
++ spl_dram_init(32);
++ else
++ spl_dram_init(64);
++
++ /* Clear the BSS. */
++ memset(__bss_start, 0, __bss_end - __bss_start);
++
++ get_clocks();
++
++ /* load/boot image from boot device */
++ board_init_r(NULL, 0);
++}
++
++void reset_cpu(ulong addr)
++{
++}
+Index: uboot-2014.07/board/armadeus/apf6/clocks.cfg
+===================================================================
+--- /dev/null
++++ uboot-2014.07/board/armadeus/apf6/clocks.cfg
+@@ -0,0 +1,25 @@
++/* set the default clock gate to save power */
++DATA 4, CCM_CCGR0, 0x00C03F3F
++DATA 4, CCM_CCGR1, 0x0030FC03
++DATA 4, CCM_CCGR2, 0x0FFFC000
++DATA 4, CCM_CCGR3, 0x3FF00000
++DATA 4, CCM_CCGR4, 0x00FFF300
++DATA 4, CCM_CCGR5, 0x0F0000C3
++DATA 4, CCM_CCGR6, 0x000003FF
++
++/* enable AXI cache for VDOA/VPU/IPU */
++DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
++/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
++DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
++DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
++
++/*
++ * Setup CCM_CCOSR register as follows:
++ *
++ * cko1_en = 1 --> CKO1 enabled
++ * cko1_div = 111 --> divide by 8
++ * cko1_sel = 1011 --> ahb_clk_root
++ *
++ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
++ */
++DATA 4, CCM_CCOSR, 0x000000fb
hooks/post-receive
--
armadeus
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