[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-341-gfa65c74
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-341-gfa65c74
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From: jorasse <jo...@us...> - 2013-07-25 12:53:26
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via fa65c74a1f1d80e5e5d461c2b4a4c9ebb5976a16 (commit)
from 98ecd8696cb12a5fb20ef6c3e6109aa2a5970fe4 (commit)
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- Log -----------------------------------------------------------------
commit fa65c74a1f1d80e5e5d461c2b4a4c9ebb5976a16
Author: Eric Jarrige <eri...@ar...>
Date: Thu Jul 25 15:04:00 2013 +0200
[UBOOT] 2013.04: remove spartan6 patch. now natively supported by U-Boot
-----------------------------------------------------------------------
Summary of changes:
patches/u-boot/2013.04/321-add_spartan6.patch | 763 -------------------------
1 files changed, 0 insertions(+), 763 deletions(-)
delete mode 100644 patches/u-boot/2013.04/321-add_spartan6.patch
diff --git a/patches/u-boot/2013.04/321-add_spartan6.patch b/patches/u-boot/2013.04/321-add_spartan6.patch
deleted file mode 100644
index 689db28..0000000
--- a/patches/u-boot/2013.04/321-add_spartan6.patch
+++ /dev/null
@@ -1,763 +0,0 @@
-Add suport for Spartan 6.
-
-Signed-off-by: Eric Jarrige <eri...@ar...>
-Signed-off-by: Philippe Reynes <tr...@ya...>
-Signed-off-by: Nicolas Colombain <nic...@ar...>
----
- README | 2 +-
- drivers/fpga/Makefile | 1 +
- drivers/fpga/spartan6.c | 538 +++++++++++++++++++++++++++++++++++++++++++++++
- drivers/fpga/xilinx.c | 1 +
- include/spartan6.h | 132 ++++++++++++
- include/xilinx.h | 3 +
- 6 files changed, 676 insertions(+), 1 deletions(-)
- create mode 100644 drivers/fpga/spartan6.c
- create mode 100644 include/spartan6.h
-
-diff --git a/README b/README
-index dd250a0..d97bc04 100644
---- a/README
-+++ b/README
-@@ -2134,7 +2134,7 @@ The following options need to be configured:
- CONFIG_FPGA_<family>
-
- Enables support for FPGA family.
-- (SPARTAN2, SPARTAN3, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
-+ (SPARTAN2, SPARTAN3,SPARTAN6, VIRTEX2, CYCLONE2, ACEX1K, ACEX)
-
- CONFIG_FPGA_COUNT
-
-diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
-index b48f623..e3fad66 100644
---- a/drivers/fpga/Makefile
-+++ b/drivers/fpga/Makefile
-@@ -29,6 +29,7 @@ ifdef CONFIG_FPGA
- COBJS-y += fpga.o
- COBJS-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
- COBJS-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
-+COBJS-$(CONFIG_FPGA_SPARTAN6) += spartan6.o
- COBJS-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
- COBJS-$(CONFIG_FPGA_XILINX) += xilinx.o
- COBJS-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
-diff --git a/drivers/fpga/spartan6.c b/drivers/fpga/spartan6.c
-new file mode 100644
-index 0000000..2c25f4b
---- /dev/null
-+++ b/drivers/fpga/spartan6.c
-@@ -0,0 +1,538 @@
-+/*
-+ * (C) Copyright 2010 Fabien Marteau <fab...@ar...>
-+ * Sponsorised by ARMadeus Systems.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+
-+/*
-+ * Configuration support for Xilinx Spartan6 devices. Based
-+ * on spartan6.c (Rich Ireland, rir...@en...).
-+ */
-+
-+#include <common.h> /* core U-Boot definitions */
-+#include <spartan6.h> /* Spartan-II device family */
-+
-+#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_SPARTAN6)
-+
-+/* Define FPGA_DEBUG to get debug printf's */
-+#ifdef FPGA_DEBUG
-+#define PRINTF(fmt,args...) printf (fmt ,##args)
-+#else
-+#define PRINTF(fmt,args...)
-+#endif
-+
-+#undef CONFIG_SYS_FPGA_CHECK_BUSY
-+#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-+
-+/* Note: The assumption is that we cannot possibly run fast enough to
-+ * overrun the device (the Slave Parallel mode can free run at 50MHz).
-+ * If there is a need to operate slower, define CONFIG_FPGA_DELAY in
-+ * the board config file to slow things down.
-+ */
-+#ifndef CONFIG_FPGA_DELAY
-+#define CONFIG_FPGA_DELAY()
-+#endif
-+
-+#ifndef CONFIG_SYS_FPGA_WAIT
-+#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
-+#endif
-+
-+static int Spartan6_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
-+static int Spartan6_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-+/* static int Spartan6_sp_info( Xilinx_desc *desc ); */
-+static int Spartan6_sp_reloc( Xilinx_desc *desc, ulong reloc_offset );
-+
-+static int Spartan6_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
-+static int Spartan6_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-+/* static int Spartan6_ss_info( Xilinx_desc *desc ); */
-+static int Spartan6_ss_reloc( Xilinx_desc *desc, ulong reloc_offset );
-+static int Spartan6_ssm_reloc( Xilinx_desc *desc, ulong reloc_offset );
-+
-+/* ------------------------------------------------------------------------- */
-+/* Spartan-II Generic Implementation */
-+int Spartan6_load (Xilinx_desc * desc, void *buf, size_t bsize)
-+{
-+ int ret_val = FPGA_FAIL;
-+
-+ printf("ERROR: spartan6 simple load function is not implemented\n");
-+
-+ return ret_val;
-+}
-+
-+/* ------------------------------------------------------------------------- */
-+/* Spartan-VI Generic Implementation */
-+int Spartan6_dump (Xilinx_desc * desc, void *buf, size_t bsize)
-+{
-+ int ret_val = FPGA_FAIL;
-+
-+
-+ return ret_val;
-+}
-+
-+int Spartan6_info( Xilinx_desc *desc )
-+{
-+ return FPGA_SUCCESS;
-+}
-+
-+
-+int Spartan6_reloc (Xilinx_desc * desc, ulong reloc_offset)
-+{
-+ int ret_val = FPGA_FAIL; /* assume a failure */
-+
-+ if (desc->family != Xilinx_Spartan6) {
-+ printf ("%s: Unsupported family type (spartan6 line %d), %d\n",
-+ __FUNCTION__, __LINE__, desc->family);
-+ return FPGA_FAIL;
-+ } else
-+ switch (desc->iface) {
-+ case slave_serial:
-+ ret_val = Spartan6_ss_reloc (desc, reloc_offset);
-+ break;
-+
-+ case slave_parallel:
-+ ret_val = Spartan6_sp_reloc (desc, reloc_offset);
-+ break;
-+
-+ case slave_selectmap:
-+ ret_val = Spartan6_ssm_reloc (desc, reloc_offset);
-+ break;
-+
-+ default:
-+ printf ("%s: Unsupported interface type (spartan6 line %d), %d\n",
-+ __FUNCTION__, __LINE__, desc->iface);
-+ }
-+
-+ return ret_val;
-+}
-+
-+/* ------------------------------------------------------------------------- */
-+/* Spartan-VI Slave Parallel Generic Implementation */
-+static int Spartan6_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
-+{
-+ int ret_val = FPGA_FAIL; /* assume the worst */
-+ Xilinx_Spartan6_Slave_Parallel_fns *fn = desc->iface_fns;
-+
-+ PRINTF ("%s: start with interface functions @ 0x%p\n",
-+ __FUNCTION__, fn);
-+
-+ if (fn) {
-+ size_t bytecount = 0;
-+ unsigned char *data = (unsigned char *) buf;
-+ int cookie = desc->cookie; /* make a local copy */
-+ unsigned long ts; /* timestamp */
-+
-+ PRINTF ("%s: Function Table:\n"
-+ "ptr:\t0x%p\n"
-+ "struct: 0x%p\n"
-+ "pre: 0x%p\n"
-+ "pgm:\t0x%p\n"
-+ "init:\t0x%p\n"
-+ "err:\t0x%p\n"
-+ "clk:\t0x%p\n"
-+ "cs:\t0x%p\n"
-+ "wr:\t0x%p\n"
-+ "read data:\t0x%p\n"
-+ "write data:\t0x%p\n"
-+ "busy:\t0x%p\n"
-+ "abort:\t0x%p\n",
-+ "post:\t0x%p\n\n",
-+ __FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
-+ fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
-+ fn->abort, fn->post);
-+
-+ /*
-+ * This code is designed to emulate the "Express Style"
-+ * Continuous Data Loading in Slave Parallel Mode for
-+ * the Spartan-II Family.
-+ */
-+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-+ printf ("Loading FPGA Device %d...\n", cookie);
-+#endif
-+ /*
-+ * Run the pre configuration function if there is one.
-+ */
-+ if (*fn->pre) {
-+ (*fn->pre) (cookie);
-+ }
-+
-+ /* Establish the initial state */
-+ (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
-+
-+ /* Get ready for the burn */
-+ CONFIG_FPGA_DELAY ();
-+ (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
-+
-+ ts = get_timer (0); /* get current time */
-+ /* Now wait for INIT and BUSY to go high */
-+ do {
-+ CONFIG_FPGA_DELAY ();
-+ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
-+ puts ("** Timeout waiting for INIT to clear.\n");
-+ (*fn->abort) (cookie); /* abort the burn */
-+ return FPGA_FAIL;
-+ }
-+ } while ((*fn->init) (cookie) && (*fn->busy) (cookie));
-+
-+ (*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
-+ (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
-+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
-+
-+ /* Load the data */
-+ while ( (*fn->done) (cookie) == FPGA_FAIL){
-+ /* XXX - do we check for an Ctrl-C press in here ??? */
-+ /* XXX - Check the error bit? */
-+
-+ (*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
-+ CONFIG_FPGA_DELAY ();
-+ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
-+ CONFIG_FPGA_DELAY ();
-+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
-+
-+ ts = get_timer (0); /* get current time */
-+#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
-+ while ((*fn->busy) (cookie)) {
-+ /* XXX - we should have a check in here somewhere to
-+ * make sure we aren't busy forever... */
-+
-+ CONFIG_FPGA_DELAY ();
-+ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
-+ CONFIG_FPGA_DELAY ();
-+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
-+
-+ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
-+ puts ("** Timeout waiting for BUSY to clear.\n");
-+ (*fn->abort) (cookie); /* abort the burn */
-+ return FPGA_FAIL;
-+ }
-+ }
-+#endif
-+ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
-+ puts ("** Timeout waiting for BUSY to clear.\n");
-+ (*fn->abort) (cookie); /* abort the burn */
-+ return FPGA_FAIL;
-+ }
-+
-+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-+ if (bytecount % (bsize / 40) == 0)
-+ putc ('.'); /* let them know we are alive */
-+#endif
-+ }
-+
-+ CONFIG_FPGA_DELAY ();
-+ (*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */
-+ (*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */
-+
-+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-+ putc ('\n'); /* terminate the dotted line */
-+#endif
-+
-+ /* now check for done signal */
-+ ts = get_timer (0); /* get current time */
-+ ret_val = FPGA_SUCCESS;
-+ while ((*fn->done) (cookie) == FPGA_FAIL) {
-+ /* XXX - we should have a check in here somewhere to
-+ * make sure we aren't busy forever... */
-+
-+ CONFIG_FPGA_DELAY ();
-+ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
-+ CONFIG_FPGA_DELAY ();
-+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
-+
-+ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
-+ puts ("** Timeout waiting for DONE to clear.\n");
-+ (*fn->abort) (cookie); /* abort the burn */
-+ ret_val = FPGA_FAIL;
-+ break;
-+ }
-+ }
-+
-+ if (ret_val == FPGA_SUCCESS) {
-+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-+ puts ("Done.\n");
-+#endif
-+ }
-+ /*
-+ * Run the post configuration function if there is one.
-+ */
-+ if (*fn->post) {
-+ (*fn->post) (cookie);
-+ }
-+
-+ else {
-+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-+ puts ("Fail.\n");
-+#endif
-+ }
-+
-+ } else {
-+ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
-+ }
-+
-+ return ret_val;
-+}
-+
-+static int Spartan6_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
-+{
-+ int ret_val = FPGA_FAIL; /* assume the worst */
-+ Xilinx_Spartan6_Slave_Parallel_fns *fn = desc->iface_fns;
-+
-+ if (fn) {
-+ unsigned char *data = (unsigned char *) buf;
-+ size_t bytecount = 0;
-+ int cookie = desc->cookie; /* make a local copy */
-+
-+ printf ("Starting Dump of FPGA Device %d...\n", cookie);
-+
-+ (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
-+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
-+
-+ /* dump the data */
-+ while (bytecount < bsize) {
-+ /* XXX - do we check for an Ctrl-C press in here ??? */
-+
-+ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
-+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
-+ (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
-+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-+ if (bytecount % (bsize / 40) == 0)
-+ putc ('.'); /* let them know we are alive */
-+#endif
-+ }
-+
-+ (*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */
-+ (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
-+ (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
-+
-+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-+ putc ('\n'); /* terminate the dotted line */
-+#endif
-+ puts ("Done.\n");
-+
-+ /* XXX - checksum the data? */
-+ } else {
-+ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
-+ }
-+
-+ return ret_val;
-+}
-+
-+
-+static int Spartan6_sp_reloc (Xilinx_desc * desc, ulong reloc_offset)
-+{
-+ int ret_val = FPGA_FAIL; /* assume the worst */
-+ Xilinx_Spartan6_Slave_Parallel_fns *fn_r, *fn =
-+ (Xilinx_Spartan6_Slave_Parallel_fns *) (desc->iface_fns);
-+
-+ if (fn) {
-+ ulong addr;
-+
-+ /* Get the relocated table address */
-+ addr = (ulong) fn + reloc_offset;
-+ fn_r = (Xilinx_Spartan6_Slave_Parallel_fns *) addr;
-+
-+ if (!fn_r->relocated) {
-+
-+ if (memcmp (fn_r, fn,
-+ sizeof (Xilinx_Spartan6_Slave_Parallel_fns))
-+ == 0) {
-+ /* good copy of the table, fix the descriptor pointer */
-+ desc->iface_fns = fn_r;
-+ } else {
-+ PRINTF ("%s: Invalid function table at 0x%p\n",
-+ __FUNCTION__, fn_r);
-+ return FPGA_FAIL;
-+ }
-+
-+ PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
-+ desc);
-+
-+ addr = (ulong) (fn->pre) + reloc_offset;
-+ fn_r->pre = (Xilinx_pre_fn) addr;
-+
-+ addr = (ulong) (fn->pgm) + reloc_offset;
-+ fn_r->pgm = (Xilinx_pgm_fn) addr;
-+
-+ addr = (ulong) (fn->init) + reloc_offset;
-+ fn_r->init = (Xilinx_init_fn) addr;
-+
-+ addr = (ulong) (fn->done) + reloc_offset;
-+ fn_r->done = (Xilinx_done_fn) addr;
-+
-+ addr = (ulong) (fn->clk) + reloc_offset;
-+ fn_r->clk = (Xilinx_clk_fn) addr;
-+
-+ addr = (ulong) (fn->err) + reloc_offset;
-+ fn_r->err = (Xilinx_err_fn) addr;
-+
-+ addr = (ulong) (fn->cs) + reloc_offset;
-+ fn_r->cs = (Xilinx_cs_fn) addr;
-+
-+ addr = (ulong) (fn->wr) + reloc_offset;
-+ fn_r->wr = (Xilinx_wr_fn) addr;
-+
-+ addr = (ulong) (fn->rdata) + reloc_offset;
-+ fn_r->rdata = (Xilinx_rdata_fn) addr;
-+
-+ addr = (ulong) (fn->wdata) + reloc_offset;
-+ fn_r->wdata = (Xilinx_wdata_fn) addr;
-+
-+ addr = (ulong) (fn->busy) + reloc_offset;
-+ fn_r->busy = (Xilinx_busy_fn) addr;
-+
-+ addr = (ulong) (fn->abort) + reloc_offset;
-+ fn_r->abort = (Xilinx_abort_fn) addr;
-+
-+ addr = (ulong) (fn->post) + reloc_offset;
-+ fn_r->post = (Xilinx_post_fn) addr;
-+
-+ fn_r->relocated = TRUE;
-+
-+ } else {
-+ /* this table has already been moved */
-+ /* XXX - should check to see if the descriptor is correct */
-+ desc->iface_fns = fn_r;
-+ }
-+
-+ ret_val = FPGA_SUCCESS;
-+ } else {
-+ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
-+ }
-+
-+ return ret_val;
-+
-+}
-+
-+/* ------------------------------------------------------------------------- */
-+
-+static int Spartan6_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
-+{
-+ int ret_val = FPGA_FAIL; /* assume the worst */
-+
-+ printf ("%s: Slave Serial load is unavailable\n",
-+ __FUNCTION__);
-+
-+ return ret_val;
-+}
-+
-+static int Spartan6_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
-+{
-+ /* Readback is only available through the Slave Parallel and */
-+ /* boundary-scan interfaces. */
-+ printf ("%s: Slave Serial Dumping is unavailable\n",
-+ __FUNCTION__);
-+ return FPGA_FAIL;
-+}
-+
-+static int Spartan6_ss_reloc (Xilinx_desc * desc, ulong reloc_offset)
-+{
-+ int ret_val = FPGA_FAIL; /* assume the worst */
-+
-+ printf ("%s: Slave Serial reloc is unavailable\n",
-+ __FUNCTION__);
-+
-+ return ret_val;
-+
-+}
-+
-+static int Spartan6_ssm_reloc (Xilinx_desc * desc, ulong reloc_offset)
-+{
-+ int ret_val = FPGA_FAIL; /* assume the worst */
-+
-+ Xilinx_Spartan6_Slave_SelectMap_fns *fn_r, *fn =
-+ (Xilinx_Spartan6_Slave_SelectMap_fns *) (desc->iface_fns);
-+
-+ if (fn) {
-+ ulong addr;
-+
-+ /* Get the relocated table address */
-+ addr = (ulong) fn + reloc_offset;
-+ fn_r = (Xilinx_Spartan6_Slave_SelectMap_fns *) addr;
-+
-+ if (!fn_r->relocated) {
-+
-+ if (memcmp (fn_r, fn,
-+ sizeof (Xilinx_Spartan6_Slave_SelectMap_fns))
-+ == 0) {
-+ /* good copy of the table, fix the descriptor pointer */
-+ desc->iface_fns = fn_r;
-+ } else {
-+ PRINTF ("%s: Invalid function table at 0x%p\n",
-+ __FUNCTION__, fn_r);
-+ return FPGA_FAIL;
-+ }
-+
-+ PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__,
-+ desc);
-+
-+ addr = (ulong) (fn->pre) + reloc_offset;
-+ fn_r->pre = (Xilinx_pre_fn) addr;
-+
-+ addr = (ulong) (fn->pgm) + reloc_offset;
-+ fn_r->pgm = (Xilinx_pgm_fn) addr;
-+
-+ addr = (ulong) (fn->init) + reloc_offset;
-+ fn_r->init = (Xilinx_init_fn) addr;
-+
-+ addr = (ulong) (fn->done) + reloc_offset;
-+ fn_r->done = (Xilinx_done_fn) addr;
-+
-+ addr = (ulong) (fn->clk) + reloc_offset;
-+ fn_r->clk = (Xilinx_clk_fn) addr;
-+
-+ addr = (ulong) (fn->err) + reloc_offset;
-+ fn_r->err = (Xilinx_err_fn) addr;
-+
-+ addr = (ulong) (fn->cs) + reloc_offset;
-+ fn_r->cs = (Xilinx_cs_fn) addr;
-+
-+ addr = (ulong) (fn->wr) + reloc_offset;
-+ fn_r->wr = (Xilinx_wr_fn) addr;
-+
-+ addr = (ulong) (fn->rdata) + reloc_offset;
-+ fn_r->rdata = (Xilinx_rdata_fn) addr;
-+
-+ addr = (ulong) (fn->wdata) + reloc_offset;
-+ fn_r->wdata = (Xilinx_wdata_fn) addr;
-+
-+ addr = (ulong) (fn->busy) + reloc_offset;
-+ fn_r->busy = (Xilinx_busy_fn) addr;
-+
-+ addr = (ulong) (fn->abort) + reloc_offset;
-+ fn_r->abort = (Xilinx_abort_fn) addr;
-+
-+ addr = (ulong) (fn->post) + reloc_offset;
-+ fn_r->post = (Xilinx_post_fn) addr;
-+
-+ fn_r->relocated = TRUE;
-+
-+ } else {
-+ /* this table has already been moved */
-+ /* XXX - should check to see if the descriptor is correct */
-+ desc->iface_fns = fn_r;
-+ }
-+
-+ ret_val = FPGA_SUCCESS;
-+ } else {
-+ printf ("%s: NULL Interface function table!\n", __FUNCTION__);
-+ }
-+
-+
-+ return ret_val;
-+
-+}
-+#endif
-diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
-index 4072cb4..1290793 100644
---- a/drivers/fpga/xilinx.c
-+++ b/drivers/fpga/xilinx.c
-@@ -31,6 +31,7 @@
- #include <virtex2.h>
- #include <spartan2.h>
- #include <spartan3.h>
-+#include <spartan6.h>
-
- #if 0
- #define FPGA_DEBUG
-diff --git a/include/spartan6.h b/include/spartan6.h
-new file mode 100644
-index 0000000..3f648a0
---- /dev/null
-+++ b/include/spartan6.h
-@@ -0,0 +1,132 @@
-+/*
-+ * (C) Copyright 2010-2011 Fabien Marteau <fab...@ar...>
-+ * Sponsorised by ARMadeus Systems.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+
-+/*
-+ * Configuration support for Xilinx Spartan6 devices. Based
-+ * on spartan2.h (Rich Ireland, rir...@en...).
-+ */
-+
-+#ifndef _SPARTAN6_H_
-+#define _SPARTAN6_H_
-+
-+#include <xilinx.h>
-+
-+extern int Spartan6_load( Xilinx_desc *desc, void *image, size_t size );
-+extern int Spartan6_dump( Xilinx_desc *desc, void *buf, size_t bsize );
-+extern int Spartan6_info( Xilinx_desc *desc );
-+extern int Spartan6_reloc( Xilinx_desc *desc, ulong reloc_off );
-+
-+/* Slave Parallel Implementation function table */
-+typedef struct {
-+ Xilinx_pre_fn pre;
-+ Xilinx_pgm_fn pgm;
-+ Xilinx_init_fn init;
-+ Xilinx_err_fn err;
-+ Xilinx_done_fn done;
-+ Xilinx_clk_fn clk;
-+ Xilinx_cs_fn cs;
-+ Xilinx_wr_fn wr;
-+ Xilinx_rdata_fn rdata;
-+ Xilinx_wdata_fn wdata;
-+ Xilinx_busy_fn busy;
-+ Xilinx_abort_fn abort;
-+ Xilinx_post_fn post;
-+ int relocated;
-+} Xilinx_Spartan6_Slave_Parallel_fns;
-+
-+/* Slave SelectMap Implementation function table */
-+typedef struct {
-+ Xilinx_pre_fn pre;
-+ Xilinx_pgm_fn pgm;
-+ Xilinx_init_fn init;
-+ Xilinx_err_fn err;
-+ Xilinx_done_fn done;
-+ Xilinx_clk_fn clk;
-+ Xilinx_cs_fn cs;
-+ Xilinx_wr_fn wr;
-+ Xilinx_rdata_fn rdata;
-+ Xilinx_wdata_fn wdata;
-+ Xilinx_busy_fn busy;
-+ Xilinx_abort_fn abort;
-+ Xilinx_post_fn post;
-+ int relocated;
-+} Xilinx_Spartan6_Slave_SelectMap_fns;
-+
-+/* Device Image Sizes
-+ *********************************************************************/
-+/* Spartan-VI */
-+#define XILINX_XC6SLX4_SIZE (2724704l/8)
-+#define XILINX_XC6SLX9_SIZE (2724704l/8)
-+#define XILINX_XC6SLX16_SIZE (3713440l/8)
-+#define XILINX_XC6SLX25_SIZE (6411440l/8)
-+#define XILINX_XC6SLX25T_SIZE (6411440l/8)
-+#define XILINX_XC6SLX45_SIZE (11875104l/8)
-+#define XILINX_XC6SLX45T_SIZE (11875104l/8)
-+#define XILINX_XC6SLX75_SIZE (19624608l/8)
-+#define XILINX_XC6SLX75T_SIZE (19624608l/8)
-+#define XILINX_XC6SLX100_SIZE (26543136l/8)
-+#define XILINX_XC6SLX100T_SIZE (26543136l/8)
-+#define XILINX_XC6SLX150_SIZE (33761568l/8)
-+#define XILINX_XC6SLX150T40_SIZE (33761568l/8)
-+
-+/* Descriptor Macros
-+ *********************************************************************/
-+/* Spartan-VI devices */
-+#define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \
-+{ Xilinx_Spartan6, iface,XILINX_XC6SLX9_SIZE , fn_table, cookie }
-+
-+#define XILINX_XC6SLX9_DESC(iface, fn_table, cookie) \
-+{ Xilinx_Spartan6, iface,XILINX_XC6SLX16_SIZE , fn_table, cookie }
-+
-+#define XILINX_XC6SLX16_DESC(iface, fn_table, cookie) \
-+{ Xilinx_Spartan6, iface,XILINX_XC6SLX25_SIZE , fn_table, cookie }
-+
-+#define XILINX_XC6SLX25_DESC(iface, fn_table, cookie) \
-+{ Xilinx_Spartan6, iface,XILINX_XC6SLX25T_SIZE , fn_table, cookie }
-+
-+#define XILINX_XC6SLX25T_DESC(iface, fn_table, cookie) \
-+{ Xilinx_Spartan6, iface,XILINX_XC6SLX25T_SIZE , fn_table, cookie }
-+
-+#define XILINX_XC6SLX45_DESC(iface, fn_table, cookie) \
-+{ Xilinx_Spartan6, iface,XILINX_XC6SLX45_SIZE , fn_table, cookie }
-+
-+#define XILINX_XC6SLX45T_DESC(iface, fn_table, cookie) \
-+{ Xilinx_Spartan6, iface,XILINX_XC6SLX45T_SIZE , fn_table, cookie }
-+
-+#define XILINX_XC6SLX75_DESC(iface, fn_table, cookie) \
-+{ Xilinx_Spartan6, iface,XILINX_XC6SLX75_SIZE , fn_table, cookie }
-+
-+#define XILINX_XC6SLX75T_DESC(iface, fn_table, cookie) \
-+{ Xilinx_Spartan6, iface,XILINX_XC6SLX75T_SIZE , fn_table, cookie }
-+
-+#define XILINX_XC6SLX100_DESC(iface, fn_table, cookie) \
-+{ Xilinx_Spartan6, iface,XILINX_XC6SLX100_SIZE , fn_table, cookie }
-+
-+#define XILINX_XC6SLX100T_DESC(iface, fn_table, cookie) \
-+{ Xilinx_Spartan6, iface, XILINX_XC6SLX100T_SIZE , fn_table, cookie }
-+
-+#define XILINX_XC6SLX150_DESC(iface, fn_table, cookie) \
-+{ Xilinx_Spartan6, iface, XILINX_XC6SLX150_SIZE , fn_table, cookie }
-+
-+#define XILINX_XC6SLX150T40_DESC(iface, fn_table, cookie) \
-+{ Xilinx_Spartan6, iface,XILINX_XC6SLX150T40_SIZE , fn_table, cookie }
-+
-+#endif /* _SPARTAN6_H_ */
-diff --git a/include/xilinx.h b/include/xilinx.h
-index 5f25b7a..c228559 100644
---- a/include/xilinx.h
-+++ b/include/xilinx.h
-@@ -33,10 +33,12 @@
- #define CONFIG_SYS_VIRTEX_E CONFIG_SYS_FPGA_DEV( 0x2 )
- #define CONFIG_SYS_VIRTEX2 CONFIG_SYS_FPGA_DEV( 0x4 )
- #define CONFIG_SYS_SPARTAN3 CONFIG_SYS_FPGA_DEV( 0x8 )
-+#define CONFIG_SYS_SPARTAN6 CONFIG_SYS_FPGA_DEV( 0xa )
- #define CONFIG_SYS_XILINX_SPARTAN2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN2)
- #define CONFIG_SYS_XILINX_VIRTEX_E (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX_E)
- #define CONFIG_SYS_XILINX_VIRTEX2 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_VIRTEX2)
- #define CONFIG_SYS_XILINX_SPARTAN3 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN3)
-+#define CONFIG_SYS_XILINX_SPARTAN6 (CONFIG_SYS_FPGA_XILINX | CONFIG_SYS_SPARTAN6)
- /* XXX - Add new models here */
-
-
-@@ -68,6 +70,7 @@ typedef enum { /* typedef Xilinx_Family */
- Xilinx_VirtexE, /* Virtex-E Family */
- Xilinx_Virtex2, /* Virtex2 Family */
- Xilinx_Spartan3, /* Spartan-III Family */
-+ Xilinx_Spartan6, /* Spartan-VI Family */
- max_xilinx_type /* insert all new types before this */
- } Xilinx_Family; /* end, typedef Xilinx_Family */
-
---
-1.7.2.5
-
hooks/post-receive
--
armadeus
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