[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-336-g7529281
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-336-g7529281
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From: jorasse <jo...@us...> - 2013-07-24 16:09:39
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This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
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from c32345f876b7951a0c9af928b15656cd60632699 (commit)
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- Log -----------------------------------------------------------------
commit 7529281983f70df10a9974aeb9f7e7f763efe930
Author: Eric Jarrige <eri...@ar...>
Date: Wed Jul 24 18:20:09 2013 +0200
[UBOOT] 2013.04: apf51: Update I2C & SD/MMC configuration - work in progress
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf51/apf51-u-boot-2013.04.h | 16 ++----
patches/u-boot/2013.04/401-apf51.patch | 54 +++++++++++---------
2 files changed, 36 insertions(+), 34 deletions(-)
diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2013.04.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2013.04.h
index 158357f..bd19e5c 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2013.04.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2013.04.h
@@ -103,10 +103,10 @@
#define CONFIG_CMD_DNS
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT /* FAT support */
-/*#define CONFIG_CMD_I2C*/ /* I2C serial bus support */
-/*#define CONFIG_CMD_IIM*/ /* imx iim fuse */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_IIM /* imx iim fuse */
#define CONFIG_CMD_MII /* MII support */
-/*#define CONFIG_CMD_MMC*/
+#define CONFIG_CMD_MMC
#define CONFIG_CMD_MTDPARTS /* MTD partition support */
#define CONFIG_CMD_NAND /* NAND support */
#define CONFIG_CMD_NAND_LOCK_UNLOCK
@@ -418,9 +418,8 @@
*/
#ifdef CONFIG_CMD_I2C
#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_I2C_MXC 1
-#define CONFIG_SYS_I2C_PORT I2C2_BASE_ADDR
-#define CONFIG_SYS_I2C_MX51_PORT2
+#define CONFIG_I2C_MXC
+#define CONFIG_SYS_I2C_BASE I2C2_BASE_ADDR
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0xfe
#endif /* CONFIG_CMD_I2C */
@@ -434,11 +433,8 @@
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_SYS_FSL_ESDHC_NUM 1
-
+#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
#define CONFIG_MMC
-#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#endif
diff --git a/patches/u-boot/2013.04/401-apf51.patch b/patches/u-boot/2013.04/401-apf51.patch
index fe88a12..53c66f8 100644
--- a/patches/u-boot/2013.04/401-apf51.patch
+++ b/patches/u-boot/2013.04/401-apf51.patch
@@ -67,7 +67,7 @@ new file mode 100644
index 0000000..8ff1381
--- /dev/null
+++ b/board/armadeus/apf51/apf51.c
-@@ -0,0 +1,1168 @@
+@@ -0,0 +1,1174 @@
+/*
+ * (C) Copyright 2010-2013 Eric Jarrige, Armadeus Project
+ *
@@ -93,6 +93,7 @@ index 0000000..8ff1381
+#include <common.h>
+#include <command.h>
+#include <asm/armv7.h>
++#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/regs_esdctl.h>
@@ -101,6 +102,7 @@ index 0000000..8ff1381
+#include <asm/errno.h>
+#include <i2c.h>
+#include <jffs2/jffs2.h>
++#include <fsl_esdhc.h>
+#include "fpga.h"
+#include <nand.h>
+
@@ -823,51 +825,57 @@ index 0000000..8ff1381
+#endif
+}
+
-+#ifdef CONFIG_FSL_MMC
-+int esdhc_active = CONFIG_DEFAULT_MMC;
++#ifdef CONFIG_FSL_ESDHC
++
++struct fsl_esdhc_cfg esdhc_cfg[2] = {
++ {MMC_SDHC1_BASE_ADDR},
++ {MMC_SDHC2_BASE_ADDR},
++};
++
+#define SD1_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | \
-+ PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | \
++ PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU | \
+ PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | \
+ PAD_CTL_SRE_FAST)
-+int sdhc_init(void)
++int board_mmc_init(bd_t *bis)
+{
+ s32 status = 0;
++ int esdh_addr = CONFIG_SYS_FSL_ESDHC_ADDR;
+
-+ switch (esdhc_active) {
-+ case 0:
++ switch (esdh_addr) {
++ case MMC_SDHC1_BASE_ADDR:
+/*
+ mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT0 |
+ IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_GPIO1_0, SD1_PAD_CFG);
+*/
+ /* SD1_CMD */
-+ mxc_request_iomux(MX51_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
++ mxc_request_iomux(MX51_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_CMD, SD1_PAD_CFG);
+
+ /* SD1_CLK */
-+ mxc_request_iomux(MX51_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
-+ mxc_iomux_set_pad(MX51_PIN_SD1_CLK, SD1_PAD_CFG);
++ mxc_request_iomux(MX51_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
++ mxc_iomux_set_pad(MX51_PIN_SD1_CLK, PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_NONE | PAD_CTL_47K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+
+ /* SD1_DATA0 */
-+ mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
++ mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, SD1_PAD_CFG);
+
+ /* SD1_DATA1 */
-+ mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
++ mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, SD1_PAD_CFG);
+
+ /* SD1_DATA2 */
-+ mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
++ mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, SD1_PAD_CFG);
+
+ /* SD1_DATA3 */
-+ mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
++ mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
+ mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, SD1_PAD_CFG);
++ printf("*** SD/MMC interface %d intialized\n", esdh_addr);
++ esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
++ status = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
+ break;
-+
-+ status = 1;
-+ break;
-+ case 1:
++ case MMC_SDHC2_BASE_ADDR:
+/*
+ mxc_request_iomux(MX51_PIN_GPIO1_0, IOMUX_CONFIG_ALT0 |
+ IOMUX_CONFIG_SION);
@@ -896,15 +904,13 @@ index 0000000..8ff1381
+ /* SD2_DATA3 */
+ mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, SD1_PAD_CFG);
++ printf("*** SD/MMC interface %x intialized\n", esdh_addr);
++ esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
++ status = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
+ break;
-+
-+ status = 1;
-+ break;
-+ case 2:
-+ case 3:
+ default:
+ printf("*** ERROR: SD/MMC interface %d not supported\n",
-+ esdhc_active);
++ esdh_addr);
+ status = 1;
+ break;
+ }
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