[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-328-g1cf91d4
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-328-g1cf91d4
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From: jorasse <jo...@us...> - 2013-07-23 23:15:21
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 1cf91d44c33cf35f84e088746a1d70b5341deab0 (commit)
from d489f3a63438b1f83a85205ad9ead40faedadafc (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 1cf91d44c33cf35f84e088746a1d70b5341deab0
Author: Eric Jarrige <eri...@ar...>
Date: Wed Jul 24 01:25:45 2013 +0200
[UBOOT] 2013.04: apf51: extend SDRAM pin init - and new clean-up
-----------------------------------------------------------------------
Summary of changes:
patches/u-boot/2013.04/400-imx51.patch | 205 +++----------------
patches/u-boot/2013.04/401-apf51.patch | 24 +--
patches/u-boot/2013.04/420-apf51-nand-spl-NG.patch | 15 +--
3 files changed, 39 insertions(+), 205 deletions(-)
diff --git a/patches/u-boot/2013.04/400-imx51.patch b/patches/u-boot/2013.04/400-imx51.patch
index 8c8057f..d28be43 100644
--- a/patches/u-boot/2013.04/400-imx51.patch
+++ b/patches/u-boot/2013.04/400-imx51.patch
@@ -1,13 +1,11 @@
Signed-off-by: Eric Jarrige <eri...@ar...>
Signed-off-by: Philippe Reynes <tr...@ya...>
---
- arch/arm/cpu/armv7/cpu.c | 4 +
- arch/arm/cpu/armv7/mx5/asm-offsets.c | 135 ++++++++++++++++++++++++++-
- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 85 +++++++++++++++--
- arch/arm/include/asm/arch-mx5/imx-regs.h | 2 +
- arch/arm/include/asm/arch-mx5/regs_esdctl.h | 131 ++++++++++++++++++++++++++
- 5 files changed, 344 insertions(+), 13 deletions(-)
- create mode 100644 arch/arm/include/asm/arch-mx5/regs_esdctl.h
+ arch/arm/cpu/armv7/cpu.c
+ arch/arm/cpu/armv7/mx5/lowlevel_init.S
+ arch/arm/include/asm/arch-mx5/imx-regs.h
+ arch/arm/include/asm/arch-mx5/mx5x_pins.h
+ arch/arm/include/asm/arch-mx5/regs_esdctl.h
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 39a8023..c8c2293 100644
@@ -23,171 +21,6 @@ index 39a8023..c8c2293 100644
+
return 0;
}
-diff --git a/arch/arm/cpu/armv7/mx5/asm-offsets.c b/arch/arm/cpu/armv7/mx5/asm-offsets.c
-index f972498..f7ef30a 100644
---- a/arch/arm/cpu/armv7/mx5/asm-offsets.c
-+++ b/arch/arm/cpu/armv7/mx5/asm-offsets.c
-@@ -17,13 +17,15 @@
-
- #include <common.h>
- #include <asm/arch/imx-regs.h>
--
-+#include <asm/arch/iomux.h>
-+#include <asm/arch/regs_esdctl.h>
- #include <linux/kbuild.h>
-
- int main(void)
- {
-
- /* Round up to make sure size gives nice stack alignment */
-+ COMMENT("ESDCTL");
- DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
- DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
- DEFINE(CLKCTL_CSR, offsetof(struct clkctl, csr));
-@@ -62,7 +64,8 @@ int main(void)
- DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
- #endif
-
-- /* DPLL */
-+ BLANK();
-+ COMMENT("DPLL");
- DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
- DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
- DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
-@@ -72,5 +75,133 @@ int main(void)
- DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
- DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
-
-+#if defined(CONFIG_MX51)
-+ BLANK();
-+ COMMENT("ESDCTL");
-+ DEFINE(ESDCTL_ESDCTL0, offsetof(struct esdctl_regs, esdctl0));
-+ DEFINE(ESDCTL_ESDCFG0, offsetof(struct esdctl_regs, esdcfg0));
-+ DEFINE(ESDCTL_ESDCTL1, offsetof(struct esdctl_regs, esdctl1));
-+ DEFINE(ESDCTL_ESDCFG1, offsetof(struct esdctl_regs, esdcfg1));
-+ DEFINE(ESDCTL_ESDMISC, offsetof(struct esdctl_regs, esdmisc));
-+ DEFINE(ESDCTL_ESDSCR, offsetof(struct esdctl_regs, esdscr));
-+ DEFINE(ESDCTL_ESDCDLY1, offsetof(struct esdctl_regs, esdcdly1));
-+ DEFINE(ESDCTL_ESDCDLY2, offsetof(struct esdctl_regs, esdcdly2));
-+ DEFINE(ESDCTL_ESDCDLY3, offsetof(struct esdctl_regs, esdcdly3));
-+ DEFINE(ESDCTL_ESDCDLY4, offsetof(struct esdctl_regs, esdcdly4));
-+ DEFINE(ESDCTL_ESDCDLY5, offsetof(struct esdctl_regs, esdcdly5));
-+ DEFINE(ESDCTL_ESDGPR, offsetof(struct esdctl_regs, esdgpr));
-+ DEFINE(ESDCTL_ESDPRCT0, offsetof(struct esdctl_regs, esdprct0));
-+ DEFINE(ESDCTL_ESDPRCT1, offsetof(struct esdctl_regs, esdprct1));
-+ BLANK();
-+ COMMENT("IOMUX");
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DDRPKS, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDRPKS));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_PKEDDR, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_PKEDDR));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_PKEADDR, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_PKEADDR));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DDRAPKS, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDRAPKS));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DDRAPUS, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDRAPUS));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DDRPUS, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDRPUS));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_HYSDDR0, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_HYSDDR0));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_HYSDDR1, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_HYSDDR1));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_HYSDDR2, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_HYSDDR2));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_HYSDDR3, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_HYSDDR3));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DDR_SR_B0, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDR_SR_B0));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DDR_SR_B1, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDR_SR_B1));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DDR_SR_B2, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDR_SR_B2));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DDR_SR_B4, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDR_SR_B4));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DRAM_B0, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DRAM_B0));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DRAM_B1, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DRAM_B1));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DRAM_B2, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DRAM_B2));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DRAM_B4, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DRAM_B4));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_INMODE1, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_INMODE1));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A0, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDR_SR_A0));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_EMI_DS5, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_EMI_DS5));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DDR_SR_A1, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDR_SR_A1));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DDR_A0, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDR_A0));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DDR_A1, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDR_A1));
-+ DEFINE(IOMUXC_SW_PAD_CTL_GRP_DISP_PKE0, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DISP_PKE0));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_RAS));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_CAS));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_SDWE));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_SDCKE0));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_SDCKE1));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_SDCLK));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_SDQS0));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_SDQS1));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_SDQS2));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_SDQS3));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_CS0));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_CS1));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_DQM0));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_DQM1));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_DQM2));
-+ DEFINE(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, PAD_I_START
-+ + PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_DQM3));
-+
-+ BLANK();
-+ COMMENT("various IOMUX pad functions");
-+ DEFINE(PAD_CTL_SRE_SLOW, PAD_CTL_SRE_SLOW);
-+ DEFINE(PAD_CTL_SRE_FAST, PAD_CTL_SRE_FAST);
-+ DEFINE(PAD_CTL_DRV_LOW, PAD_CTL_DRV_LOW);
-+ DEFINE(PAD_CTL_DRV_MEDIUM, PAD_CTL_DRV_MEDIUM);
-+ DEFINE(PAD_CTL_DRV_HIGH, PAD_CTL_DRV_HIGH);
-+ DEFINE(PAD_CTL_DRV_MAX, PAD_CTL_DRV_MAX);
-+ DEFINE(PAD_CTL_ODE_OPENDRAIN_NONE, PAD_CTL_ODE_OPENDRAIN_NONE);
-+ DEFINE(PAD_CTL_ODE_OPENDRAIN_ENABLE, PAD_CTL_ODE_OPENDRAIN_ENABLE);
-+ DEFINE(PAD_CTL_100K_PD, PAD_CTL_100K_PD);
-+ DEFINE(PAD_CTL_47K_PU, PAD_CTL_47K_PU);
-+ DEFINE(PAD_CTL_100K_PU, PAD_CTL_100K_PU);
-+ DEFINE(PAD_CTL_22K_PU, PAD_CTL_22K_PU);
-+ DEFINE(PAD_CTL_PUE_KEEPER, PAD_CTL_PUE_KEEPER);
-+ DEFINE(PAD_CTL_PUE_PULL, PAD_CTL_PUE_PULL);
-+ DEFINE(PAD_CTL_PUE_PULL, PAD_CTL_PUE_PULL);
-+ DEFINE(PAD_CTL_PKE_NONE, PAD_CTL_PKE_NONE);
-+ DEFINE(PAD_CTL_PKE_ENABLE, PAD_CTL_PKE_ENABLE);
-+ DEFINE(PAD_CTL_HYS_NONE, PAD_CTL_HYS_NONE);
-+ DEFINE(PAD_CTL_HYS_ENABLE, PAD_CTL_HYS_ENABLE);
-+ DEFINE(PAD_CTL_DDR_INPUT_CMOS, PAD_CTL_DDR_INPUT_CMOS);
-+ DEFINE(PAD_CTL_DDR_INPUT_DDR, PAD_CTL_DDR_INPUT_DDR);
-+ DEFINE(PAD_CTL_DRV_VOT_HIGH, PAD_CTL_DRV_VOT_HIGH);
-+ DEFINE(PAD_CTL_DRV_VOT_LOW, PAD_CTL_DRV_VOT_LOW);
-+#endif
- return 0;
- }
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index a40b84f..1ca9b22 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -468,6 +301,34 @@ index 0000000..1c0bf8e
+ + (cs << 2) + ba)
+
+#endif /* __REGS_ESDCTL_H__ */
+--- uboot-custom/arch/arm/include/asm/arch-mx5/mx5x_pins.h
++++ uboot-custom/arch/arm/include/asm/arch-mx5/mx5x_pins.h
+@@ -380,6 +380,7 @@ enum {
+ /* The following are PADS used for drive strength */
+
+ MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820),
++ MX51_PIN_CTL_GRP_INDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x830),
+ MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838),
+ MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890),
+ MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C),
+@@ -388,6 +389,7 @@ enum {
+ MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C),
+ MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864),
+ MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C),
++ MX51_PIN_CTL_GRP_HVDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x870),
+ MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874),
+ MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878),
+ MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880),
+@@ -420,6 +422,9 @@ enum {
+ MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8),
+ MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC),
+ MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0),
++ MX51_PIN_CTL_PAD_EIM_SDBA2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x508),
++ MX51_PIN_CTL_PAD_EIM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x50C),
++ MX51_PIN_CTL_PAD_EIM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x510),
+ };
+
+ enum {
--
1.7.2.5
diff --git a/patches/u-boot/2013.04/401-apf51.patch b/patches/u-boot/2013.04/401-apf51.patch
index 7fa9920..fe88a12 100644
--- a/patches/u-boot/2013.04/401-apf51.patch
+++ b/patches/u-boot/2013.04/401-apf51.patch
@@ -67,7 +67,7 @@ new file mode 100644
index 0000000..8ff1381
--- /dev/null
+++ b/board/armadeus/apf51/apf51.c
-@@ -0,0 +1,1184 @@
+@@ -0,0 +1,1168 @@
+/*
+ * (C) Copyright 2010-2013 Eric Jarrige, Armadeus Project
+ *
@@ -93,11 +93,7 @@ index 0000000..8ff1381
+#include <common.h>
+#include <command.h>
+#include <asm/armv7.h>
-+#include <asm/io.h>
-+#include <asm/arch/imx-regs.h>
-+#include <generated/asm-offsets.h>
+#include <asm/arch/crm_regs.h>
-+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/regs_esdctl.h>
+#include <asm/arch/sys_proto.h>
@@ -105,7 +101,6 @@ index 0000000..8ff1381
+#include <asm/errno.h>
+#include <i2c.h>
+#include <jffs2/jffs2.h>
-+#include <asm/arch/mxc_nand.h>
+#include "fpga.h"
+#include <nand.h>
+
@@ -643,9 +638,6 @@ index 0000000..8ff1381
+
+ mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT0);
+ mxc_iomux_set_pad(MX51_PIN_NANDF_D7, NAND_PAD100K_CFG);
-+
-+ writel(0, NFC_IPC);
-+ NFC_SET_FW(1);
+}
+
+void setup_spi_io(void)
@@ -1104,28 +1096,24 @@ index 0000000..8ff1381
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_DRAM_DQM3),
+ ACFG_IOMUX_PAD_DRAM_DQM3);
-+/*
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
-+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_EIM_SDBA2),
++ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_PAD_EIM_SDBA2),
+ ACFG_IOMUX_PAD_EIM_SDBA2);
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
-+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_EIM_SDODT1),
++ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_PAD_EIM_SDODT1),
+ ACFG_IOMUX_PAD_EIM_SDODT1);
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
-+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_EIM_SDODT0),
++ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_PAD_EIM_SDODT0),
+ ACFG_IOMUX_PAD_EIM_SDODT0);
-+*/
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDRPKS),
+ ACFG_IOMUX_GRP_DDRPKS);
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DRAM_B4),
+ ACFG_IOMUX_GRP_DRAM_B4);
-+/*
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_INDDR),
+ ACFG_IOMUX_GRP_INDDR);
-+*/
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_PKEDDR),
+ ACFG_IOMUX_GRP_PKEDDR);
@@ -1135,7 +1123,6 @@ index 0000000..8ff1381
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDR_A1),
+ ACFG_IOMUX_GRP_DDR_A1);
-+/*
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDRAPUS),
+ ACFG_IOMUX_GRP_DDRAPUS);
@@ -1154,7 +1141,6 @@ index 0000000..8ff1381
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_HYSDDR3),
+ ACFG_IOMUX_GRP_HYSDDR3);
-+*/
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDR_SR_B0),
+ ACFG_IOMUX_GRP_DDR_SR_B0);
@@ -1176,11 +1162,9 @@ index 0000000..8ff1381
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DDR_SR_B4),
+ ACFG_IOMUX_GRP_DDR_SR_B4);
-+/*
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_INMODE1),
+ ACFG_IOMUX_GRP_INMODE1);
-+*/
+ printf(dcd_item, i++, 4, IOMUXC_BASE_ADDR + PAD_I_START +
+ PIN_TO_IOMUX_PAD(MX51_PIN_CTL_GRP_DRAM_B0),
+ ACFG_IOMUX_GRP_DRAM_B0);
diff --git a/patches/u-boot/2013.04/420-apf51-nand-spl-NG.patch b/patches/u-boot/2013.04/420-apf51-nand-spl-NG.patch
index 81e05dd..805f50d 100644
--- a/patches/u-boot/2013.04/420-apf51-nand-spl-NG.patch
+++ b/patches/u-boot/2013.04/420-apf51-nand-spl-NG.patch
@@ -61,7 +61,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+#endif
--- uboot-custom/board/armadeus/apf51/apf51_spl.c
+++ uboot-custom/board/armadeus/apf51/apf51_spl.c
-@@ -0,0 +1,208 @@
+@@ -0,0 +1,197 @@
+/*
+ * (C) Copyright 2013 ej / Armadeus Project <eri...@ar...>
+ *
@@ -88,10 +88,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+#include <config.h>
+#include <spl.h>
+#include <nand.h>
-+#include <asm/io.h>
-+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
-+#include <asm/arch/mx5x_pins.h>
+#include <asm/arch/regs_esdctl.h>
+
+/* Pointer to as well as the global data structure for SPL */
@@ -118,27 +115,21 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1, ACFG_IOMUX_PAD_DRAM_DQM1);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2, ACFG_IOMUX_PAD_DRAM_DQM2);
+ mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3, ACFG_IOMUX_PAD_DRAM_DQM3);
-+/*
+ mxc_iomux_set_pad(MX51_PIN_CTL_PAD_EIM_SDBA2, ACFG_IOMUX_PAD_EIM_SDBA2);
-+ mxc_iomux_set_pad(MX51_PIN_CTL_PAD_EIM_SDODT0, ACFG_IOMUX_PAD_EIM_SDODT1);
++ mxc_iomux_set_pad(MX51_PIN_CTL_PAD_EIM_SDODT1, ACFG_IOMUX_PAD_EIM_SDODT1);
+ mxc_iomux_set_pad(MX51_PIN_CTL_PAD_EIM_SDODT0, ACFG_IOMUX_PAD_EIM_SDODT0);
-+*/
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, ACFG_IOMUX_GRP_DDRPKS);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, ACFG_IOMUX_GRP_DRAM_B4);
-+/*
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INDDR, ACFG_IOMUX_GRP_INDDR);
-+*/
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, ACFG_IOMUX_GRP_PKEDDR);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, ACFG_IOMUX_GRP_DDR_A0);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, ACFG_IOMUX_GRP_DDR_A1);
-+/*
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, ACFG_IOMUX_GRP_DDRAPUS);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, ACFG_IOMUX_GRP_HYSDDR0);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, ACFG_IOMUX_GRP_HYSDDR1);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, ACFG_IOMUX_GRP_HYSDDR2);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HVDDR, ACFG_IOMUX_GRP_HVDDR);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, ACFG_IOMUX_GRP_HYSDDR3);
-+*/
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, ACFG_IOMUX_GRP_DDR_SR_B0);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, ACFG_IOMUX_GRP_DDRAPKS);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, ACFG_IOMUX_GRP_DDR_SR_B1);
@@ -146,9 +137,7 @@ Signed-off-by: Eric Jarrige <eri...@ar...>
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, ACFG_IOMUX_GRP_DDR_SR_B2);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, ACFG_IOMUX_GRP_PKEADDR);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, ACFG_IOMUX_GRP_DDR_SR_B4);
-+/*
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, ACFG_IOMUX_GRP_INMODE1);
-+*/
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, ACFG_IOMUX_GRP_DRAM_B0);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, ACFG_IOMUX_GRP_DRAM_B1);
+ mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A0, ACFG_IOMUX_GRP_DDR_SR_A0);
hooks/post-receive
--
armadeus
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