[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-270-gdf2707f
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-270-gdf2707f
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From: jorasse <jo...@us...> - 2013-05-27 21:07:35
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via df2707f8b739745108e3415ea5e5ec6ac4e238f9 (commit)
from 6a3936bc132688b3be022a0933b2e03a31da13bf (commit)
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not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit df2707f8b739745108e3415ea5e5ec6ac4e238f9
Author: Eric Jarrige <eri...@ar...>
Date: Mon May 27 23:15:22 2013 +0200
[UBOOT] cleanup 2012.10 patchwork
-----------------------------------------------------------------------
Summary of changes:
.../device/armadeus/apf27/apf27-u-boot-2012.10.h | 460 ------
.../100-SPL-Add-u-boot-nand-build-option.patch | 30 -
patches/u-boot/2012.10/102-mx1-i2c.patch | 46 -
patches/u-boot/2012.10/103-apf9328.patch | 1345 ----------------
patches/u-boot/2012.10/104-apf9328-makefile.patch | 41 -
patches/u-boot/2012.10/106-mx1-pllclk.patch | 63 -
patches/u-boot/2012.10/107-mx1-pllclk-debug.patch | 26 -
patches/u-boot/2012.10/108-DM9000.patch | 48 -
patches/u-boot/2012.10/109-mx1-relocation.patch | 33 -
patches/u-boot/2012.10/111-mx1-timer.patch | 25 -
...stant-to-support-the-armadeus-APF27-board.patch | 181 ---
...-add-support-for-the-armadeus-APF27-board.patch | 1469 ------------------
.../303-apf27-Add-spl-support-for-the-apf27.patch | 679 ---------
...pf27-Add-FPGA-support-for-the-apf27-board.patch | 372 -----
.../u-boot/2012.10/311-imx-nand-lock-unlock.patch | 95 --
patches/u-boot/2012.10/320-spartan.patch | 47 -
patches/u-boot/2012.10/321-add_spartan6.patch | 763 ----------
patches/u-boot/2012.10/330-arm926-relocation.patch | 31 -
.../u-boot/2012.10/340-apf27-misc-commands.patch | 379 -----
.../2012.10/350-nand_large_file_download.patch | 241 ---
...60-arm-support-continuous-mmu-mem-mapping.patch | 52 -
.../u-boot/2012.10/370-imx27-add-i2c-driver.patch | 25 -
patches/u-boot/2012.10/400-imx51.patch | 511 -------
patches/u-boot/2012.10/401-apf51.patch | 1601 --------------------
patches/u-boot/2012.10/403-apf51-wdog.patch | 29 -
patches/u-boot/2012.10/407-imx51-nand.patch | 1398 -----------------
patches/u-boot/2012.10/409-apf51-nand-spl.patch | 407 -----
patches/u-boot/2012.10/410-imx-iim.patch | 547 -------
patches/u-boot/2012.10/425-cortex-relocation.patch | 32 -
.../u-boot/2012.10/501-imx28-update-and-fix.patch | 61 -
patches/u-boot/2012.10/502-add-apf28.patch | 1338 ----------------
31 files changed, 0 insertions(+), 12375 deletions(-)
delete mode 100644 buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.10.h
delete mode 100644 patches/u-boot/2012.10/100-SPL-Add-u-boot-nand-build-option.patch
delete mode 100644 patches/u-boot/2012.10/102-mx1-i2c.patch
delete mode 100644 patches/u-boot/2012.10/103-apf9328.patch
delete mode 100644 patches/u-boot/2012.10/104-apf9328-makefile.patch
delete mode 100644 patches/u-boot/2012.10/106-mx1-pllclk.patch
delete mode 100644 patches/u-boot/2012.10/107-mx1-pllclk-debug.patch
delete mode 100644 patches/u-boot/2012.10/108-DM9000.patch
delete mode 100644 patches/u-boot/2012.10/109-mx1-relocation.patch
delete mode 100644 patches/u-boot/2012.10/111-mx1-timer.patch
delete mode 100644 patches/u-boot/2012.10/301-imx27-Add-missing-constant-to-support-the-armadeus-APF27-board.patch
delete mode 100644 patches/u-boot/2012.10/302-apf27-add-support-for-the-armadeus-APF27-board.patch
delete mode 100644 patches/u-boot/2012.10/303-apf27-Add-spl-support-for-the-apf27.patch
delete mode 100644 patches/u-boot/2012.10/304-apf27-Add-FPGA-support-for-the-apf27-board.patch
delete mode 100644 patches/u-boot/2012.10/311-imx-nand-lock-unlock.patch
delete mode 100644 patches/u-boot/2012.10/320-spartan.patch
delete mode 100644 patches/u-boot/2012.10/321-add_spartan6.patch
delete mode 100644 patches/u-boot/2012.10/330-arm926-relocation.patch
delete mode 100644 patches/u-boot/2012.10/340-apf27-misc-commands.patch
delete mode 100644 patches/u-boot/2012.10/350-nand_large_file_download.patch
delete mode 100644 patches/u-boot/2012.10/360-arm-support-continuous-mmu-mem-mapping.patch
delete mode 100644 patches/u-boot/2012.10/370-imx27-add-i2c-driver.patch
delete mode 100644 patches/u-boot/2012.10/400-imx51.patch
delete mode 100644 patches/u-boot/2012.10/401-apf51.patch
delete mode 100644 patches/u-boot/2012.10/403-apf51-wdog.patch
delete mode 100644 patches/u-boot/2012.10/407-imx51-nand.patch
delete mode 100644 patches/u-boot/2012.10/409-apf51-nand-spl.patch
delete mode 100644 patches/u-boot/2012.10/410-imx-iim.patch
delete mode 100644 patches/u-boot/2012.10/425-cortex-relocation.patch
delete mode 100644 patches/u-boot/2012.10/501-imx28-update-and-fix.patch
delete mode 100644 patches/u-boot/2012.10/502-add-apf28.patch
diff --git a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.10.h b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.10.h
deleted file mode 100644
index 4839d5b..0000000
--- a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.10.h
+++ /dev/null
@@ -1,460 +0,0 @@
-/*
- *
- * Configuration settings for the Armadeus Project motherboard APF27
- *
- * Copyright (C) 2008-2012 ej / Armadeus Project <eri...@ar...>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VERSION "3.3"
-#define CONFIG_IDENT_STRING " apf27 patch 3.9"
-#define CONFIG_BOARD_NAME apf27
-
-/*
- * SoC configurations
- */
-#define CONFIG_ARM926EJS /* this is an ARM926EJS CPU */
-#define CONFIG_MX27 /* in a Freescale i.MX27 Chip */
-#define CONFIG_MACH_TYPE 1698 /* APF27 */
-
-/*
- * Enable the call to miscellaneous platform dependent initialization.
- */
-#define CONFIG_SYS_NO_FLASH /* to be define before <config_cmd_default.h> */
-#define CONFIG_MISC_INIT_R
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/*
- * Board display option
- */
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_CPUINFO
-
-/*
- * SPL
- */
-/* Copy SPL+U-Boot here */
-#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_TEXT_BASE - 0x800)
-/* Size is the partion size */
-#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN
-/* Build image with spl and u-boot */
-#define CONFIG_NAND_U_BOOT
-#define CONFIG_SPL_PAD_TO 0xa1000000
-
-/*
- * SPL
- */
-#define CONFIG_SPL
-#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
-#define CONFIG_SPL_START_S_PATH "board/armadeus/apf27"
-#define CONFIG_SPL_LDSCRIPT "board/armadeus/apf27/u-boot-spl.lds"
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-
-#define CONFIG_HOSTNAME CONFIG_BOARD_NAME
-#define CONFIG_ROOTPATH "/tftpboot/" MK_STR(CONFIG_BOARD_NAME) "-root"
-
-/*
- * U-Boot Commands
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV /* ask for env variable */
-#define CONFIG_CMD_BSP /* Board Specific functions */
-#define CONFIG_CMD_CACHE /* icache, dcache */
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP /* DHCP Support */
-#define CONFIG_CMD_DNS
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_IMX_FUSE /* imx iim fuse */
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII /* MII support */
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_MTDPARTS /* MTD partition support */
-#define CONFIG_CMD_NAND /* NAND support */
-#define CONFIG_CMD_NAND_LOCK_UNLOCK
-#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_CMD_NFS /* NFS support */
-#define CONFIG_CMD_PING /* ping support */
-#define CONFIG_CMD_SETEXPR /* setexpr support */
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-
-/*
- * Memory configurations
- */
-#define CONFIG_NR_DRAM_POPULATED 1
-#define CONFIG_NR_DRAM_BANKS 2
-
-#define ACFG_SDRAM_MBYTE_SYZE 64
-
-#define PHYS_SDRAM_1 0xA0000000
-#define PHYS_SDRAM_2 0xB0000000
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10))
-#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */
-#define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */
-
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
- + PHYS_SDRAM_1_SIZE - 0x0100000)
-
-#define CONFIG_SYS_TEXT_BASE 0xA1000000
-
-/*
- * FLASH organization
- */
-#define ACFG_MONITOR_OFFSET 0x00000000
-#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */
-#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */
-#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */
-#define CONFIG_ENV_OFFSET_REDUND \
- (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */
-#define CONFIG_FIRMWARE_OFFSET 0x00200000
-#define CONFIG_KERNEL_OFFSET 0x00300000
-#define CONFIG_ROOTFS_OFFSET 0x00800000
-
-#define CONFIG_MTDMAP "mxc_nand.0"
-#define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP
-#define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \
- ":1M(u-boot)ro," \
- "512K(env)," \
- "512K(env2)," \
- "512K(firmware)," \
- "512K(dtb)," \
- "5M(kernel)," \
- "-(rootfs)"
-
-/*
- * U-Boot general configurations
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_PROMPT "BIOS> " /* prompt string */
-#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */
-#define CONFIG_SYS_PBSIZE \
- (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
- /* Print buffer size */
-#define CONFIG_SYS_MAXARGS 16 /* max command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
- /* Boot argument buffer size */
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_HUSH_PARSER /* enable the "hush" shell */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* secondary prompt string */
-
-/*
- * Boot Linux
- */
-#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
-#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
-#define CONFIG_INITRD_TAG /* send initrd params */
-
-#define CONFIG_OF_LIBFDT
-
-#define CONFIG_BOOTDELAY 5
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_BOOTFILE MK_STR(CONFIG_BOARD_NAME) "-linux.bin"
-#define CONFIG_BOOTARGS "console=" MK_STR(ACFG_CONSOLE_DEV) "," \
- MK_STR(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
- " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
-
-#define ACFG_CONSOLE_DEV ttySMX0
-#define CONFIG_BOOTCOMMAND "run ubifsboot"
-#define CONFIG_SYS_AUTOLOAD "no"
-/*
- * Default load address for user programs and kernel
- */
-#define CONFIG_LOADADDR 0xA0000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-/*
- * Extra Environments
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "env_version=" CONFIG_ENV_VERSION "\0" \
- "consoledev=" MK_STR(ACFG_CONSOLE_DEV) "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
- "partition=nand0,6\0" \
- "u-boot_addr=" MK_STR(ACFG_MONITOR_OFFSET) "\0" \
- "env_addr=" MK_STR(CONFIG_ENV_OFFSET) "\0" \
- "firmware_addr=" MK_STR(CONFIG_FIRMWARE_OFFSET) "\0" \
- "kernel_addr=" MK_STR(CONFIG_KERNEL_OFFSET) "\0" \
- "rootfs_addr=" MK_STR(CONFIG_ROOTFS_OFFSET) "\0" \
- "board_name=" MK_STR(CONFIG_BOARD_NAME) "\0" \
- "kernel_addr_r=A0000000\0" \
- "addnfsargs=setenv bootargs ${bootargs} " \
- "root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
- "addubifsargs=setenv bootargs ${bootargs} " \
- "ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \
- "addmmcargs=setenv bootargs ${bootargs} " \
- "root=/dev/mmcblk0p1 rootfstype=ext2\0" \
- "addipargs=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \
- "${hostname}:eth0:off \0" \
- "nfsboot=setenv bootargs console=${consoledev},${baudrate} " \
- "${mtdparts} ${extrabootargs}; run addnfsargs addipargs;"\
- "nfs ${kernel_addr_r} " \
- "${serverip}:${rootpath}/boot/${board_name}-linux.bin;" \
- "if test -n ${fdt_addr_r} ; then " \
- "nand read ${fdt_addr_r} dtb; fi;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "ubifsboot=setenv bootargs console=${consoledev},${baudrate} " \
- "${mtdparts} ${extrabootargs};run addubifsargs addipargs;"\
- "if test -n ${fdt_addr_r} ; then " \
- "nand read ${fdt_addr_r} dtb; fi;" \
- "nboot ${kernel_addr_r} kernel;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "mmcboot=setenv bootargs console=${consoledev},${baudrate} " \
- "${mtdparts} ${extrabootargs}; run addmmcargs addipargs;"\
- "if test -n ${fdt_addr_r} ; then " \
- "nand read ${fdt_addr_r} dtb; fi;" \
- "mmc dev 0; ext2load mmc 0 ${kernel_addr_r}" \
- " /boot/${board_name}-linux.bin;" \
- "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "boot_nfs_fallback_flash=if ping ${serverip};" \
- "then echo Boot over NFS; run nfsboot;" \
- "else echo Boot from the board; run ubifsboot;" \
- "fi\0" \
- "firmware_autoload=0\0" \
- "flash_uboot=nand unlock ${u-boot_addr} ;" \
- "nand erase.part u-boot;" \
- "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
- "then nand lock; nand unlock ${env_addr};" \
- "echo Flashing of uboot succeed;" \
- "else echo Flashing of uboot failed;" \
- "fi; \0" \
- "flash_firmware=nand erase.part firmware;" \
- "if nand write.trimffs ${fileaddr} ${firmware_addr} ${filesize};"\
- "then echo Flashing of Firmware succeed;" \
- "else echo Flashing of Firmware failed;" \
- "fi\0" \
- "flash_kernel=nand erase.part kernel;" \
- "if nand write.trimffs ${fileaddr} ${kernel_addr} ${filesize};"\
- "then echo Flashing of kernel succeed;" \
- "else echo Flashing of kernel failed;" \
- "fi\0" \
- "flash_rootfs=nand erase.part rootfs;" \
- "if nand write.trimffs ${fileaddr} ${rootfs_addr} ${filesize};"\
- "then echo Flashing of rootfs succeed;" \
- "else echo Flashing of rootfs failed;" \
- "fi\0" \
- "flash_dtb=nand erase.part dtb;" \
- "if nand write.trimffs ${fileaddr} dtb ${filesize};" \
- "then echo Flashing of rootfs succeed;" \
- "else echo Flashing of rootfs failed;" \
- "fi\0" \
- "flash_reset_env=env default -f -a; saveenv;" \
- "echo Flash environment variables erased!\0" \
- "download_uboot=tftpboot ${loadaddr} ${board_name}-u-boot-nand.bin\0" \
- "download_kernel=tftpboot ${loadaddr} ${board_name}-linux.bin\0" \
- "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ubi\0" \
- "download_dtb=tftpboot ${loadaddr} imx27-${board_name}.dtb\0" \
- "update_uboot=run download_uboot flash_uboot\0" \
- "update_kernel=run download_kernel flash_kernel\0" \
- "update_rootfs=run download_rootfs flash_rootfs\0" \
- "update_dtb=run download_dtb flash_dtb\0" \
- "update_all=run download_kernel flash_kernel download_rootfs " \
- "flash_rootfs download_uboot flash_uboot\0" \
- "unlock_regs=mw 10000008 0; mw 10020008 0\0" \
-
-/*
- * Serial Driver
- */
-#define CONFIG_MXC_UART
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_MXC_UART_BASE UART1_BASE
-
-/*
- * GPIO
- */
-#define CONFIG_MXC_GPIO
-
-/*
- * NOR
- */
-
-/*
- * NAND
- */
-#define CONFIG_NAND_MXC
-
-#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000
-#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_LARGEPAGE
-#define IMX27_NAND_16BITS
-#define NAND_MAX_CHIPS 1
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-#define CONFIG_FLASH_SHOW_PROGRESS 45
-#define CONFIG_SYS_NAND_QUIET 1
-
-#define CONFIG_BOOT_TRACE_REG 0xAFFFFFF8 /* Addr to store traces of SPL boot*/
-
-/*
- * Partitions & Filsystems
- */
-#define CONFIG_MTD_DEVICE
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_DOS_PARTITION
-#define CONFIG_SUPPORT_VFAT
-
-/*
- * UBIFS
- */
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-
-/*
- * Ethernet (on SOC imx FEC)
- */
-#define CONFIG_FEC_MXC
-
-#define CONFIG_NET_MULTI
-#define CONFIG_FEC_MXC_PHYADDR 0x1f
-#define CONFIG_MII 1 /* MII PHY management */
-
-/*
- * FPGA
- */
-#define CONFIG_FPGA CONFIG_SYS_SPARTAN3
-#define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA_XILINX
-#define CONFIG_FPGA_SPARTAN3
-#define CONFIG_SYS_FPGA_WAIT 20000 /* 20 ms */
-#define CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_SYS_FPGA_CHECK_CTRLC
-#define CONFIG_SYS_FPGA_CHECK_ERROR
-
-/*
- * Fuses - IIM
- */
-#ifdef CONFIG_CMD_IMX_FUSE
-#define IIM_MAC_BANK 0
-#define IIM_MAC_ROW 5
-#define IIM0_SCC_KEY 11
-#define IIM1_SUID 1
-#endif
-
-/*
- * I2C
- */
-
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_HARD_I2C
-#define CONFIG_I2C_MXC
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_BASE IMX_I2C1_BASE
-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES { }
-
-#ifdef CONFIG_CMD_EEPROM
-# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */
-# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */
-#endif /* CONFIG_CMD_EEPROM */
-#endif /* CONFIG_CMD_I2C */
-
-/*
- * SPI
- */
-
-/*
- * SD/MMC
- */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MXC_MMC
-#define CONFIG_MXC_MCI_REGS_BASE 0x10014000
-#endif
-
-/*
- * RTC
- */
-#ifdef CONFIG_CMD_DATE
-#define CONFIG_RTC_DS1374
-#define CONFIG_SYS_RTC_BUS_NUM 0
-#endif /* CONFIG_CMD_DATE */
-
-/*
- * Watchdog Config
- */
-
-/*
- * USB
- */
-
-/*
- * Clocks
- */
-#define CONFIG_SYS_HZ 1000 /* Ticks per second */
-
-/*
- * PLL
- *
- * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
- * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
- */
-#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
-#undef CONFIG_MX27_CLK26 /* No external 26MHz external clock */
-
-#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
-/* micron 64MB */
-#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
-#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
-#endif
-
-#if (ACFG_SDRAM_MBYTE_SYZE == 128)
-/* micron 128MB */
-#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
-#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
-#endif
-
-#if (ACFG_SDRAM_MBYTE_SYZE == 256)
-/* micron 256MB */
-#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
-#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/patches/u-boot/2012.10/100-SPL-Add-u-boot-nand-build-option.patch b/patches/u-boot/2012.10/100-SPL-Add-u-boot-nand-build-option.patch
deleted file mode 100644
index 21e74fb..0000000
--- a/patches/u-boot/2012.10/100-SPL-Add-u-boot-nand-build-option.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-SPL: Add u-boot-nand build option
-
-Signed-off-by: Eric Jarrige <eri...@ar...>
-
----
- Makefile | 5 +++++
- 1 files changed, 5 insertions(+), 0 deletions(-)
-
-diff --git a/Makefile b/Makefile
-index 08eecbb..00c9422 100644
---- a/Makefile
-+++ b/Makefile
-@@ -554,8 +554,14 @@ $(obj)u-boot.lds: $(LDSCRIPT)
- nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
- $(MAKE) -C nand_spl/board/$(BOARDDIR) all
-
-+ifeq ($(CONFIG_SPL),y)
-+$(obj)u-boot-nand.bin: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
-+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin && \
-+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
-+else
- $(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin
- cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin
-+endif
-
- $(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend
- $(MAKE) -C spl all
---
-1.7.4.4
-
diff --git a/patches/u-boot/2012.10/102-mx1-i2c.patch b/patches/u-boot/2012.10/102-mx1-i2c.patch
deleted file mode 100644
index ff78658..0000000
--- a/patches/u-boot/2012.10/102-mx1-i2c.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-mx1: add i2c registers
-
-Add i2c registers for Freescale imx1/L/S
-
-Signed-off-by: Eric Jarrige <eri...@ar...>
-Signed-off-by: Philippe Reynes <tr...@ya...>
-Cc: Stefano Babic <sb...@de...>
----
- arch/arm/include/asm/arch-imx/imx-regs.h | 23 +++++++++++++++++++++++
- 1 files changed, 23 insertions(+), 0 deletions(-)
-
-diff --git a/arch/arm/include/asm/arch-imx/imx-regs.h b/arch/arm/include/asm/arch-imx/imx-regs.h
-index 4de0779..1fd3e17 100644
---- a/arch/arm/include/asm/arch-imx/imx-regs.h
-+++ b/arch/arm/include/asm/arch-imx/imx-regs.h
-@@ -634,4 +634,27 @@
- #define TSTAT_CAPT (1<<1) /* Capture event */
- #define TSTAT_COMP (1) /* Compare event */
-
-+/*
-+ * I2C module
-+ */
-+#define IADR __REG(IMX_I2C_BASE + 0x000) /* I2C Address Register */
-+#define IFDR __REG(IMX_I2C_BASE + 0x004) /* I2C Frequency Divider Register*/
-+#define I2CR __REG(IMX_I2C_BASE + 0x008) /* I2C Control Register */
-+#define I2SR __REG(IMX_I2C_BASE + 0x00C) /* I2C Status Register */
-+#define I2DR __REG(IMX_I2C_BASE + 0x010) /* I2C Data I/O Register */
-+/* I2C Control Register Bit Fields */
-+#define I2CR_IEN (1<<7) /* I2C Enable */
-+#define I2CR_IIEN (1<<6) /* I2C Interrupt Enable */
-+#define I2CR_MSTA (1<<5) /* I2C Master/Slave Mode Select */
-+#define I2CR_MTX (1<<4) /* I2C Transmit/Receive Mode Select */
-+#define I2CR_TXAK (1<<3) /* I2C Transmit Acknowledge Enable */
-+#define I2CR_RSTA (1<<2) /* I2C Repeated START */
-+#define I2SR_ICF (1<<7) /* I2C Data Transfer */
-+#define I2SR_IAAS (1<<6) /* I2C Addressed As a Slave */
-+#define I2SR_IBB (1<<5) /* I2C Bus Busy */
-+#define I2SR_IAL (1<<4) /* I2C Arbitration Lost */
-+#define I2SR_SRW (1<<2) /* I2C Slave Read/Write */
-+#define I2SR_IIF (1<<1) /* I2C interrupt */
-+#define I2SR_RXAK (1<<0) /* I2C Received Acknowledge */
-+
- #endif /* _IMX_REGS_H */
---
-1.7.2.5
-
diff --git a/patches/u-boot/2012.10/103-apf9328.patch b/patches/u-boot/2012.10/103-apf9328.patch
deleted file mode 100644
index 36f302a..0000000
--- a/patches/u-boot/2012.10/103-apf9328.patch
+++ /dev/null
@@ -1,1345 +0,0 @@
-apf9328: Add Armadeus Project board APF9328
-
-Add Armadeus Project board APF9328
-
-Signed-off-by: Eric Jarrige <eri...@ar...>
-Signed-off-by: Nicolas Colombain <nic...@ar...>
-Signed-off-by: Philippe Reynes <tr...@ya...>
-Cc: Nicolas Colombain <nic...@ar...>
----
- board/armadeus/apf9328/Makefile | 51 ++++
- board/armadeus/apf9328/apf9328.c | 106 +++++++
- board/armadeus/apf9328/apf9328fpga.c | 100 +++++++
- board/armadeus/apf9328/apf9328fpga.h | 31 ++
- board/armadeus/apf9328/eeprom.c | 88 ++++++
- board/armadeus/apf9328/fpga.c | 121 ++++++++
- board/armadeus/apf9328/fpga.h | 30 ++
- board/armadeus/apf9328/i2c.c | 276 +++++++++++++++++++
- board/armadeus/apf9328/lowlevel_init.S | 469 ++++++++++++++++++++++++++++++++
- 9 files changed, 1272 insertions(+), 0 deletions(-)
- create mode 100644 board/armadeus/apf9328/Makefile
- create mode 100644 board/armadeus/apf9328/apf9328.c
- create mode 100644 board/armadeus/apf9328/apf9328fpga.c
- create mode 100644 board/armadeus/apf9328/apf9328fpga.h
- create mode 100644 board/armadeus/apf9328/eeprom.c
- create mode 100644 board/armadeus/apf9328/fpga.c
- create mode 100644 board/armadeus/apf9328/fpga.h
- create mode 100644 board/armadeus/apf9328/i2c.c
- create mode 100644 board/armadeus/apf9328/lowlevel_init.S
-
-diff --git a/board/armadeus/apf9328/Makefile b/board/armadeus/apf9328/Makefile
-new file mode 100644
-index 0000000..0f097cd
---- /dev/null
-+++ b/board/armadeus/apf9328/Makefile
-@@ -0,0 +1,51 @@
-+#
-+# (C) Copyright 2000-2004
-+# Wolfgang Denk, DENX Software Engineering, wd...@de....
-+#
-+# See file CREDITS for list of people who contributed to this
-+# project.
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+
-+include $(TOPDIR)/config.mk
-+
-+LIB = $(obj)lib$(BOARD).o
-+
-+COBJS := apf9328.o i2c.o apf9328fpga.o fpga.o eeprom.o
-+SOBJS := lowlevel_init.o
-+
-+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-+OBJS := $(addprefix $(obj),$(COBJS))
-+SOBJS := $(addprefix $(obj),$(SOBJS))
-+
-+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
-+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-+
-+clean:
-+ rm -f $(SOBJS) $(OBJS)
-+
-+distclean: clean
-+ rm -f $(LIB) core *.bak .depend
-+
-+#########################################################################
-+
-+# defines $(obj).depend target
-+include $(SRCTREE)/rules.mk
-+
-+sinclude $(obj).depend
-+
-+#########################################################################
-diff --git a/board/armadeus/apf9328/apf9328.c b/board/armadeus/apf9328/apf9328.c
-new file mode 100644
-index 0000000..280f749
---- /dev/null
-+++ b/board/armadeus/apf9328/apf9328.c
-@@ -0,0 +1,93 @@
-+/*
-+ * (C) Copyright 2005-2011
-+ * Nicolas Colombain <nic...@ar...>
-+ * Eric Jarrige <eri...@ar...>
-+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+
-+#include <common.h>
-+#include <asm/arch/imx-regs.h>
-+#include <flash.h>
-+#include <netdev.h>
-+#include "apf9328fpga.h"
-+
-+DECLARE_GLOBAL_DATA_PTR;
-+
-+int board_init(void)
-+{
-+
-+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-+
-+ return 0;
-+}
-+
-+int dram_init(void)
-+{
-+ /* dram_init must store complete ramsize in gd->ram_size */
-+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
-+ PHYS_SDRAM_1_SIZE);
-+ return 0;
-+}
-+
-+void enable_caches(void)
-+{
-+#ifndef CONFIG_SYS_DCACHE_OFF
-+ /* Enable D-cache. I-cache is already enabled in start.S */
-+ dcache_enable();
-+#endif
-+}
-+
-+/*
-+ * Miscellaneous intialization
-+ */
-+int misc_init_r(void)
-+{
-+ char *s;
-+
-+#ifdef CONFIG_FPGA
-+ apf9328_init_fpga();
-+#endif
-+
-+#ifdef CONFIG_DRIVER_DM9000
-+ imx_gpio_mode(GPIO_PORTB | GPIO_DR | GPIO_IN | 14);
-+#endif
-+
-+ /* detect compatibility issue of environment version */
-+ s = getenv("env_version");
-+ if ((NULL == s) || (0 != strcmp(s, CONFIG_ENV_VERSION))) {
-+ char * const vars[] = {"flash_reset_env"};
-+ printf("*** Warning - Environment version change suggests: "
-+ "run flash_reset_env; reset\n");
-+ set_default_vars(1, vars);
-+ }
-+
-+ return 0;
-+}
-+
-+void show_boot_progress(int status)
-+{
-+ return;
-+}
-+
-+#ifdef CONFIG_DRIVER_DM9000
-+int board_eth_init(bd_t *bis)
-+{
-+ return dm9000_initialize(bis);
-+}
-+#endif
-diff --git a/board/armadeus/apf9328/apf9328fpga.c b/board/armadeus/apf9328/apf9328fpga.c
-new file mode 100644
-index 0000000..9782115
---- /dev/null
-+++ b/board/armadeus/apf9328/apf9328fpga.c
-@@ -0,0 +1,100 @@
-+/*
-+ * (C) Copyright 2005-2011
-+ * Nicolas Colombain <nic...@ar...>
-+ * Eric Jarrige <eri...@ar...>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+
-+/*
-+ * Spartan 3 FPGA configuration support for the APF9328 daughter board
-+ */
-+
-+#include <common.h>
-+#include <spartan3.h>
-+#include <command.h>
-+#include <jffs2/jffs2.h>
-+#include <asm/arch/imx-regs.h>
-+#include <asm/io.h>
-+#include "apf9328fpga.h"
-+
-+#ifdef CONFIG_FPGA
-+DECLARE_GLOBAL_DATA_PTR;
-+/* Note that these are pointers to code that is in Flash. They will be
-+ * relocated at runtime.
-+ * Spartan3 code is used to download our Spartan 3 :) code is compatible.
-+ * Just take care about the file size
-+*/
-+Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
-+ fpga_pre_fn,
-+ fpga_pgm_fn,
-+ fpga_clk_fn,
-+ fpga_init_fn,
-+ fpga_done_fn,
-+ fpga_wr_fn,
-+};
-+
-+Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
-+ {Xilinx_Spartan3,
-+ slave_serial,
-+ XILINX_XC3S400_SIZE,
-+ (void *)&fpga_fns,
-+ 0}
-+};
-+
-+/*
-+ * Initialize the fpga. Return 1 on success, 0 on failure.
-+ */
-+int apf9328_init_fpga(void)
-+{
-+ char *autoload = getenv("firmware_autoload");
-+ int i, lout = 1;
-+ u8 pnum;
-+ struct mtd_device *dev;
-+ struct part_info *part;
-+
-+ debug("%s:%d: Initialize FPGA interface (relocation offset= 0x%.8lx)\n",
-+ __func__, __LINE__, gd->reloc_off);
-+
-+ fpga_init();
-+
-+ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
-+ debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
-+ fpga_add(fpga_xilinx, &fpga[i]);
-+ }
-+
-+ if ((autoload) && (0 == strcmp(autoload, "1"))) {
-+ if ((mtdparts_init() == 0) &&
-+ (find_dev_and_part("firmware", &dev, &pnum, &part) == 0)) {
-+ if (ctrlc()) {
-+ printf("Firmware download stopped!\n");
-+ lout = 0;
-+ } else if (FPGA_SUCCESS != fpga_load(0,
-+ (void *)part->offset,
-+ (size_t)part->size)) {
-+ lout = 0;
-+ printf("Firmware not loaded!\n");
-+ }
-+ }
-+ }
-+ return lout;
-+}
-+
-+#endif /* CONFIG_FPGA */
-diff --git a/board/armadeus/apf9328/apf9328fpga.h b/board/armadeus/apf9328/apf9328fpga.h
-new file mode 100644
-index 0000000..2a15443
---- /dev/null
-+++ b/board/armadeus/apf9328/apf9328fpga.h
-@@ -0,0 +1,31 @@
-+/*
-+ * (C) Copyright 2002
-+ * Rich Ireland, Enterasys Networks, rir...@en....
-+ * Keith Outwater, kei...@mv....
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+
-+/*
-+ * Spartan 3 FPGA configuration support for the APF9328 daughter board
-+ */
-+
-+#include "fpga.h"
-+extern int apf9328_init_fpga(void);
-diff --git a/board/armadeus/apf9328/eeprom.c b/board/armadeus/apf9328/eeprom.c
-new file mode 100644
-index 0000000..c8165ea
---- /dev/null
-+++ b/board/armadeus/apf9328/eeprom.c
-@@ -0,0 +1,88 @@
-+/*
-+ * (C) Copyright 2008-2011 Armadeus Project
-+ * (C) Copyright 2007
-+ * Stefano Babic, DENX Software Engineering, sb...@de....
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+#include <common.h>
-+#include <command.h>
-+#include <dm9000.h>
-+
-+static int do_read_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
-+ char * const argv[])
-+{
-+ unsigned int i;
-+ u8 data[2];
-+
-+ for (i = 0; i < 0x40; i++) {
-+ if (!(i % 0x10))
-+ printf("\n%08x:", i);
-+ dm9000_read_srom_word(i, data);
-+ printf(" %02x%02x", data[1], data[0]);
-+ }
-+ printf("\n");
-+ return 0;
-+}
-+
-+static int do_write_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
-+ char * const argv[])
-+{
-+ unsigned long offset, value;
-+
-+ if (argc < 4) {
-+ cmd_usage(cmdtp);
-+ return 1;
-+ }
-+
-+ strict_strtoul(argv[2], 16, &offset);
-+ strict_strtoul(argv[3], 16, &value);
-+ if (offset > 0x40) {
-+ printf("Wrong offset : 0x%lx\n", offset);
-+ cmd_usage(cmdtp);
-+ return 1;
-+ }
-+ dm9000_write_srom_word(offset, value);
-+ return 0;
-+}
-+
-+int do_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-+{
-+ if (argc < 2) {
-+ cmd_usage(cmdtp);
-+ return 1;
-+ }
-+
-+ if (strcmp(argv[1], "read") == 0) {
-+ return do_read_dm9000_eeprom(cmdtp, flag, argc, argv);
-+ } else if (strcmp(argv[1], "write") == 0) {
-+ return do_write_dm9000_eeprom(cmdtp, flag, argc, argv);
-+ } else {
-+ cmd_usage(cmdtp);
-+ return 1;
-+ }
-+}
-+
-+U_BOOT_CMD(dm9000ee, 4, 1, do_dm9000_eeprom,
-+ "Read/Write eeprom connected to Ethernet Controller",
-+ "\ndm9000ee write <word offset> <value>\n"
-+ "\tdm9000ee read\n"
-+ "\tword:\t\t00-02 : MAC Address\n"
-+ "\t\t\t03-07 : DM9000 Configuration\n" "\t\t\t08-63 : User data");
-diff --git a/board/armadeus/apf9328/fpga.c b/board/armadeus/apf9328/fpga.c
-new file mode 100644
-index 0000000..f3d4f03
---- /dev/null
-+++ b/board/armadeus/apf9328/fpga.c
-@@ -0,0 +1,121 @@
-+/*
-+ * (C) Copyright 2002
-+ * Rich Ireland, Enterasys Networks, rir...@en....
-+ * Keith Outwater, kei...@mv....
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+#include <common.h>
-+
-+#ifdef CONFIG_FPGA
-+
-+#include <asm/arch/imx-regs.h>
-+#include <asm/io.h>
-+#include <config.h>
-+
-+#define GPIO_PORT(x) ((x >> 5) & 3)
-+#define GPIO_SET(x) (DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
-+#define GPIO_CLEAR(x) (DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
-+#define GPIO_WRITE(x, y) (y ? GPIO_SET(x) : GPIO_CLEAR(x))
-+#define GPIO_READ(x) ((SSR(GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK))))
-+
-+/*
-+ * Port bit numbers for the serial slave controls
-+ */
-+#define FPGA_INIT CONFIG_SYS_FPGA_INIT
-+#define FPGA_DONE CONFIG_SYS_FPGA_DONE
-+#define FPGA_DIN CONFIG_SYS_FPGA_DATA
-+#define FPGA_PROGRAM CONFIG_SYS_FPGA_PRG
-+#define FPGA_CLOCK CONFIG_SYS_FPGA_CLK
-+
-+/* Note that these are pointers to code that is in Flash. They will be
-+ * relocated at runtime.
-+ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
-+ * Just take care about the file size
-+*/
-+
-+/*
-+ * nitialize GPIO port B before download
-+ */
-+int fpga_pre_fn(int cookie)
-+{
-+ debug("%s:%d: FPGA PRE ", __func__, __LINE__);
-+
-+ /* Initialize GPIO pins */
-+ imx_gpio_mode(FPGA_INIT | GPIO_DR | GPIO_IN);
-+ imx_gpio_mode(FPGA_DONE | GPIO_DR | GPIO_IN);
-+ imx_gpio_mode(FPGA_DIN | GPIO_DR | GPIO_OUT);
-+ imx_gpio_mode(FPGA_PROGRAM | GPIO_DR | GPIO_OUT);
-+ imx_gpio_mode(FPGA_CLOCK | GPIO_DR | GPIO_OUT);
-+ return cookie;
-+}
-+
-+/*
-+ * Set the FPGA's active-low program line to the specified level
-+ */
-+int fpga_pgm_fn(int assert, int flush, int cookie)
-+{
-+ debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
-+ assert ? "high" : "low");
-+ GPIO_WRITE(FPGA_PROGRAM, !assert);
-+ return assert;
-+}
-+
-+/*
-+ * Set the FPGA's active-high clock line to the specified level
-+ */
-+int fpga_clk_fn(int assert_clk, int flush, int cookie)
-+{
-+ debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
-+ assert_clk ? "high" : "low");
-+ GPIO_WRITE(FPGA_CLOCK, assert_clk);
-+ return assert_clk;
-+}
-+
-+/*
-+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
-+ * asserted (low).
-+ */
-+int fpga_init_fn(int cookie)
-+{
-+ debug("%s:%d: INIT check... ", __func__, __LINE__);
-+ return !GPIO_READ(FPGA_INIT);
-+}
-+
-+/*
-+ * Test the state of the active-high FPGA DONE pin
-+ */
-+int fpga_done_fn(int cookie)
-+{
-+ debug("%s:%d: DONE check... ", __func__, __LINE__);
-+ return GPIO_READ(FPGA_DONE);
-+}
-+
-+/*
-+ * Set the FPGA's data line to the specified level
-+ */
-+int fpga_wr_fn(int assert_write, int flush, int cookie)
-+{
-+ debug("%s:%d: DATA write... ", __func__, __LINE__);
-+ GPIO_WRITE(FPGA_DIN, assert_write);
-+ return assert_write;
-+}
-+
-+#endif /* CONFIG_FPGA */
-diff --git a/board/armadeus/apf9328/fpga.h b/board/armadeus/apf9328/fpga.h
-new file mode 100644
-index 0000000..3b226d7
---- /dev/null
-+++ b/board/armadeus/apf9328/fpga.h
-@@ -0,0 +1,30 @@
-+/*
-+ * (C) Copyright 2002
-+ * Rich Ireland, Enterasys Networks, rir...@en....
-+ * Keith Outwater, kei...@mv....
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ */
-+extern int fpga_pre_fn(int cookie);
-+extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-+extern int fpga_init_fn(int cookie);
-+extern int fpga_done_fn(int cookie);
-+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
-diff --git a/board/armadeus/apf9328/i2c.c b/board/armadeus/apf9328/i2c.c
-new file mode 100644
-index 0000000..0ba0a8d
---- /dev/null
-+++ b/board/armadeus/apf9328/i2c.c
-@@ -0,0 +1,276 @@
-+/*
-+ * (C) Copyright 2005-2011 ej Armadeus Project <eri...@ar...>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ *
-+ */
-+
-+#include <common.h>
-+
-+#ifdef CONFIG_HARD_I2C
-+
-+#include <asm/io.h>
-+#include <asm/arch/imx-regs.h>
-+#include <i2c.h>
-+
-+/*-----------------------------------------------------------------------
-+ * Definitions
-+ */
-+
-+#define I2C_ACK 0 /* level to ack a byte */
-+#define I2C_NOACK 1 /* level to noack a byte */
-+
-+/*-----------------------------------------------------------------------
-+ * Local functions
-+ */
-+
-+/*-----------------------------------------------------------------------
-+ * START: High -> Low on SDA while SCL is High
-+ * after check for a bus free
-+ */
-+static void imxi2c_send_start(void)
-+{
-+ while (I2SR & I2SR_IBB)
-+ udelay(1);
-+
-+ I2CR |= I2CR_MSTA;
-+ I2SR &= ~I2SR_IIF;
-+}
-+
-+/*-----------------------------------------------------------------------
-+ * STOP: Low -> High on SDA while SCL is High
-+ * after the end of previous transfer
-+ */
-+static void imxi2c_send_stop(void)
-+{
-+ while (!(I2SR & I2SR_ICF))
-+ udelay(1);
-+
-+ I2CR &= ~I2CR_MSTA;
-+}
-+
-+/*-----------------------------------------------------------------------
-+ * Send 8 bits and look for an acknowledgement.
-+ */
-+static int imxi2c_write_byte(uchar data)
-+{
-+ while (!(I2SR & I2SR_ICF)) /* Wait end of transfer */
-+ udelay(1);
-+
-+ I2CR |= I2CR_MTX;
-+ I2SR &= ~I2SR_IIF;
-+ I2DR = data;
-+
-+ while (!(I2SR & I2SR_IIF)) /* checking IIF before ICF: FIXME */
-+ udelay(1);
-+
-+ I2SR &= ~I2SR_IIF;
-+
-+ while (!(I2SR & I2SR_ICF)) /* Wait end of transfer */
-+ udelay(1);
-+
-+ return I2SR & I2SR_RXAK; /* not a nack is an ack */
-+}
-+
-+/*-----------------------------------------------------------------------
-+ * if ack == I2C_ACK, ACK the byte so can continue reading, else
-+ * send I2C_NOACK to end the read.
-+ */
-+static uchar imxi2c_read_byte(int ack)
-+{
-+ int data;
-+
-+ while (!(I2SR & I2SR_ICF))
-+ udelay(1);
-+
-+ I2CR &= ~I2CR_MTX;
-+
-+ if (ack)
-+ I2CR |= I2CR_TXAK;
-+ else
-+ I2CR &= ~I2CR_TXAK;
-+
-+ data = I2DR;
-+ return data;
-+}
-+
-+/* ------------------------------------------------------------------------
-+ * API Functions
-+ * ------------------------------------------------------------------------
-+ */
-+
-+/*-----------------------------------------------------------------------
-+ * i2c_init compute the i2c divider to reach the requested speed
-+ * see mxl reference manual
-+ */
-+void i2c_init(int speed, int slaveaddr)
-+{
-+ int hclk_dividers[] = {
-+ 30, 32, 36, 42, 48, 52, 60, 72,
-+ 80, 88, 104, 128, 144, 160, 192, 240,
-+ 288, 320, 384, 480, 576, 640, 768, 960,
-+ 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840,
-+ 22, 24, 26, 26, 32, 36, 40, 44,
-+ 48, 56, 64, 72, 80, 96, 112, 128,
-+ 160, 192, 224, 256, 320, 384, 448, 512,
-+ 640, 768, 896, 1024, 1280, 1536, 1792, 2048
-+ };
-+ int refDiv = get_HCLK() / speed;
-+ int i, tmpIC;
-+
-+ imx_gpio_mode(PA15_PF_I2C_SDA);
-+ imx_gpio_mode(PA16_PF_I2C_SCL);
-+
-+ tmpIC = (sizeof(hclk_dividers) / sizeof(int)) - 1;
-+ for (i = tmpIC; i >= 0; i--) {
-+ if ((hclk_dividers[i] >= refDiv)
-+ && (hclk_dividers[i] < hclk_dividers[tmpIC])) {
-+ tmpIC = i;
-+ }
-+ }
-+
-+ IFDR = tmpIC;
-+ IADR = slaveaddr << 1;
-+
-+ if (I2SR & I2SR_IBB)
-+ imxi2c_send_stop();
-+
-+ I2CR |= I2CR_IEN;
-+}
-+
-+/*-----------------------------------------------------------------------
-+ * Probe to see if a chip is present. Also good for checking for the
-+ * completion of EEPROM writes since the chip stops responding until
-+ * the write completes (typically 10mSec).
-+ * probe sends a read command to probe a an address
-+ */
-+int i2c_probe(uchar addr)
-+{
-+ int rc;
-+
-+ imxi2c_send_start();
-+ rc = imxi2c_write_byte((addr << 1) | 0);
-+ imxi2c_send_stop();
-+
-+ return rc ? 1 : 0;
-+}
-+
-+/*-----------------------------------------------------------------------
-+ * Read bytes
-+ */
-+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
-+{
-+ int shift;
-+ debug("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
-+ chip, addr, alen, buffer, len);
-+
-+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
-+ /*
-+ * EEPROM chips that implement "address overflow" are ones
-+ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
-+ * address and the extra bits end up in the "chip address"
-+ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
-+ * four 256 byte chips.
-+ *
-+ * Note that we consider the length of the address field to
-+ * still be one byte because the extra address bits are
-+ * hidden in the chip address.
-+ */
-+ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
-+
-+ debug("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
-+ chip, addr);
-+#endif
-+
-+ /*
-+ * Do the addressing portion of a write cycle to set the
-+ * chip's address pointer. If the address length is zero,
-+ * don't do the normal write cycle to set the address pointer,
-+ * there is no address pointer in this chip.
-+ */
-+ imxi2c_send_start();
-+ if (alen > 0) {
-+ if (imxi2c_write_byte(chip << 1)) { /* write cycle */
-+ imxi2c_send_stop();
-+ debug("i2c_read, no chip responded %02X\n", chip);
-+ return 1;
-+ }
-+ shift = (alen - 1) * 8;
-+ while (alen-- > 0) {
-+ if (imxi2c_write_byte(addr >> shift)) {
-+ debug("i2c_read, address not <ACK>ed\n");
-+ return 1;
-+ }
-+ shift -= 8;
-+ }
-+
-+ /* reportedly some chips need a full stop */
-+ imxi2c_send_stop();
-+ imxi2c_send_start();
-+ }
-+ /*
-+ * Send the chip address again, this time for a read cycle.
-+ * Then read the data. On the last byte, we do a NACK instead
-+ * of an ACK(len == 0) to terminate the read.
-+ */
-+ imxi2c_write_byte((chip << 1) | 1); /* read cycle */
-+ imxi2c_read_byte(len <= 2);
-+ while (len-- > 1)
-+ *buffer++ = imxi2c_read_byte(len == 1);
-+
-+ imxi2c_send_stop();
-+ *buffer++ = imxi2c_read_byte(0);
-+ return 0;
-+}
-+
-+/*-----------------------------------------------------------------------
-+ * Write bytes
-+ */
-+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
-+{
-+ int shift, failures = 0;
-+
-+ debug("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
-+ chip, addr, alen, buffer, len);
-+
-+ imxi2c_send_start();
-+ if (imxi2c_write_byte(chip << 1)) { /* write cycle */
-+ imxi2c_send_stop();
-+ debug("i2c_write, no chip responded %02X\n", chip);
-+ return 1;
-+ }
-+ shift = (alen - 1) * 8;
-+ while (alen-- > 0) {
-+ if (imxi2c_write_byte(addr >> shift)) {
-+ debug("i2c_write, address not <ACK>ed\n");
-+ return 1;
-+ }
-+ shift -= 8;
-+ }
-+
-+ while (len-- > 0) {
-+ if (imxi2c_write_byte(*buffer++))
-+ failures++;
-+ }
-+ imxi2c_send_stop();
-+ return failures;
-+}
-+
-+#endif /* CONFIG_HARD_I2C */
-diff --git a/board/armadeus/apf9328/lowlevel_init.S b/board/armadeus/apf9328/lowlevel_init.S
-new file mode 100644
-index 0000000..f080423
---- /dev/null
-+++ b/board/armadeus/apf9328/lowlevel_init.S
-@@ -0,0 +1,469 @@
-+/*
-+ * (C) Copyright 2005-2011 ej Armadeus Project <eri...@ar...>
-+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version 2
-+ * of the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
-+ * 02111-1307, USA.
-+ *
-+ */
-+
-+#include <config.h>
-+#include <version.h>
-+#include <asm/arch/imx-regs.h>
-+
-+.globl lowlevel_init
-+lowlevel_init:
-+/* Change PERCLK1DIV to 14 ie 14+1 */
-+ ldr r0, =PCDR
-+ ldr r1, =CONFIG_SYS_PCDR_VAL
-+ str r1, [r0]
-+
-+/* set MCU PLL Control Register 0 */
-+
-+ ldr r0, =MPCTL0
-+ ldr r1, =CONFIG_SYS_MPCTL0_VAL
-+ str r1, [r0]
-+
-+/* set MCU PLL Control Register 1 */
-+
-+ ldr r0, =MPCTL1
-+ ldr r1, =CONFIG_SYS_MPCTL1_VAL
-+ str r1, [r0]
-+
-+/* set mpll restart bit */
-+ ldr r0, =CSCR
-+ ldr r1, [r0]
-+ orr r1,r1,#(1<<21)
-+ str r1, [r0]
-+
-+ mov r2,#0x10
-+1:
-+ mov r3,#0x2000
-+2:
-+ subs r3,r3,#1
-+ bne 2b
-+
-+ subs r2,r2,#1
-+ bne 1b
-+
-+/* set System PLL Control Register 0 */
-+
-+ ldr r0, =SPCTL0
-+ ldr r1, =CONFIG_SYS_SPCTL0_VAL
-+ str r1, [r0]
-+
-+/* set System PLL Control Register 1 */
-+
-+ ldr r0, =SPCTL1
-+ ldr r1, =CONFIG_SYS_SPCTL1_VAL
-+ str r1, [r0]
-+
-+/* set spll restart bit */
-+ ldr r0, =CSCR
-+ ldr r1, [r0]
-+ orr r1,r1,#(1<<22)
-+ str r1, [r0]
-+
-+ mov r2,#0x10
-+1:
-+ mov r3,#0x2000
-+2:
-+ subs r3,r3,#1
-+ bne 2b
-+
-+ subs r2,r2,#1
-+ bne 1b
-+
-+ ldr r0, =CSCR
-+ ldr r1, =CONFIG_SYS_CSCR_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GPCR
-+ ldr r1, =CONFIG_SYS_GPCR_VAL
-+ str r1, [r0]
-+
-+/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
-+ *this.....
-+ *
-+ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
-+ * register 1, this stops it using the output of the PLL and thus runs at the
-+ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
-+ * use the value set in the CM_OSC registers...regardless of what you set it
-+ * too! Thus, although i thought i was running at 140MHz, i'm actually running
-+ * at 40!..
-+
-+ * Slapping this into my bootloader does the trick...
-+
-+ * MRC p15,0,r0,c1,c0,0 ; read core configuration register
-+ * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
-+ * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
-+ * register
-+ */
-+ MRC p15,0,r0,c1,c0,0
-+ ORR r0,r0,#0xC0000000
-+ MCR p15,0,r0,c1,c0,0
-+
-+/* ldr r0, =GPR(0)
-+ ldr r1, =CONFIG_SYS_GPR_A_VAL
-+ str r1, [r0]
-+*/
-+
-+ ldr r0, =DR(0)
-+ ldr r1, =CONFIG_SYS_DR_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR1(0)
-+ ldr r1, =CONFIG_SYS_OCR1_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR2(0)
-+ ldr r1, =CONFIG_SYS_OCR2_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA1(0)
-+ ldr r1, =CONFIG_SYS_ICFA1_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA2(0)
-+ ldr r1, =CONFIG_SYS_ICFA2_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB1(0)
-+ ldr r1, =CONFIG_SYS_ICFB1_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB2(0)
-+ ldr r1, =CONFIG_SYS_ICFB2_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR1(0)
-+ ldr r1, =CONFIG_SYS_ICR1_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR2(0)
-+ ldr r1, =CONFIG_SYS_ICR2_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =IMR(0)
-+ ldr r1, =CONFIG_SYS_IMR_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =DDIR(0)
-+ ldr r1, =CONFIG_SYS_DDIR_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GPR(0)
-+ ldr r1, =CONFIG_SYS_GPR_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =PUEN(0)
-+ ldr r1, =CONFIG_SYS_PUEN_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GIUS(0)
-+ ldr r1, =CONFIG_SYS_GIUS_A_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =DR(1)
-+ ldr r1, =CONFIG_SYS_DR_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR1(1)
-+ ldr r1, =CONFIG_SYS_OCR1_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR2(1)
-+ ldr r1, =CONFIG_SYS_OCR2_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA1(1)
-+ ldr r1, =CONFIG_SYS_ICFA1_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA2(1)
-+ ldr r1, =CONFIG_SYS_ICFA2_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB1(1)
-+ ldr r1, =CONFIG_SYS_ICFB1_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB2(1)
-+ ldr r1, =CONFIG_SYS_ICFB2_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR1(1)
-+ ldr r1, =CONFIG_SYS_ICR1_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR2(1)
-+ ldr r1, =CONFIG_SYS_ICR2_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =IMR(1)
-+ ldr r1, =CONFIG_SYS_IMR_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =DDIR(1)
-+ ldr r1, =CONFIG_SYS_DDIR_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GPR(1)
-+ ldr r1, =CONFIG_SYS_GPR_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =PUEN(1)
-+ ldr r1, =CONFIG_SYS_PUEN_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GIUS(1)
-+ ldr r1, =CONFIG_SYS_GIUS_B_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =DR(2)
-+ ldr r1, =CONFIG_SYS_DR_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR1(2)
-+ ldr r1, =CONFIG_SYS_OCR1_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR2(2)
-+ ldr r1, =CONFIG_SYS_OCR2_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA1(2)
-+ ldr r1, =CONFIG_SYS_ICFA1_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA2(2)
-+ ldr r1, =CONFIG_SYS_ICFA2_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB1(2)
-+ ldr r1, =CONFIG_SYS_ICFB1_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB2(2)
-+ ldr r1, =CONFIG_SYS_ICFB2_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR1(2)
-+ ldr r1, =CONFIG_SYS_ICR1_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR2(2)
-+ ldr r1, =CONFIG_SYS_ICR2_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =IMR(2)
-+ ldr r1, =CONFIG_SYS_IMR_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =DDIR(2)
-+ ldr r1, =CONFIG_SYS_DDIR_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GPR(2)
-+ ldr r1, =CONFIG_SYS_GPR_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =PUEN(2)
-+ ldr r1, =CONFIG_SYS_PUEN_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GIUS(2)
-+ ldr r1, =CONFIG_SYS_GIUS_C_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =DR(3)
-+ ldr r1, =CONFIG_SYS_DR_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR1(3)
-+ ldr r1, =CONFIG_SYS_OCR1_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =OCR2(3)
-+ ldr r1, =CONFIG_SYS_OCR2_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA1(3)
-+ ldr r1, =CONFIG_SYS_ICFA1_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFA2(3)
-+ ldr r1, =CONFIG_SYS_ICFA2_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB1(3)
-+ ldr r1, =CONFIG_SYS_ICFB1_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICONFB2(3)
-+ ldr r1, =CONFIG_SYS_ICFB2_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR1(3)
-+ ldr r1, =CONFIG_SYS_ICR1_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =ICR2(3)
-+ ldr r1, =CONFIG_SYS_ICR2_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =IMR(3)
-+ ldr r1, =CONFIG_SYS_IMR_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =DDIR(3)
-+ ldr r1, =CONFIG_SYS_DDIR_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GPR(3)
-+ ldr r1, =CONFIG_SYS_GPR_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =PUEN(3)
-+ ldr r1, =CONFIG_SYS_PUEN_D_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =GIUS(3)
-+ ldr r1, =CONFIG_SYS_GIUS_D_VAL
-+ str r1, [r0]
-+
-+/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
-+
-+ ldr r0, =FMCR
-+ ldr r1, =CONFIG_SYS_FMCR_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS0U
-+ ldr r1, =CONFIG_SYS_CS0U_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS0L
-+ ldr r1, =CONFIG_SYS_CS0L_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS1U
-+ ldr r1, =CONFIG_SYS_CS1U_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS1L
-+ ldr r1, =CONFIG_SYS_CS1L_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS2U
-+ ldr r1, =CONFIG_SYS_CS2U_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS2L
-+ ldr r1, =CONFIG_SYS_CS2L_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS3U
-+ ldr r1, =CONFIG_SYS_CS3U_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS3L
-+ ldr r1, =CONFIG_SYS_CS3L_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS4U
-+ ldr r1, =CONFIG_SYS_CS4U_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS4L
-+ ldr r1, =CONFIG_SYS_CS4L_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS5U
-+ ldr r1, =CONFIG_SYS_CS5U_VAL
-+ str r1, [r0]
-+
-+ ldr r0, =CS5L
-+ ldr r1, =CONFIG_SYS_CS5L_VAL
-+ str r1, [r0]
-+
-+ adr r0, sdramsetup /* r0 <- current position of code */
-+ /* test if we run from flash or RAM */
-+ ldr r1, =PHYS_SDRAM_1
-+ cmp r1, r0 /* don't reloc during debug*/
-+ bhi sdramsetup
-+ /* test if we run from flash or RAM */
-+ ldr r1, =CONFIG_SYS_FLASH_BASE
-+ cmp r0, r1 /* don't reloc during debug */
-+ bmi copy2ram
-+
-+/* SDRAM Setup */
-+sdramsetup:
-+ ldr r0, =SDCTL0
-+ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
-+ str r1, [r0]
-+
-+ ldr r1, =PHYS_SDRAM_1 \
-+ +CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
-+ ldr r2, [r1]
-+
-+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
-+ str r1, [r0]
-+
-+ ldr r1, =PHYS_SDRAM_1
-+ ldr r2, [r1] /* Issue AutoRefresh Command */
-+ ldr r2, [r1]
-+ ldr r2, [r1]
-+ ldr r2, [r1]
-+ ldr r2, [r1]
-+ ldr r2, [r1]
-+ ldr r2, [r1]
-+ ldr r2, [r1]
-+
-+ ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD
-+ str r1, [r0]
-+
-+ ldr r1, =PHYS_SDRAM_1 \
-+ +CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
-+ str r2, [r1]
-+
-+ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
-+ str r1, [r0]
-+/* make U-Boot runnable form "almost" anywhere */
-+/* but SYS_TEXT_BASE should be in RAM */
-+copy2ram: /* populate _TEXT_BASE with U-Boot from load addr */
-+ ldr r0, _start_adr
-+ ldr r1, _copy2ram
-+ sub r1, r1, r0
-+ adr r0, copy2ram
-+ sub r0, r0, r1
-+ ldr r1, =CONFIG_SYS_TEXT_BASE
-+ cmp r0, r1
-+ beq end_of_copy2ram /* skip U-Boot copy */
-+ ldr r2, =CONFIG_SYS_MONITOR_LEN
-+ add r2, r2, r0 /* r2 <- source end address */
-+
-+copy_loop:
-+ ldmia r0!, {r9-r10} /* copy from source address [r0] */
-+ stmia r1!, {r9-r10} /* copy to target address [r1] */
-+ cmp r0, r2 /* until source end address [r2] */
-+ blo copy_loop
-+
-+end_of_copy2ram:
-+ mov pc,lr
-+
-+_copy2ram:
-+ .word copy2ram
-+_start_adr:
-+ .word _start
---
-1.7.2.5
-
diff --git a/patches/u-boot/2012.10/104-apf9328-makefile.patch b/patches/u-boot/2012.10/104-apf9328-makefile.patch
deleted file mode 100644
index fc15410..0000000
--- a/patches/u-boot/2012.10/104-apf9328-makefile.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-apf9328: add apf9328 board in Makefile
-
-add apf9328 board definition in makefile, MAKEALL and MAINTAINERS list
-
-Signed-off-by: Eric Jarrige <eri...@ar...>
-Signed-off-by: Philippe Reynes <tr...@ya...>
----
- MAINTAINERS | 4 ++++
- boards.cfg | 1 +
- 2 files changed, 5 insertions(+), 0 deletions(-)
-
-diff --git a/MAINTAINERS b/MAINTAINERS
-index b571400..18ac7d3 100644
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -255,6 +255,10 @@ Gabriel Huau <co...@hu...>
-
- mini2440 s3c2440
-
-+Eric Jarrige <eri...@ar...>
-+
-+ apf9328 ARM920T (iMX1)
-+
- Gary Jennejohn <ga...@de...>
-
- quad100hd PPC...
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