[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-264-g832588a
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-264-g832588a
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From: jorasse <jo...@us...> - 2013-05-27 01:12:06
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 832588a251eafebd30c19f8344bc8b5a40532233 (commit)
from f8270ad6feca5a23bbfb5dec26d2e9e8e9954746 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 832588a251eafebd30c19f8344bc8b5a40532233
Author: Eric Jarrige <eri...@ar...>
Date: Mon May 27 03:19:35 2013 +0200
[UBOOT] 2013.04: start update
-----------------------------------------------------------------------
Summary of changes:
.../100-SPL-Add-u-boot-nand-build-option.patch | 0
.../u-boot/{2012.10 => 2013.04}/102-mx1-i2c.patch | 0
.../u-boot/{2012.10 => 2013.04}/103-apf9328.patch | 0
.../104-apf9328-makefile.patch | 0
.../{2012.10 => 2013.04}/106-mx1-pllclk.patch | 0
.../107-mx1-pllclk-debug.patch | 0
.../u-boot/{2012.10 => 2013.04}/108-DM9000.patch | 0
.../{2012.10 => 2013.04}/111-mx1-timer.patch | 0
...stant-to-support-the-armadeus-APF27-board.patch | 49 +
.../301-imx27-add-function-enable_caches.patch | 26 +
...-add-support-for-the-armadeus-APF27-board.patch | 921 +++++++++++++++-----
...pf27-Add-FPGA-support-for-the-apf27-board.patch | 101 +--
.../311-imx-nand-lock-unlock.patch | 0
.../u-boot/{2012.10 => 2013.04}/320-spartan.patch | 0
.../{2013.01.01 => 2013.04}/321-add_spartan6.patch | 0
.../340-apf27-misc-commands.patch | 2 +-
.../350-nand_large_file_download.patch | 0
...60-arm-support-continuous-mmu-mem-mapping.patch | 29 +-
.../370-imx27-add-i2c-driver.patch | 0
.../u-boot/{2013.01.01 => 2013.04}/400-imx51.patch | 35 -
.../u-boot/{2013.01.01 => 2013.04}/401-apf51.patch | 2 +-
.../{2013.01.01 => 2013.04}/403-apf51-wdog.patch | 0
.../{2013.01.01 => 2013.04}/407-imx51-nand.patch | 2 +-
.../{2012.10 => 2013.04}/409-apf51-nand-spl.patch | 0
.../{2013.01.01 => 2013.04}/410-imx-iim.patch | 0
.../501-imx28-update-and-fix.patch | 0
.../{2013.01.01 => 2013.04}/502-add-apf28.patch | 11 +-
27 files changed, 836 insertions(+), 342 deletions(-)
copy patches/u-boot/{2013.01.01 => 2013.04}/100-SPL-Add-u-boot-nand-build-option.patch (100%)
copy patches/u-boot/{2012.10 => 2013.04}/102-mx1-i2c.patch (100%)
copy patches/u-boot/{2012.10 => 2013.04}/103-apf9328.patch (100%)
copy patches/u-boot/{2013.01.01 => 2013.04}/104-apf9328-makefile.patch (100%)
copy patches/u-boot/{2012.10 => 2013.04}/106-mx1-pllclk.patch (100%)
copy patches/u-boot/{2012.10 => 2013.04}/107-mx1-pllclk-debug.patch (100%)
copy patches/u-boot/{2012.10 => 2013.04}/108-DM9000.patch (100%)
copy patches/u-boot/{2012.10 => 2013.04}/111-mx1-timer.patch (100%)
create mode 100644 patches/u-boot/2013.04/301-imx27-Add-missing-constant-to-support-the-armadeus-APF27-board.patch
create mode 100644 patches/u-boot/2013.04/301-imx27-add-function-enable_caches.patch
copy patches/u-boot/{2013.01.01 => 2013.04}/302-apf27-add-support-for-the-armadeus-APF27-board.patch (67%)
copy patches/u-boot/{2012.10 => 2013.04}/304-apf27-Add-FPGA-support-for-the-apf27-board.patch (83%)
copy patches/u-boot/{2012.10 => 2013.04}/311-imx-nand-lock-unlock.patch (100%)
copy patches/u-boot/{2012.10 => 2013.04}/320-spartan.patch (100%)
copy patches/u-boot/{2013.01.01 => 2013.04}/321-add_spartan6.patch (100%)
copy patches/u-boot/{2013.01.01 => 2013.04}/340-apf27-misc-commands.patch (99%)
copy patches/u-boot/{2013.01.01 => 2013.04}/350-nand_large_file_download.patch (100%)
copy patches/u-boot/{2013.01.01 => 2013.04}/360-arm-support-continuous-mmu-mem-mapping.patch (67%)
copy patches/u-boot/{2013.01.01 => 2013.04}/370-imx27-add-i2c-driver.patch (100%)
copy patches/u-boot/{2013.01.01 => 2013.04}/400-imx51.patch (94%)
copy patches/u-boot/{2013.01.01 => 2013.04}/401-apf51.patch (99%)
copy patches/u-boot/{2013.01.01 => 2013.04}/403-apf51-wdog.patch (100%)
copy patches/u-boot/{2013.01.01 => 2013.04}/407-imx51-nand.patch (99%)
copy patches/u-boot/{2012.10 => 2013.04}/409-apf51-nand-spl.patch (100%)
copy patches/u-boot/{2013.01.01 => 2013.04}/410-imx-iim.patch (100%)
copy patches/u-boot/{2013.01.01 => 2013.04}/501-imx28-update-and-fix.patch (100%)
copy patches/u-boot/{2013.01.01 => 2013.04}/502-add-apf28.patch (98%)
diff --git a/patches/u-boot/2013.01.01/100-SPL-Add-u-boot-nand-build-option.patch b/patches/u-boot/2013.04/100-SPL-Add-u-boot-nand-build-option.patch
similarity index 100%
copy from patches/u-boot/2013.01.01/100-SPL-Add-u-boot-nand-build-option.patch
copy to patches/u-boot/2013.04/100-SPL-Add-u-boot-nand-build-option.patch
diff --git a/patches/u-boot/2012.10/102-mx1-i2c.patch b/patches/u-boot/2013.04/102-mx1-i2c.patch
similarity index 100%
copy from patches/u-boot/2012.10/102-mx1-i2c.patch
copy to patches/u-boot/2013.04/102-mx1-i2c.patch
diff --git a/patches/u-boot/2012.10/103-apf9328.patch b/patches/u-boot/2013.04/103-apf9328.patch
similarity index 100%
copy from patches/u-boot/2012.10/103-apf9328.patch
copy to patches/u-boot/2013.04/103-apf9328.patch
diff --git a/patches/u-boot/2013.01.01/104-apf9328-makefile.patch b/patches/u-boot/2013.04/104-apf9328-makefile.patch
similarity index 100%
copy from patches/u-boot/2013.01.01/104-apf9328-makefile.patch
copy to patches/u-boot/2013.04/104-apf9328-makefile.patch
diff --git a/patches/u-boot/2012.10/106-mx1-pllclk.patch b/patches/u-boot/2013.04/106-mx1-pllclk.patch
similarity index 100%
copy from patches/u-boot/2012.10/106-mx1-pllclk.patch
copy to patches/u-boot/2013.04/106-mx1-pllclk.patch
diff --git a/patches/u-boot/2012.10/107-mx1-pllclk-debug.patch b/patches/u-boot/2013.04/107-mx1-pllclk-debug.patch
similarity index 100%
copy from patches/u-boot/2012.10/107-mx1-pllclk-debug.patch
copy to patches/u-boot/2013.04/107-mx1-pllclk-debug.patch
diff --git a/patches/u-boot/2012.10/108-DM9000.patch b/patches/u-boot/2013.04/108-DM9000.patch
similarity index 100%
copy from patches/u-boot/2012.10/108-DM9000.patch
copy to patches/u-boot/2013.04/108-DM9000.patch
diff --git a/patches/u-boot/2012.10/111-mx1-timer.patch b/patches/u-boot/2013.04/111-mx1-timer.patch
similarity index 100%
copy from patches/u-boot/2012.10/111-mx1-timer.patch
copy to patches/u-boot/2013.04/111-mx1-timer.patch
diff --git a/patches/u-boot/2013.04/301-imx27-Add-missing-constant-to-support-the-armadeus-APF27-board.patch b/patches/u-boot/2013.04/301-imx27-Add-missing-constant-to-support-the-armadeus-APF27-board.patch
new file mode 100644
index 0000000..74a645b
--- /dev/null
+++ b/patches/u-boot/2013.04/301-imx27-Add-missing-constant-to-support-the-armadeus-APF27-board.patch
@@ -0,0 +1,49 @@
+Add some missing constant (chip select, ...), and
+a file mxc_nand.h with the NFC constant.
+
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+ arch/arm/cpu/arm926ejs/mx27/asm-offsets.c | 5 +++++
+ arch/arm/include/asm/arch-mx27/imx-regs.h | 3 ++-
+ 2 files changed, 7 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+index f3a8d7b..215c562 100644
+--- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
++++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+@@ -41,5 +41,10 @@ int main(void)
+ DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
+ DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+
++ DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
++ offsetof(struct system_control_regs, gpcr));
++ DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
++ offsetof(struct system_control_regs, fmcr));
++
+ return 0;
+ }
+diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
+index 8867e9f..707ca4b 100644
+--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
++++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
+@@ -185,7 +185,7 @@ struct iim_regs {
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ u32 fuse_rsvd[0xe0];
+- } bank[1];
++ } bank[2];
+ };
+
+ struct fuse_bank0_regs {
+@@ -225,6 +225,7 @@ struct fuse_bank0_regs {
+ #define IIM_BASE_ADDR IMX_IIM_BASE
+ #define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE)
+
++#define IMX_NFC_BASE (0xD8000000)
+ #define IMX_ESD_BASE (0xD8001000)
+ #define IMX_WEIM_BASE (0xD8002000)
+
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2013.04/301-imx27-add-function-enable_caches.patch b/patches/u-boot/2013.04/301-imx27-add-function-enable_caches.patch
new file mode 100644
index 0000000..6c19eda
--- /dev/null
+++ b/patches/u-boot/2013.04/301-imx27-add-function-enable_caches.patch
@@ -0,0 +1,26 @@
+mx27: add function enable_caches
+
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+ arch/arm/cpu/arm926ejs/mx27/generic.c | 6 ++++++
+ 1 files changed, 6 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/cpu/arm926ejs/mx27/generic.c b/arch/arm/cpu/arm926ejs/mx27/generic.c
+index 41bb84b..4239fa0 100644
+--- a/arch/arm/cpu/arm926ejs/mx27/generic.c
++++ b/arch/arm/cpu/arm926ejs/mx27/generic.c
+@@ -380,3 +380,9 @@ void mx27_sd2_init_pins(void)
+
+ }
+ #endif /* CONFIG_MXC_MMC */
++
++void enable_caches(void)
++{
++ /* Enable D-cache. I-cache is already enabled in start.S */
++ dcache_enable();
++}
+--
+1.7.4.4
+
+
diff --git a/patches/u-boot/2013.01.01/302-apf27-add-support-for-the-armadeus-APF27-board.patch b/patches/u-boot/2013.04/302-apf27-add-support-for-the-armadeus-APF27-board.patch
similarity index 67%
copy from patches/u-boot/2013.01.01/302-apf27-add-support-for-the-armadeus-APF27-board.patch
copy to patches/u-boot/2013.04/302-apf27-add-support-for-the-armadeus-APF27-board.patch
index f4df5bf..b99faaf 100644
--- a/patches/u-boot/2013.01.01/302-apf27-add-support-for-the-armadeus-APF27-board.patch
+++ b/patches/u-boot/2013.04/302-apf27-add-support-for-the-armadeus-APF27-board.patch
@@ -4,33 +4,42 @@ Signed-off-by: Philippe Reynes <tr...@ya...>
Signed-off-by: Eric Jarrige <eri...@ar...>
Signed-off-by: Nicolas Colombain <nic...@ar...>
---
+ MAINTAINERS | 5 +
+ board/armadeus/apf27/Makefile | 51 ++++
+ board/armadeus/apf27/apf27.c | 362 +++++++++++++++++++++++++++++
+ board/armadeus/apf27/apf27.h | 450 ++++++++++++++++++++++++++++++++++++
+ board/armadeus/apf27/splboot.S | 500 ++++++++++++++++++++++++++++++++++++++++
+ boards.cfg | 1 +
+ include/configs/apf27.h | 448 +++++++++++++++++++++++++++++++++++
+ 7 files changed, 1817 insertions(+), 0 deletions(-)
create mode 100644 board/armadeus/apf27/Makefile
create mode 100644 board/armadeus/apf27/apf27.c
create mode 100644 board/armadeus/apf27/apf27.h
+ create mode 100644 board/armadeus/apf27/splboot.S
create mode 100644 include/configs/apf27.h
diff --git a/MAINTAINERS b/MAINTAINERS
-index 1b2da94..297467a 100644
+index 7c12d95..445527d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -1028,6 +1028,11 @@ Nobuhiro Iwamatsu <nob...@re...>
-
- nokia_rx51 ARM ARMV7 (OMAP34xx SoC)
+@@ -712,6 +712,11 @@ Ilko Iliev <il...@ro...>
+ PM9263 AT91SAM9263
+ PM9G45 ARM926EJS (AT91SAM9G45 SoC)
+Eric Jarrige <eri...@ar...>
+Philippe Reynes <tr...@ya...>
+
-+ apf27 ARM926EJS (imx27 SoC)
++ apf27 ARM926EJS (i.MX27 SoC)
+
- -------------------------------------------------------------------------
+ Michael Jones <mic...@ma...>
- Unknown / orphaned boards:
+ omap3_mvblx ARM ARMV7 (OMAP3xx SoC)
diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile
new file mode 100644
-index 0000000..1da9548
+index 0000000..08d5d8d
--- /dev/null
+++ b/board/armadeus/apf27/Makefile
-@@ -0,0 +1,45 @@
+@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd...@de....
@@ -60,9 +69,15 @@ index 0000000..1da9548
+
+LIB = $(obj)lib$(BOARD).o
+
++ifndef CONFIG_SPL_BUILD
+COBJS := apf27.o
++endif
++
++ifdef CONFIG_SPL_BUILD
++SOBJS := splboot.o
++endif
+
-+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++SRCS := $(COBJS:.o=.c) $(SOBJS:.o=.S)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
@@ -78,10 +93,10 @@ index 0000000..1da9548
+#########################################################################
diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
new file mode 100644
-index 0000000..bf3e5ec
+index 0000000..fce3325
--- /dev/null
+++ b/board/armadeus/apf27/apf27.c
-@@ -0,0 +1,423 @@
+@@ -0,0 +1,356 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ * Copyright (C) 2008-2012 Eric Jarrige <eri...@ar...>
@@ -104,7 +119,7 @@ index 0000000..bf3e5ec
+ */
+
+#include <common.h>
-+#include "crc.h"
++#include <environment.h>
+#include <jffs2/jffs2.h>
+#include <nand.h>
+#include <netdev.h>
@@ -112,20 +127,28 @@ index 0000000..bf3e5ec
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/gpio.h>
+#include <asm/errno.h>
-+#include <environment.h>
+#include "apf27.h"
++#include "crc.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
++static inline void wait(void)
++{
++ int i;
++
++ for (i = 0; i < 0x10000; i++)
++ asm volatile ("nop");
++}
++
+/*
+ * Fuse bank 1 row 8 is "reserved for future use" and therefore available for
-+ * custormer use. The APF27 board uses this fuse to store the board revision:
++ * customer use. The APF27 board uses this fuse to store the board revision:
+ * 0: initial board revision
+ * 1: first revision - Presence of the second RAM chip on the board is blown in
+ * fuse bank 1 row 9 bit 0 - No hardware change
+ * N: to be defined
+ */
-+u32 get_board_rev(void)
++static u32 get_board_rev(void)
+{
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+
@@ -134,12 +157,12 @@ index 0000000..bf3e5ec
+
+/*
+ * Fuse bank 1 row 9 is "reserved for future use" and therefore available for
-+ * custormer use. The APF27 board revision 1 uses the bit 0 to permanently store
++ * customer use. The APF27 board revision 1 uses the bit 0 to permanently store
+ * the presence of the second RAM chip
+ * 0: AFP27 with 1 RAM of 64 MiB
+ * 1: AFP27 with 2 RAM chips of 64 MiB each (128MB)
+ */
-+int get_num_ram_bank(void)
++static int get_num_ram_bank(void)
+{
+ struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+ int nr_dram_banks = 1;
@@ -152,109 +175,45 @@ index 0000000..bf3e5ec
+ return nr_dram_banks;
+}
+
-+static void apf27_gpio_init(void)
++static void apf27_port_init(int port, u32 gpio_dr, u32 ocr1, u32 ocr2,
++ u32 iconfa1, u32 iconfa2, u32 iconfb1, u32 iconfb2,
++ u32 icr1, u32 icr2, u32 imr, u32 gpio_dir, u32 gpr,
++ u32 puen, u32 gius)
+{
+ struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
+
-+ /* PORT A */
-+ writel(ACFG_DR_A_VAL, ®s->port[PORTA].gpio_dr);
-+ writel(ACFG_OCR1_A_VAL, ®s->port[PORTA].ocr1);
-+ writel(ACFG_OCR2_A_VAL, ®s->port[PORTA].ocr2);
-+ writel(ACFG_ICFA1_A_VAL, ®s->port[PORTA].iconfa1);
-+ writel(ACFG_ICFA2_A_VAL, ®s->port[PORTA].iconfa2);
-+ writel(ACFG_ICFB1_A_VAL, ®s->port[PORTA].iconfb1);
-+ writel(ACFG_ICFB2_A_VAL, ®s->port[PORTA].iconfb2);
-+ writel(ACFG_ICR1_A_VAL, ®s->port[PORTA].icr1);
-+ writel(ACFG_ICR2_A_VAL, ®s->port[PORTA].icr2);
-+ writel(ACFG_IMR_A_VAL, ®s->port[PORTA].imr);
-+ writel(ACFG_DDIR_A_VAL, ®s->port[PORTA].gpio_dir);
-+ writel(ACFG_GPR_A_VAL, ®s->port[PORTA].gpr);
-+ writel(ACFG_PUEN_A_VAL, ®s->port[PORTA].puen);
-+ writel(ACFG_GIUS_A_VAL, ®s->port[PORTA].gius);
-+
-+ /* PORT B */
-+ writel(ACFG_DR_B_VAL, ®s->port[PORTB].gpio_dr);
-+ writel(ACFG_OCR1_B_VAL, ®s->port[PORTB].ocr1);
-+ writel(ACFG_OCR2_B_VAL, ®s->port[PORTB].ocr2);
-+ writel(ACFG_ICFA1_B_VAL, ®s->port[PORTB].iconfa1);
-+ writel(ACFG_ICFA2_B_VAL, ®s->port[PORTB].iconfa2);
-+ writel(ACFG_ICFB1_B_VAL, ®s->port[PORTB].iconfb1);
-+ writel(ACFG_ICFB2_B_VAL, ®s->port[PORTB].iconfb2);
-+ writel(ACFG_ICR1_B_VAL, ®s->port[PORTB].icr1);
-+ writel(ACFG_ICR2_B_VAL, ®s->port[PORTB].icr2);
-+ writel(ACFG_IMR_B_VAL, ®s->port[PORTB].imr);
-+ writel(ACFG_DDIR_B_VAL, ®s->port[PORTB].gpio_dir);
-+ writel(ACFG_GPR_B_VAL, ®s->port[PORTB].gpr);
-+ writel(ACFG_PUEN_B_VAL, ®s->port[PORTB].puen);
-+ writel(ACFG_GIUS_B_VAL, ®s->port[PORTB].gius);
-+
-+ /* PORT C */
-+ writel(ACFG_DR_C_VAL, ®s->port[PORTC].gpio_dr);
-+ writel(ACFG_OCR1_C_VAL, ®s->port[PORTC].ocr1);
-+ writel(ACFG_OCR2_C_VAL, ®s->port[PORTC].ocr2);
-+ writel(ACFG_ICFA1_C_VAL, ®s->port[PORTC].iconfa1);
-+ writel(ACFG_ICFA2_C_VAL, ®s->port[PORTC].iconfa2);
-+ writel(ACFG_ICFB1_C_VAL, ®s->port[PORTC].iconfb1);
-+ writel(ACFG_ICFB2_C_VAL, ®s->port[PORTC].iconfb2);
-+ writel(ACFG_ICR1_C_VAL, ®s->port[PORTC].icr1);
-+ writel(ACFG_ICR2_C_VAL, ®s->port[PORTC].icr2);
-+ writel(ACFG_IMR_C_VAL, ®s->port[PORTC].imr);
-+ writel(ACFG_DDIR_C_VAL, ®s->port[PORTC].gpio_dir);
-+ writel(ACFG_GPR_C_VAL, ®s->port[PORTC].gpr);
-+ writel(ACFG_PUEN_C_VAL, ®s->port[PORTC].puen);
-+ writel(ACFG_GIUS_C_VAL, ®s->port[PORTC].gius);
-+
-+ /* PORT D */
-+ writel(ACFG_DR_D_VAL, ®s->port[PORTD].gpio_dr);
-+ writel(ACFG_OCR1_D_VAL, ®s->port[PORTD].ocr1);
-+ writel(ACFG_OCR2_D_VAL, ®s->port[PORTD].ocr2);
-+ writel(ACFG_ICFA1_D_VAL, ®s->port[PORTD].iconfa1);
-+ writel(ACFG_ICFA2_D_VAL, ®s->port[PORTD].iconfa2);
-+ writel(ACFG_ICFB1_D_VAL, ®s->port[PORTD].iconfb1);
-+ writel(ACFG_ICFB2_D_VAL, ®s->port[PORTD].iconfb2);
-+ writel(ACFG_ICR1_D_VAL, ®s->port[PORTD].icr1);
-+ writel(ACFG_ICR2_D_VAL, ®s->port[PORTD].icr2);
-+ writel(ACFG_IMR_D_VAL, ®s->port[PORTD].imr);
-+ writel(ACFG_DDIR_D_VAL, ®s->port[PORTD].gpio_dir);
-+ writel(ACFG_GPR_D_VAL, ®s->port[PORTD].gpr);
-+ writel(ACFG_PUEN_D_VAL, ®s->port[PORTD].puen);
-+ writel(ACFG_GIUS_D_VAL, ®s->port[PORTD].gius);
-+
-+ /* PORT E */
-+ writel(ACFG_DR_E_VAL, ®s->port[PORTE].gpio_dr);
-+ writel(ACFG_OCR1_E_VAL, ®s->port[PORTE].ocr1);
-+ writel(ACFG_OCR2_E_VAL, ®s->port[PORTE].ocr2);
-+ writel(ACFG_ICFA1_E_VAL, ®s->port[PORTE].iconfa1);
-+ writel(ACFG_ICFA2_E_VAL, ®s->port[PORTE].iconfa2);
-+ writel(ACFG_ICFB1_E_VAL, ®s->port[PORTE].iconfb1);
-+ writel(ACFG_ICFB2_E_VAL, ®s->port[PORTE].iconfb2);
-+ writel(ACFG_ICR1_E_VAL, ®s->port[PORTE].icr1);
-+ writel(ACFG_ICR2_E_VAL, ®s->port[PORTE].icr2);
-+ writel(ACFG_IMR_E_VAL, ®s->port[PORTE].imr);
-+ writel(ACFG_DDIR_E_VAL, ®s->port[PORTE].gpio_dir);
-+ writel(ACFG_GPR_E_VAL, ®s->port[PORTE].gpr);
-+ writel(ACFG_PUEN_E_VAL, ®s->port[PORTE].puen);
-+ writel(ACFG_GIUS_E_VAL, ®s->port[PORTE].gius);
-+
-+ /* PORT F */
-+ writel(ACFG_DR_F_VAL, ®s->port[PORTF].gpio_dr);
-+ writel(ACFG_OCR1_F_VAL, ®s->port[PORTF].ocr1);
-+ writel(ACFG_OCR2_F_VAL, ®s->port[PORTF].ocr2);
-+ writel(ACFG_ICFA1_F_VAL, ®s->port[PORTF].iconfa1);
-+ writel(ACFG_ICFA2_F_VAL, ®s->port[PORTF].iconfa2);
-+ writel(ACFG_ICFB1_F_VAL, ®s->port[PORTF].iconfb1);
-+ writel(ACFG_ICFB2_F_VAL, ®s->port[PORTF].iconfb2);
-+ writel(ACFG_ICR1_F_VAL, ®s->port[PORTF].icr1);
-+ writel(ACFG_ICR2_F_VAL, ®s->port[PORTF].icr2);
-+ writel(ACFG_IMR_F_VAL, ®s->port[PORTF].imr);
-+ writel(ACFG_DDIR_F_VAL, ®s->port[PORTF].gpio_dir);
-+ writel(ACFG_GPR_F_VAL, ®s->port[PORTF].gpr);
-+ writel(ACFG_PUEN_F_VAL, ®s->port[PORTF].puen);
-+ writel(ACFG_GIUS_F_VAL, ®s->port[PORTF].gius);
++ writel(gpio_dr, ®s->port[port].gpio_dr);
++ writel(ocr1, ®s->port[port].ocr1);
++ writel(ocr2, ®s->port[port].ocr2);
++ writel(iconfa1, ®s->port[port].iconfa1);
++ writel(iconfa2, ®s->port[port].iconfa2);
++ writel(iconfb1, ®s->port[port].iconfb1);
++ writel(iconfb2, ®s->port[port].iconfb2);
++ writel(icr1, ®s->port[port].icr1);
++ writel(icr2, ®s->port[port].icr2);
++ writel(imr, ®s->port[port].imr);
++ writel(gpio_dir, ®s->port[port].gpio_dir);
++ writel(gpr, ®s->port[port].gpr);
++ writel(puen, ®s->port[port].puen);
++ writel(gius, ®s->port[port].gius);
+}
+
-+void bus_i2c_init(void *base, int speed, int slave_addr,
-+ int (*idle_bus_fn)(void *p), void *p);
++#define APF27_PORT_INIT(n) apf27_port_init(PORT##n, ACFG_DR_##n##_VAL, \
++ ACFG_OCR1_##n##_VAL, ACFG_OCR2_##n##_VAL, ACFG_ICFA1_##n##_VAL, \
++ ACFG_ICFA2_##n##_VAL, ACFG_ICFB1_##n##_VAL, ACFG_ICFB2_##n##_VAL, \
++ ACFG_ICR1_##n##_VAL, ACFG_ICR2_##n##_VAL, ACFG_IMR_##n##_VAL, \
++ ACFG_DDIR_##n##_VAL, ACFG_GPR_##n##_VAL, ACFG_PUEN_##n##_VAL, \
++ ACFG_GIUS_##n##_VAL)
++
++void apf27_gpio_init(void)
++{
++ APF27_PORT_INIT(A);
++ APF27_PORT_INIT(B);
++ APF27_PORT_INIT(C);
++ APF27_PORT_INIT(D);
++ APF27_PORT_INIT(E);
++ APF27_PORT_INIT(F);
++}
+
+static int apf27_devices_init(void)
+{
@@ -294,13 +253,13 @@ index 0000000..bf3e5ec
+ mx27_sd2_init_pins();
+ imx_gpio_mode((GPIO_PORTF | GPIO_OUT | GPIO_PUEN | GPIO_GPIO | 16));
+ writel(readl(®s->port[PORTF].gpio_dr) | (1 << 16),
-+ ®s->port[PORTF].gpio_dr);
++ ®s->port[PORTF].gpio_dr);
+#endif
+#if defined(CONFIG_I2C_MXC) && defined(CONFIG_I2C_MULTI_BUS)
+ bus_i2c_init(IMX_I2C1_BASE, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
-+ NULL, NULL);
++ NULL, NULL);
+ bus_i2c_init(IMX_I2C2_BASE, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
-+ NULL, NULL);
++ NULL, NULL);
+#endif
+ return 0;
+}
@@ -309,7 +268,7 @@ index 0000000..bf3e5ec
+{
+ struct aipi_regs *aipi1 = (struct aipi_regs *)IMX_AIPI1_BASE;
+ struct aipi_regs *aipi2 = (struct aipi_regs *)IMX_AIPI2_BASE;
-+ struct system_control_regs *system = \
++ struct system_control_regs *system =
+ (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
+ u32 gpcr;
+
@@ -358,33 +317,31 @@ index 0000000..bf3e5ec
+
+static void board_setup_port(void)
+{
-+ struct system_control_regs *system = \
++ struct system_control_regs *system =
+ (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
+
+ writel(ACFG_FMCR_VAL, &system->fmcr);
+}
+
-+static void board_setup_clock()
++static void board_setup_clock(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-+ volatile int wait = 0x1000;
+ u32 cscr;
+
+ /* disable MPLL/SPLL first */
+ cscr = readl(&pll->cscr);
-+ cscr &= ~(CSCR_MPEN|CSCR_SPEN);
++ cscr &= ~(CSCR_MPEN | CSCR_SPEN);
+ writel(cscr, &pll->cscr);
+
+ /* pll clock initialization */
+ writel(ACFG_MPCTL0_VAL, &pll->mpctl0);
+ writel(ACFG_SPCTL0_VAL, &pll->spctl0);
+
-+ cscr = ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART;
++ cscr = ACFG_CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART;
+ writel(cscr, &pll->cscr);
+
+ /* add some delay here */
-+ while (wait)
-+ wait--;
++ wait();
+
+ /* peripheral clock divider */
+ writel(ACFG_PCDR0_VAL, &pll->pcdr0);
@@ -405,8 +362,7 @@ index 0000000..bf3e5ec
+ return 0;
+}
+
-+int
-+board_init(void)
++int board_init(void)
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
@@ -416,8 +372,7 @@ index 0000000..bf3e5ec
+ return 0;
+}
+
-+int
-+dram_init(void)
++int dram_init(void)
+{
+ /* dram_init must store complete ramsize in gd->ram_size */
+ if (get_num_ram_bank() > 1) {
@@ -435,37 +390,32 @@ index 0000000..bf3e5ec
+{
+ phys_size_t ramsize = gd->ram_size;
+
-+ if (get_num_ram_bank() > 1) {
++ if (get_num_ram_bank() > 1)
+ ramsize -= PHYS_SDRAM_2 - CONFIG_SYS_SDRAM_BASE;
-+ }
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = ramsize;
-+ gd->ram_size = gd->bd->bi_dram[0].size;
-+
-+ if (CONFIG_NR_DRAM_BANKS > 1) {
-+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-+ if (get_num_ram_bank() > 1) {
-+ gd->bd->bi_dram[1].size = ramsize;
-+ } else {
-+ gd->bd->bi_dram[1].size = 0;
-+ }
-+ gd->ram_size += gd->bd->bi_dram[1].size;
-+ }
++ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
++ if (get_num_ram_bank() > 1)
++ gd->bd->bi_dram[1].size = ramsize;
++ else
++ gd->bd->bi_dram[1].size = 0;
++ gd->ram_size = gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size;
+}
+
+/*
-+ * Miscellaneous intialization
++ * Miscellaneous initialisation
+ */
-+int
-+misc_init_r(void)
++int misc_init_r(void)
+{
+ char *s;
-+ u_char * firmware_buffer = (u_char *)(CONFIG_SYS_LOAD_ADDR + \
++ u_char *firmware_buffer = (u_char *)(CONFIG_SYS_LOAD_ADDR +
+ CONFIG_SYS_MONITOR_LEN);
+ size_t size = 0;
+ size_t offset = -1;
++#if defined(CONFIG_FPGA)
+ char *autoload = getenv("firmware_autoload");
++#endif
+ u8 pnum;
+ struct mtd_device *dev;
+ struct part_info *part;
@@ -473,17 +423,19 @@ index 0000000..bf3e5ec
+ /* detect compatibility issue of environment version */
+ s = getenv("env_version");
+ if ((NULL == s) || (0 != strcmp(s, CONFIG_ENV_VERSION))) {
-+ char * const vars[] = {"flash_reset_env"};
-+ printf("*** Warning - Environment version change suggests: "
-+ "run flash_reset_env; reset\n");
++ char *const vars[] = {"flash_reset_env"};
++ printf("*** Warning - Environment version change suggests: ");
++ printf("run flash_reset_env; reset\n");
+ set_default_vars(1, vars);
+ }
+
+ /* Unlock whole flash but U-Boot */
-+ s = getenv("env_offset");
-+ offset = CONFIG_ENV_OFFSET;
-+ if ((s != NULL) && (0 != strcmp(s, "0")))
-+ offset = simple_strtoul(s, NULL, 16);
++ if (mtdparts_init() == 0) {
++ if (find_dev_and_part("u-boot",
++ &dev, &pnum, &part) == 0) {
++ offset = part->size;
++ }
++ }
+
+ if (nand_unlock(&nand_info[0], offset, nand_info[0].size - offset, 0))
+ printf("NAND flash lock/unlocked failed\n");
@@ -498,19 +450,15 @@ index 0000000..bf3e5ec
+ return 0;
+}
+
-+void enable_caches(void)
++void lowlevel_init(void)
+{
-+ /* Enable D-cache. I-cache is already enabled in start.S */
-+ dcache_enable();
+}
-+
-+inline void lowlevel_init(void) {}
diff --git a/board/armadeus/apf27/apf27.h b/board/armadeus/apf27/apf27.h
new file mode 100644
-index 0000000..bb007e8
+index 0000000..b0a4473
--- /dev/null
+++ b/board/armadeus/apf27/apf27.h
-@@ -0,0 +1,477 @@
+@@ -0,0 +1,450 @@
+#ifndef __APF27_H
+#define __APF27_H
+
@@ -527,42 +475,20 @@ index 0000000..bb007e8
+#define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */
+#define ACFG_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */
+
-+/* MPU CLOCK source before PLL */
-+/* ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ) */
-+#ifndef CONFIG_MX27_CLK26
-+#if (CONFIG_MX27_CLK32 == 32000)
-+#define ACFG_MPCTL0_VAL 0x00211803 /* 398.998 MHz */
-+#define ACFG_MPCTL1_VAL 0
-+#define CONFIG_MPLL_FREQ 399
-+#else /* CONFIG_MX27_CLK32 == 32768*/
++/*
++ * MPU CLOCK source before PLL
++ * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ)
++ */
+#define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */
+#define ACFG_MPCTL1_VAL 0
+#define CONFIG_MPLL_FREQ 399
-+#endif /* CONFIG_MX27_CLK32 */
-+#else /* CONFIG_MX27_CLK26 in use*/
-+#define ACFG_MPCTL0_VAL 0x00331C23 /* 399.000 MHz */
-+#define ACFG_MPCTL1_VAL 0
-+#define CONFIG_MPLL_FREQ 399
-+#endif /* CONFIG_MX27_CLK26 */
+
+#define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
+
+/* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/
-+#ifndef CONFIG_MX27_CLK26
-+#if (CONFIG_MX27_CLK32 == 32000)
-+#define ACFG_SPCTL0_VAL 0x04A02419 /* 300.00020 MHz */
-+#define ACFG_SPCTL1_VAL 0
-+#define CONFIG_SPLL_FREQ 300 /* MHz */
-+#else /* CONFIG_MX27_CLK32 == 32768*/
+#define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */
+#define ACFG_SPCTL1_VAL 0
+#define CONFIG_SPLL_FREQ 300 /* MHz */
-+#endif /* CONFIG_MX27_CLK32 */
-+#else /* CONFIG_MX27_CLK26 in use*/
-+#define ACFG_SPCTL0_VAL 0x040C2C07 /* 300 MHz */
-+#define ACFG_SPCTL1_VAL 0x0
-+#define CONFIG_SPLL_FREQ 300 /* MHz */
-+#endif /* CONFIG_MX27_CLK26 */
+
+/* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */
+#define CONFIG_ARM_FREQ 399 /* up to 400 MHz */
@@ -752,7 +678,11 @@ index 0000000..bb007e8
+
+#define ACFG_EIM_VAL 0x00002200
+
-+/* FPGA specific settings */
++
++/*
++ * FPGA specific settings
++ */
++
+/* CLKO */
+#define ACFG_CCSR_VAL 0x00000305
+/* drive strength CLKO set to 2*/
@@ -768,7 +698,6 @@ index 0000000..bb007e8
+/*
+ * Default configuration for GPIOs and peripherals
+ */
-+#ifndef ACFG_APF27_CUSTOM
+#define ACFG_DDIR_A_VAL 0x00000000
+#define ACFG_OCR1_A_VAL 0x00000000
+#define ACFG_OCR2_A_VAL 0x00000000
@@ -858,12 +787,11 @@ index 0000000..bb007e8
+#define ACFG_IMR_F_VAL 0x00000000
+#define ACFG_GPR_F_VAL 0x00000000
+#define ACFG_PUEN_F_VAL 0xFFFFFFFF
-+#endif /* ACFG_APF27_CUSTOM */
+
+/* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */
+#define ACFG_GPCR_VAL 0x0003000F
+
-+#define ACFG_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN
++#define ACFG_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN
+
+/* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */
+#if (CONFIG_NR_DRAM_BANKS == 1)
@@ -872,18 +800,14 @@ index 0000000..bb007e8
+#define ACFG_FMCR_VAL 0xFFFFFFFB
+#endif
+
-+#ifndef ACFG_APF27_CUSTOM
+#define ACFG_AIPI1_PSR0_VAL 0x20040304
+#define ACFG_AIPI1_PSR1_VAL 0xDFFBFCFB
+#define ACFG_AIPI2_PSR0_VAL 0x00000000
+#define ACFG_AIPI2_PSR1_VAL 0xFFFFFFFF
-+#endif /* ACFG_APF27_CUSTOM */
+
+/* PCCR enable DMA FEC I2C1 IIM SDHC1 */
-+#ifndef ACFG_APF27_CUSTOM
+#define ACFG_PCCR0_VAL 0x05070410
+#define ACFG_PCCR1_VAL 0xA14A0608
-+#endif /* ACFG_APF27_CUSTOM */
+
+/*
+ * From here, there should not be any user configuration.
@@ -891,15 +815,12 @@ index 0000000..bb007e8
+ */
+
+/* fixme none integer value (7.5ns) => 2*hclock = 15ns */
-+#define ACFG_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */
++#define ACFG_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */
+
+/* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/
-+#ifdef CONFIG_MX27_CLK26
-+#define CSCR_MASK 0x0303800D
-+#else
+#define CSCR_MASK 0x0300800D
-+#endif
-+#define ACFG_CSCR_VAL\
++
++#define ACFG_CSCR_VAL \
+ (CSCR_MASK \
+ |((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28) \
+ |((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12) \
@@ -923,8 +844,8 @@ index 0000000..bb007e8
+ |((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24))
+
+/* SDRAM controller programming Values */
-+#if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) \
-+ || (ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1))
++#if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \
++ (ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1))
+#define REG_FIELD_SCL_VAL 3
+#define REG_FIELD_SCLIMX_VAL 0
+#else
@@ -988,24 +909,558 @@ index 0000000..bb007e8
+#define ACFG_SDRAM_PRECHARGE_ALL_VAL (1<<10)
+
+#endif /* __APF27_H */
+diff --git a/board/armadeus/apf27/splboot.S b/board/armadeus/apf27/splboot.S
+new file mode 100644
+index 0000000..bc30acc
+--- /dev/null
++++ b/board/armadeus/apf27/splboot.S
+@@ -0,0 +1,528 @@
++/*
++ * IMX27 NAND Flash SPL (Secondary Program Loader)
++ *
++ * Copyright (c) 2008 Armadeus Project / eja
++ *
++ * Based on Freescale NAND SPL
++ *
++ * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
++ * Copyright (c) 2008-2012 Eric Jarrige <eri...@ar...>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <generated/asm-offsets.h>
++#include <version.h>
++#include <asm/macro.h>
++#include <asm/arch/imx-regs.h>
++/* #include <linux/linkage.h> */
++#include "apf27.h"
++
++/*
++ * Standard NAND flash commands
++ */
++#define NAND_CMD_READ0 0
++
++/* Extended commands for large page devices */
++#define NAND_CMD_READSTART 0x30
++#define NAND_CMD_CACHEDPROG 0x15
++
++/* Status bits */
++#define NAND_STATUS_FAIL 0x01
++#define NAND_STATUS_FAIL_N1 0x02
++#define NAND_STATUS_TRUE_READY 0x20
++#define NAND_STATUS_READY 0x40
++#define NAND_STATUS_WP 0x80
++
++#define IMX_NFC_MAIN_AREA0 (0xD8000000)
++#define IMX_NFC_MAIN_AREA1 (0xD8000200)
++#define IMX_NFC_SPARE_AREA0 (0xD8000800)
++#define IMX_NFC_REGS (0xD8000E00)
++
++/*
++ * NFC registers address offset
++ */
++#define NFC_OFFSET_BUF_ADDR (0x04) /* Buffer Number for Page Data
++ Transfer To/From Flash Mem */
++#define NFC_OFFSET_FLASH_ADDR (0x06) /* NAND Flash Address */
++#define NFC_OFFSET_FLASH_CMD (0x08) /* NAND Flash Command */
++#define NFC_OFFSET_CONFIG (0x0A) /* NFC Internal Buffer Lock
++ Control */
++#define NFC_OFFSET_ECC_STATUS_RESULT (0x0C) /* Controller Status/Result of
++ Flash Operation */
++#define NFC_OFFSET_CONFIG1 (0x1A) /* Nand Flash Operation
++ Configuration 1 */
++#define NFC_OFFSET_CONFIG2 (0x1C) /* Nand Flash Operation
++ Configuration 2 */
++
++/* NFC_ECC_STATUS_RESULT Status Register Bit Fields */
++#define NFC_ECC_STAT_ERM_SHFT (2) /* ERM shift */
++#define NFC_ECC_STAT_ERROR2 (1<<1) /* non correctable error */
++
++/* NFC_CONFIG Control Register Bit Fields */
++#define NFC_CONFIG_UNLOCKED (1<<1) /* unlocked */
++
++/* NFC_CONFIG1 Control Register Bit Fields */
++#define NFC_CONFIG1_ECC_EN (1<<3)
++#define NFC_CONFIG1_INT_MSK (1<<4)
++
++/* NFC_CONFIG2 Control Register Bit Fields */
++#define NFC_CONFIG2_INT (1<<15) /* Interrupt */
++#define NFC_CONFIG2_FDO_PAGE (1<<3) /* Flash data output */
++#define NFC_CONFIG2_FDI (1<<2) /* Flash data input */
++#define NFC_CONFIG2_FADD (1<<1) /* Flash address input */
++#define NFC_CONFIG2_FCMD (1<<0) /* Flash command input */
++
++ .macro nand_boot
++
++#ifdef CONFIG_BOOT_TRACE_REG
++/*
++ * If CONFIG_BOOT_TRACE_REG is a SDRAM address then be sure to use the following
++ * 2 command after SDRAM init
++ */
++
++/* Backup state of previous boot to CONFIG_BOOT_TRACE_REG+4*/
++#define BACKUP_TRACE() \
++ ldr r4, =CONFIG_BOOT_TRACE_REG; \
++ ldr r3, [r4]; \
++ str r3, [r4, #0x04];
++
++/* Save a state of boot at CONFIG_BOOT_TRACE_REG */
++#define BOOT_TRACE(val) \
++ ldr r4, =CONFIG_BOOT_TRACE_REG; \
++ ldr r3, =val; \
++ str r3, [r4];
++#else
++#define BACKUP_TRACE()
++#define BOOT_TRACE(val)
++#endif
++
++nand_boot_setup:
++
++ /* Copy SPL image from flash to SDRAM first */
++ BOOT_TRACE(1)
++ ldr r0, =IMX_NFC_MAIN_AREA0
++ add r2, r0, #(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0) //2KB NFC Buff
++ ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
++
++ BOOT_TRACE(2)
++1: ldmia r0!, {r3-r10}
++ stmia r1!, {r3-r10}
++ cmp r0, r2
++ blo 1b
++
++
++
++ /* Jump to SDRAM */
++ BOOT_TRACE(3)
++ ldr r1, =0x7FF
++ and r0, pc, r1 /* offset of pc */
++ ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
++ add r1, r1, #0x10
++ add pc, r0, r1
++ nop
++ nop
++ nop
++ nop
++
++nand_copy_main:
++ BOOT_TRACE(4)
++ /* r0: nfc base. Reloaded after each page copying */
++ ldr r0, =IMX_NFC_MAIN_AREA0
++
++ /* r1: starting flash addr to be copied. Updated constantly */
++ /* bypass the first preloaded pages */
++ ldr r1, =(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0)
++
++ /* r2: end of 1st RAM buf. Doesn't change */
++ ldr r2, =IMX_NFC_MAIN_AREA1
++
++ /* r12: NFC register base. Doesn't change */
++ ldr r12, =IMX_NFC_REGS
++
++ ldr r11, =CONFIG_SYS_NAND_U_BOOT_DST
++
++ /* r13: end of SDRAM address for copying. Doesn't change */
++ add r13, r11, #CONFIG_SYS_NAND_U_BOOT_SIZE
++
++ /* r11: starting SDRAM address for copying. Updated constantly */
++ add r11, r11, r1
++
++ /* unlock internal buffer */
++ ldr r3, =NFC_CONFIG_UNLOCKED
++ strh r3, [r12, #NFC_OFFSET_CONFIG]
++
++ /* enable ECC and mask interrupts */
++ ldr r3, =(NFC_CONFIG1_ECC_EN | NFC_CONFIG1_INT_MSK)
++ strh r3, [r12, #NFC_OFFSET_CONFIG1]
++
++nfc_read_page:
++ BOOT_TRACE(5)
++ /* send NAND_CMD_READ0 command */
++ ldr r3, =NAND_CMD_READ0;
++ strh r3, [r12, #NFC_OFFSET_FLASH_CMD]
++
++ ldr r3, =NFC_CONFIG2_FCMD
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++
++ /* send NAND address to read. TODO small page support */
++ BOOT_TRACE(6)
++ mov r3, r1, lsr #1
++ bl do_addr_input /* 1st addr cycle */
++
++ mov r3, r1, lsr #9
++ and r3, r3, #0x03
++ bl do_addr_input /* 2nd addr cycle */
++
++ mov r3, r1, lsr #11
++ bl do_addr_input /* 3rd addr cycle */
++
++ mov r3, r1, lsr #19
++ bl do_addr_input /* 4th addr cycle */
++
++ /* Small NAND flashs (== 1Gb) support 5 addr cycles */
++ mov r3, r1, lsr #27
++ bl do_addr_input /* 5th addr cycle */
++
++ /* send NAND_CMD_READSTART command. TODO small page support */
++ BOOT_TRACE(7)
++ mov r3, #NAND_CMD_READSTART;
++ strh r3, [r12, #NFC_OFFSET_FLASH_CMD]
++ mov r3, #NFC_CONFIG2_FCMD
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++
++ /* read and copy buf 0 */
++ BOOT_TRACE(8)
++ mov r3, #0
++ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
++
++ mov r3, #NFC_CONFIG2_FDO_PAGE
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++
++ bl test_and_copy_buffer
++
++ /* read and copy buf 1 */
++ mov r3, #1
++ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
++
++ mov r3, #NFC_CONFIG2_FDO_PAGE
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++
++ bl test_and_copy_buffer
++
++ /* here we should test if 512B page flash and bypass next buffers */
++ /* read and copy buf 2. TODO small page support */
++ mov r3, #2
++ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
++
++ mov r3, #NFC_CONFIG2_FDO_PAGE
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++
++ bl test_and_copy_buffer
++
++ /* read and copy buf 3 */
++ mov r3, #3
++ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
++
++ mov r3, #NFC_CONFIG2_FDO_PAGE
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++
++ bl test_and_copy_buffer
++
++ /* is the last page ? */
++ BOOT_TRACE(12)
++ cmp r11, r13
++ bge nand_copy_main_done
++
++ /* r0: nfc base. Reloaded after each page copying */
++ ldr r0, =IMX_NFC_MAIN_AREA0
++ /* r2: end of 1st RAM buf. Doesn't change */
++ ldr r2, =IMX_NFC_MAIN_AREA1
++ b nfc_read_page
++
++nand_copy_main_done:
++ BOOT_TRACE(13)
++ .endm /* nand_boot */
++
++ .macro init_aipi
++ /*
++ * setup AIPI1 and AIPI2
++ */
++ write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL
++ write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL
++ write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL
++ write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL
++
++ /* Change SDRAM signal strengh */
++ ldr r0, =GPCR
++ ldr r1, =ACFG_GPCR_VAL
++ ldr r5, [r0]
++ orr r5, r5, r1
++ str r5, [r0]
++
++ .endm /* init_aipi */
++
++ .macro init_clock
++ ldr r0, =CSCR
++ /* disable MPLL/SPLL first */
++ ldr r1, [r0]
++ bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
++ str r1, [r0]
++
++ /*
++ * pll clock initialization predefined in apf27.h
++ */
++ write32 MPCTL0, ACFG_MPCTL0_VAL
++ write32 SPCTL0, ACFG_SPCTL0_VAL
++
++ write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART
++
++ /*
++ * add some delay here
++ */
++ mov r1, #0x1000
++ 1: subs r1, r1, #0x1
++ bne 1b
++
++ /* peripheral clock divider */
++ write32 PCDR0, ACFG_PCDR0_VAL
++ write32 PCDR1, ACFG_PCDR1_VAL
++
++ /* Configure PCCR0 and PCCR1 */
++ write32 PCCR0, ACFG_PCCR0_VAL
++ write32 PCCR1, ACFG_PCCR1_VAL
++
++ .endm /* init_clock */
++
++.globl board_init_f
++board_init_f:
++
++ /*
++ * invalidate I/D cache/TLB and drain write buffer
++ */
++ mov r0, #0
++ mcr p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
++ mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
++ mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
++
++ /*
++ * disable MMU stuff and caches
++ */
++ mrc p15, 0, r0, c1, c0, 0
++ bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
++ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
++ orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
++ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
++ mcr p15, 0, r0, c1, c0, 0
++
++init_aipi_start:
++ init_aipi
++
++ /* check if sdram has been setup (running within sdram) */
++ cmp pc, #0xa0000000 /* start of first sdram memory space */
++ blo init_clock_start
++ cmp pc, #0xc0000000 /* end of second sdram memory space */
++ blo regular_boot
++
++ /* running from sdram with full code present -> regular_boot */
++init_clock_start:
++ init_clock
++
++init_sdram_start:
++ bl setup_sdram_ddr
++
++ /* save state of previous boot (SDRAM is configured)*/
++ BACKUP_TRACE()
++
++ /* nand_boot BOOT_TRACE(1..13) */
++
++ nand_boot
++
++ BOOT_TRACE(14) /* start regular U-Boot */
++
++regular_boot: /* jump to start of next 2kiB block (U-Boot) */
++ ldr r0, =0xfffff800
++ and r0, r0, pc
++ add pc, r0, #0x800
++
++do_wait_op_done:
++ 1:
++ ldrh r3, [r12, #NFC_OFFSET_CONFIG2]
++ ands r3, r3, #NFC_CONFIG2_INT
++ beq 1b
++ mov r3, #0x0
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ mov pc, lr
++
++do_addr_input:
++ mov r9, lr
++ and r3, r3, #0xFF
++ strh r3, [r12, #NFC_OFFSET_FLASH_ADDR]
++ mov r3, #NFC_CONFIG2_FADD
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++ mov pc, r9
++
++test_and_copy_buffer:
++ /* check for bad block (2 bits error in main or spare are)*/
++ BOOT_TRACE(9)
++ ldrh r4, [r12, #NFC_OFFSET_ECC_STATUS_RESULT]
++ ands r4, r4, #(NFC_ECC_STAT_ERROR2| \
++ (NFC_ECC_STAT_ERROR2<<NFC_ECC_STAT_ERM_SHFT))
++ bne skip_bad_buffer
++
++ /* check BI byte of the current spare buffer */
++ ldr r4, =IMX_NFC_SPARE_AREA0
++ ldrh r3, [r12, #NFC_OFFSET_BUF_ADDR] /* for the current buffer */
++ orr r4, r3, lsl #0x04
++
++ /* at bi word offset 4. */
++ /* Fixme position change betwwen 8 and 16 bits bus */
++ ldrh r4, [r4, #0x04]
++ and r4, r4, #0x0FF00 /* has to be 0xFFxx */
++ cmp r4, #0x0FF00
++ bne skip_bad_buffer
++
++copy_good_buffer:
++ /* copying 512 bytes buffer */
++ BOOT_TRACE(10)
++1: ldmia r0!, {r3-r10}
++ stmia r11!, {r3-r10}
++ cmp r0, r2
++ blo 1b
++ b end_of_copy
++
++skip_bad_buffer:
++ BOOT_TRACE(11)
++ /* bad pages do not contain valid data and have to be skip */
++ add r0, r0, #0x200
++
++ /* rewind ram addr to start of buffer */
++ ldr r3, =(~0x1FF)
++ and r11, r11, r3
++
++end_of_copy:
++ add r2, r2, #0x200
++ add r1, r1, #0x200
++
++ mov pc, lr
++
++setup_sdram_ddr:
++
++ /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
++ ldr r0, =IMX_ESD_BASE
++ ldr r4, =ESDMISC_SDRAM_RDY
++2: ldr r1, [r0, #ESDMISC_ROF]
++ ands r1, r1, r4
++ bpl 2b
++
++ /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
++ ldr r0, =IMX_ESD_BASE
++ ldr r4, =ACFG_ESDMISC_VAL
++ orr r1, r4, #ESDMISC_MDDR_DL_RST
++ str r1, [r0, #ESDMISC_ROF]
++
++ /* Hold for more than 200ns */
++ ldr r1, =0x10000
++1: subs r1, r1, #0x1
++ bne 1b
++
++ str r4, [r0]
++
++ ldr r0, =IMX_ESD_BASE
++ ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
++ str r1, [r0, #ESDCFG0_ROF]
++
++ ldr r0, =IMX_ESD_BASE
++ ldr r1, =ACFG_PRECHARGE_CMD
++ str r1, [r0, #ESDCTL0_ROF]
++
++ /* write8(0xA0001000, any value) */
++ ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL
++ strb r2, [r1]
++
++ ldr r1, =ACFG_AUTOREFRESH_CMD
++ str r1, [r0, #ESDCTL0_ROF]
++
++ ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
++
++ ldr r6,=0x7 /* load loop counter */
++1: str r5,[r4] /* run auto-refresh cycle to array 0 */
++ subs r6,r6,#1
++ bne 1b
++
++ ldr r1, =ACFG_SET_MODE_REG_CMD
++ str r1, [r0, #ESDCTL0_ROF]
++
++ /* set standard mode register */
++ ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL
++ strb r2, [r4]
++
++ /* set extended mode register */
++ ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
++ strb r5, [r4]
++
++ ldr r1, =ACFG_NORMAL_RW_CMD
++ str r1, [r0, #ESDCTL0_ROF]
++
++ /* 2nd sdram */
++ ldr r0, =IMX_ESD_BASE
++ ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL
++ str r1, [r0, #ESDCFG1_ROF]
++
++ ldr r0, =IMX_ESD_BASE
++ ldr r1, =ACFG_PRECHARGE_CMD
++ str r1, [r0, #ESDCTL1_ROF]
++
++ /* write8(0xB0001000, any value) */
++ ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL
++ strb r2, [r1]
++
++ ldr r1, =ACFG_AUTOREFRESH_CMD
++ str r1, [r0, #ESDCTL1_ROF]
++
++ ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
++
++ ldr r6,=0x7 /* load loop counter */
++1: str r5,[r4] /* run auto-refresh cycle to array 0 */
++ subs r6,r6,#1
++ bne 1b
++
++ ldr r1, =ACFG_SET_MODE_REG_CMD
++ str r1, [r0, #ESDCTL1_ROF]
++
++ /* set standard mode register */
++ ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL
++ strb r2, [r4]
++
++ /* set extended mode register */
++ ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL
++ strb r2, [r4]
++
++ ldr r1, =ACFG_NORMAL_RW_CMD
++ str r1, [r0, #ESDCTL1_ROF]
++
++ mov pc, lr
diff --git a/boards.cfg b/boards.cfg
-index 4c63789..72c49df 100644
+index 0e082a0..58072c0 100644
--- a/boards.cfg
+++ b/boards.cfg
-@@ -190,6 +190,7 @@ jadecpu arm arm926ejs jadecpu syteco
+@@ -191,6 +191,7 @@ jadecpu arm arm926ejs jadecpu syteco
mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg
tx25 arm arm926ejs tx25 karo mx25
zmx25 arm arm926ejs zmx25 syteco mx25
+apf27 arm arm926ejs apf27 armadeus mx27
imx27lite arm arm926ejs imx27lite logicpd mx27
magnesium arm arm926ejs imx27lite logicpd mx27
- apx4devkit arm arm926ejs apx4devkit bluegiga mxs apx4devkit
+ mx23_olinuxino arm arm926ejs mx23_olinuxino olimex mxs mx23_olinuxino
diff --git a/include/configs/apf27.h b/include/configs/apf27.h
new file mode 100644
-index 0000000..5af347b
+index 0000000..e5e1dea
--- /dev/null
+++ b/include/configs/apf27.h
-@@ -0,0 +1,458 @@
+@@ -0,0 +1,448 @@
+/*
+ *
+ * Configuration settings for the Armadeus Project motherboard APF27
@@ -1033,7 +1488,7 @@ index 0000000..5af347b
+
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_ENV_VERSION "3.3"
-+#define CONFIG_IDENT_STRING " apf27 patch 3.8"
++#define CONFIG_IDENT_STRING " apf27 patch 3.9"
+#define CONFIG_BOARD_NAME apf27
+
+/*
@@ -1049,6 +1504,9 @@ index 0000000..5af347b
+#define CONFIG_SYS_NO_FLASH /* to be define before <config_cmd_default.h> */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_BOARD_EARLY_INIT_F
++#ifdef CONFIG_SPL_BUILD
++#define CONFIG_SKIP_LOWLEVEL_INIT
++#endif
+
+/*
+ * Board display option
@@ -1065,18 +1523,16 @@ index 0000000..5af347b
+#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN
+/* Build image with spl and u-boot */
+#define CONFIG_NAND_U_BOOT
-+#define CONFIG_SPL_PAD_TO 0xa1000000
++#define CONFIG_SPL_PAD_TO 0xa0000800
+
+/*
+ * SPL
+ */
+#define CONFIG_SPL
-+#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
-+#define CONFIG_SPL_START_S_PATH "board/armadeus/apf27"
-+#define CONFIG_SPL_LDSCRIPT "board/armadeus/apf27/u-boot-spl.lds"
-+#define CONFIG_SPL_LIBCOMMON_SUPPORT
-+#define CONFIG_SPL_LIBGENERIC_SUPPORT
-+
++#define CONFIG_SPL_TEXT_BASE 0xa0000000
++#define CONFIG_SPL_STACK 0xffffff00
++#define CONFIG_SYS_NAND_U_BOOT_START 0xa0000800
++#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800
+
+/*
+ * BOOTP options
@@ -1100,11 +1556,14 @@ index 0000000..5af347b
+#define CONFIG_CMD_ASKENV /* ask for env variable */
+#define CONFIG_CMD_BSP /* Board Specific functions */
+#define CONFIG_CMD_CACHE /* icache, dcache */
++#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP /* DHCP Support */
+#define CONFIG_CMD_DNS
++#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_IMX_FUSE /* imx iim fuse */
++#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII /* MII support */
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_MTDPARTS /* MTD partition support */
@@ -1120,7 +1579,7 @@ index 0000000..5af347b
+/*
+ * Memory configurations
+ */
-+#define CONFIG_NR_DRAM_POPULATED 1
++#define CONFIG_NR_DRAM_POPULATED 1
+#define CONFIG_NR_DRAM_BANKS 2
+
+#define ACFG_SDRAM_MBYTE_SYZE 64
@@ -1135,7 +1594,7 @@ index 0000000..5af347b
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \
+ + PHYS_SDRAM_1_SIZE - 0x0100000)
+
-+#define CONFIG_SYS_TEXT_BASE 0xA1000000
++#define CONFIG_SYS_TEXT_BASE 0xA0000800
+
+/*
+ * FLASH organization
@@ -1325,7 +1784,7 @@ index 0000000..5af347b
+
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
-+#define IMX27_NAND_16BITS
++#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
+#define NAND_MAX_CHIPS 1
+
+
@@ -1384,13 +1843,12 @@ index 0000000..5af347b
+ */
+
+#ifdef CONFIG_CMD_I2C
-+#define CONFIG_HARD_I2C 1
-+
++#define CONFIG_HARD_I2C
++#define CONFIG_I2C_MXC
++#define CONFIG_I2C_MULTI_BUS
++#define CONFIG_SYS_I2C_BASE IMX_I2C1_BASE
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
-+
-+#define CONFIG_I2C_CMD_TREE
-+#define CONFIG_I2C_MULTI_BUS 2
+#define CONFIG_SYS_I2C_NOPROBES { }
+
+#ifdef CONFIG_CMD_EEPROM
@@ -1402,10 +1860,6 @@ index 0000000..5af347b
+#endif /* CONFIG_CMD_I2C */
+
+/*
-+ * SPI
-+ */
-+
-+/*
+ * SD/MMC
+ */
+#ifdef CONFIG_CMD_MMC
@@ -1424,14 +1878,6 @@ index 0000000..5af347b
+#endif /* CONFIG_CMD_DATE */
+
+/*
-+ * Watchdog Config
-+ */
-+
-+/*
-+ * USB
-+ */
-+
-+/*
+ * Clocks
+ */
+#define CONFIG_SYS_HZ 1000 /* Ticks per second */
@@ -1443,7 +1889,6 @@ index 0000000..5af347b
+ * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
+ */
+#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */
-+#undef CONFIG_MX27_CLK26 /* No external 26MHz external clock */
+
+#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
+/* micron 64MB */
diff --git a/patches/u-boot/2012.10/304-apf27-Add-FPGA-support-for-the-apf27-board.patch b/patches/u-boot/2013.04/304-apf27-Add-FPGA-support-for-the-apf27-board.patch
similarity index 83%
copy from patches/u-boot/2012.10/304-apf27-Add-FPGA-support-for-the-apf27-board.patch
copy to patches/u-boot/2013.04/304-apf27-Add-FPGA-support-for-the-apf27-board.patch
index a3c013e..9bc8a89 100644
--- a/patches/u-boot/2012.10/304-apf27-Add-FPGA-support-for-the-apf27-board.patch
+++ b/patches/u-boot/2013.04/304-apf27-Add-FPGA-support-for-the-apf27-board.patch
@@ -3,36 +3,41 @@ Add FPGA support for the apf27 board
Signed-off-by: Philippe Reynes <tr...@ya...>
Signed-off-by: Eric Jarrige <eri...@ar...>
---
+ board/armadeus/apf27/Makefile | 3 +
+ board/armadeus/apf27/apf27.c | 18 +++
+ board/armadeus/apf27/fpga.c | 249 +++++++++++++++++++++++++++++++++++++++++
+ board/armadeus/apf27/fpga.h | 39 +++++++
+ 4 files changed, 309 insertions(+), 0 deletions(-)
create mode 100644 board/armadeus/apf27/fpga.c
create mode 100644 board/armadeus/apf27/fpga.h
diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile
-index f57f405..9d356a3 100644
+index 08d5d8d..11562a2 100644
--- a/board/armadeus/apf27/Makefile
+++ b/board/armadeus/apf27/Makefile
@@ -29,6 +29,9 @@ LIB = $(obj)lib$(BOARD).o
- ifndef CONFIG_SPL_BUILD
+ ifndef CONFIG_SPL_BUILD
COBJS := apf27.o
+ifdef CONFIG_FPGA
+COBJS += fpga.o
+endif
endif
- SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+ ifdef CONFIG_SPL_BUILD
diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
-index bf3e5ec..fa5dfd8 100644
+index fce3325..951a5e3 100644
--- a/board/armadeus/apf27/apf27.c
+++ b/board/armadeus/apf27/apf27.c
-@@ -21,6 +21,7 @@
-
- #include <common.h>
+@@ -30,6 +30,7 @@
+ #include <asm/errno.h>
+ #include "apf27.h"
#include "crc.h"
+#include "fpga.h"
- #include <jffs2/jffs2.h>
- #include <nand.h>
- #include <netdev.h>
-@@ -386,6 +387,21 @@ misc_init_r(void)
+
+ DECLARE_GLOBAL_DATA_PTR;
+
+@@ -321,6 +322,23 @@ int misc_init_r(void)
struct mtd_device *dev;
struct part_info *part;
@@ -44,7 +49,9 @@ index bf3e5ec..fa5dfd8 100644
+ &dev, &pnum, &part) == 0) {
+ size = part->size;
+ if (nand_read_skip_bad(&nand_info[0],
-+ part->offset, &size, firmware_buffer))
++ part->offset, &size,
++ NULL, part->size,
++ firmware_buffer))
+ size = 0;
+ }
+ }
@@ -56,10 +63,10 @@ index bf3e5ec..fa5dfd8 100644
if ((NULL == s) || (0 != strcmp(s, CONFIG_ENV_VERSION))) {
diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c
new file mode 100644
-index 0000000..d5c27a7
+index 0000000..47f4ffc
--- /dev/null
+++ b/board/armadeus/apf27/fpga.c
-@@ -0,0 +1,262 @@
+@@ -0,0 +1,250 @@
+/*
+ * (C) Copyright 2002-2012
+ * Eric Jarrige <eri...@ar...>
@@ -122,15 +129,14 @@ index 0000000..d5c27a7
+ {Xilinx_Spartan3,
+ slave_parallel,
+ 1196128l/8,
-+ (void *) &fpga_fns,
++ (void *)&fpga_fns,
+ 0}
+};
+
+/*
+ * Initialize GPIO port B before download
+ */
-+int
-+fpga_pre_fn(int cookie)
++int fpga_pre_fn(int cookie)
+{
+ /* Initialize GPIO pins */
+ gpio_set_value(ACFG_FPGA_PWR, 1);
@@ -150,6 +156,7 @@ index 0000000..d5c27a7
+ gpio_set_value(ACFG_FPGA_CS, 1);
+ gpio_set_value(ACFG_FPGA_SUSPEND, 0);
+ gpio_set_value(ACFG_FPGA_PWR, 0);
++ udelay(30000); /*wait until supply started*/
+
+ return cookie;
+}
@@ -157,11 +164,10 @@ index 0000000..d5c27a7
+/*
+ * Set the FPGA's active-low program line to the specified level
+ */
-+int
-+fpga_pgm_fn(int assert, int flush, int cookie)
++int fpga_pgm_fn(int assert, int flush, int cookie)
+{
+ debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
-+ assert ? "high" : "low");
++ assert ? "high" : "low");
+ gpio_set_value(ACFG_FPGA_PRG, !assert);
+ return assert;
+}
@@ -169,11 +175,10 @@ index 0000000..d5c27a7
+/*
+ * Set the FPGA's active-high clock line to the specified level
+ */
-+int
-+fpga_clk_fn(int assert_clk, int flush, int cookie)
++int fpga_clk_fn(int assert_clk, int flush, int cookie)
+{
+ debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
-+ assert_clk ? "high" : "low");
++ assert_clk ? "high" : "low");
+ gpio_set_value(ACFG_FPGA_CLK, !assert_clk);
+ return assert_clk;
+}
@@ -182,8 +187,7 @@ index 0000000..d5c27a7
+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
+ * asserted (low).
+ */
-+int
-+fpga_init_fn(int cookie)
++int fpga_init_fn(int cookie)
+{
+ int value;
+ debug("%s:%d: INIT check... ", __func__, __LINE__);
@@ -199,69 +203,61 @@ index 0000000..d5c27a7
+/*
+ * Test the state of the active-high FPGA DONE pin
+ */
-+int
-+fpga_done_fn(int cookie)
++int fpga_done_fn(int cookie)
+{
+ debug("%s:%d: DONE check... %s", __func__, __LINE__,
-+ gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low");
++ gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low");
+ return gpio_get_value(ACFG_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL;
+}
+
+/*
+ * Set the FPGA's wr line to the specified level
+ */
-+int
-+fpga_wr_fn(int assert_write, int flush, int cookie)
++int fpga_wr_fn(int assert_write, int flush, int cookie)
+{
+ debug("%s:%d: FPGA RW... %s ", __func__, __LINE__,
-+ assert_write ? "high" : "low");
++ assert_write ? "high" : "low");
+ gpio_set_value(ACFG_FPGA_RW, !assert_write);
+ return assert_write;
+}
+
-+int
-+fpga_cs_fn(int assert_cs, int flush, int cookie)
++int fpga_cs_fn(int assert_cs, int flush, int cookie)
+{
+ debug("%s:%d: FPGA CS %s ", __func__, __LINE__,
-+ assert_cs ? "high" : "low");
++ assert_cs ? "high" : "low");
+ gpio_set_value(ACFG_FPGA_CS, !assert_cs);
+ return assert_cs;
+}
+
-+int
-+fpga_rdata_fn(unsigned char *data, int cookie)
++int fpga_rdata_fn(unsigned char *data, int cookie)
+{
+ debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__,
-+ *((char *)ACFG_FPGA_RDATA));
-+ *data = (unsigned char) \
++ *((char *)ACFG_FPGA_RDATA));
++ *data = (unsigned char)
+ ((*((unsigned short *)ACFG_FPGA_RDATA))&0x00FF);
+ return *data;
+}
+
-+int
-+fpga_wdata_fn(unsigned char data, int cookie)
++int fpga_wdata_fn(unsigned char data, int flush, int cookie)
+{
+ debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__,
-+ data);
++ data);
+ *((unsigned short *)ACFG_FPGA_WDATA) = data;
+ return data;
+}
+
-+int
-+fpga_abort_fn(int cookie)
++int fpga_abort_fn(int cookie)
+{
+ return cookie;
+}
+
+
-+int
-+fpga_busy_fn(int cookie)
++int fpga_busy_fn(int cookie)
+{
+ return 1;
+}
+
-+int
-+fpga_post_fn(int cookie)
++int fpga_post_fn(int cookie)
+{
+ debug("%s:%d: FPGA POST ", __func__, __LINE__);
+
@@ -277,7 +273,7 @@ index 0000000..d5c27a7
+void apf27_fpga_setup(void)
+{
+ struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
-+ struct system_control_regs *system = \
++ struct system_control_regs *system =
+ (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
+
+ /* Configure FPGA CLKO */
@@ -293,8 +289,7 @@ index 0000000..d5c27a7
+/*
+ * Initialize the fpga. Return 1 on success, 0 on failure.
+ */
-+int
-+APF27_init_fpga(u_char *buffer, size_t size)
++int APF27_init_fpga(u_char *buffer, size_t size)
+{
+ char *autoload = getenv("firmware_autoload");
+
@@ -310,7 +305,7 @@ index 0000000..d5c27a7
+ }
+
+ if ((size >= fpga[0].size) && (autoload) &&
-+ (0 == strcmp(autoload, "1"))) {
++ (0 == strcmp(autoload, "1"))) {
+ if (ctrlc()) {
+ printf("Firmware download stopped!\n");
+ } else if (FPGA_SUCCESS != fpga_load(0, (void *)buffer, size)) {
@@ -324,7 +319,7 @@ index 0000000..d5c27a7
+}
diff --git a/board/armadeus/apf27/fpga.h b/board/armadeus/apf27/fpga.h
new file mode 100644
-index 0000000..b11b24c
+index 0000000..e30dd11
--- /dev/null
+++ b/board/armadeus/apf27/fpga.h
@@ -0,0 +1,39 @@
@@ -363,7 +358,7 @@ index 0000000..b11b24c
+extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
+extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+extern int fpga_rdata_fn(unsigned char *data, int cookie);
-+extern int fpga_wdata_fn(unsigned char data, int cookie);
++extern int fpga_wdata_fn(unsigned char data, int flush, int cookie);
+extern int fpga_abort_fn(int cookie);
+extern int fpga_post_fn(int cookie);
+extern int fpga_busy_fn(int cookie);
diff --git a/patches/u-boot/2012.10/311-imx-nand-lock-unlock.patch b/patches/u-boot/2013.04/311-imx-nand-lock-unlock.patch
similarity index 100%
copy from patches/u-boot/2012.10/311-imx-nand-lock-unlock.patch
copy to patches/u-boot/2013.04/311-imx-nand-lock-unlock.patch
diff --git a/patches/u-boot/2012.10/320-spartan.patch b/patches/u-boot/2013.04/320-spartan.patch
similarity index 100%
copy from patches/u-boot/2012.10/320-spartan.patch
copy to patches/u-boot/2013.04/320-spartan.patch
diff --git a/patches/u-boot/2013.01.01/321-add_spartan6.patch b/patches/u-boot/2013.04/321-add_spartan6.patch
similarity index 100%
copy from patches/u-boot/2013.01.01/321-add_spartan6.patch
copy to patches/u-boot/2013.04/321-add_spartan6.patch
diff --git a/patches/u-boot/2013.01.01/340-apf27-misc-commands.patch b/patches/u-boot/2013.04/340-apf27-misc-commands.patch
similarity index 99%
copy from patches/u-boot/2013.01.01/340-apf27-misc-commands.patch
copy to patches/u-boot/2013.04/340-apf27-misc-commands.patch
index e0f81c2..addecd5 100644
--- a/patches/u-boot/2013.01.01/340-apf27-misc-commands.patch
+++ b/patches/u-boot/2013.04/340-apf27-misc-commands.patch
@@ -31,7 +31,7 @@ index 7a39426..484268e 100644
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
- ifndef CONFIG_SPL_BUILD
+ ifndef CONFIG_SPL_BUILD
-COBJS := apf27.o
+COBJS := apf27.o cmd_imxfuse.o
ifdef CONFIG_FPGA
diff --git a/patches/u-boot/2013.01.01/350-nand_large_file_download.patch b/p...
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