[Armadeus-commitlog] armadeus branch, master, updated. armadeus-5.2-80-gafb27cd

[Fabien M <fa...@us...>]

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- Log -----------------------------------------------------------------
commit afb27cd715c32f5749f99a524c7acc00f8283a9c
Merge: 165ad06 8a2d2a3
Author: Fabien Marteau <fab...@ar...>
Date:   Fri Jan 4 09:58:51 2013 +0100

    Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus

commit 165ad06ba619850be5a923241ec47d4b3f35af71
Author: Fabien Marteau <fab...@ar...>
Date:   Fri Jan 4 09:58:10 2013 +0100

    [U-BOOT][2012.04][APF51] increase DDR RAM timings

-----------------------------------------------------------------------

Summary of changes:
 .../device/armadeus/apf51/apf51-u-boot-2012.04.h   |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2012.04.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2012.04.h
index 0c251a7..50320e1 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2012.04.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2012.04.h
@@ -25,7 +25,7 @@
 
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_ENV_VERSION	"1.2"
-#define CONFIG_IDENT_STRING	" apf51 patch 1.7"
+#define CONFIG_IDENT_STRING	" apf51 patch 1.8"
 #define CONFIG_BOARD_NAME	apf51
 
 /*
@@ -522,17 +522,17 @@
 #define ACFG_SDRAM_NUM_COL		10	/* 8..11 column address bits */
 #define ACFG_SDRAM_NUM_ROW		14	/* 11..13 row address bits */
 #define ACFG_SDRAM_REFRESH		3	/* 0=OFF 1=2048 2=4096 3=8192.*/
-#define ACFG_SDRAM_XSR_DELAY		125	/* ns Exit self refresh */
+#define ACFG_SDRAM_XSR_DELAY		138	/* ns Exit self refresh */
 #define ACFG_SDRAM_EXIT_PWD		10	/* ns exit power down delay */
 #define ACFG_SDRAM_W2R_DELAY		1	/* 0=1ck 1=2ck */
-#define ACFG_SDRAM_ROW_PRECHARGE_DELAY	15	/* ns (>2 x ddr_clk) */
+#define ACFG_SDRAM_ROW_PRECHARGE_DELAY	25	/* ns (>2 x ddr_clk) */
 #define ACFG_SDRAM_TMRD_DELAY		2	/* 1..4 */
 #define ACFG_SDRAM_TWR_DELAY		1	/* DDR: 0=2ck 1=3ck */
 #define ACFG_SDRAM_RAS_DELAY		40	/* ns ACTIVE-to-PRECHARGE */
 #define ACFG_SDRAM_RRD_DELAY		10	/* ns ACTIVE-to-ACTIVE delay */
-#define ACFG_SDRAM_RCD_DELAY		15	/* ns Row to Column delay */
-#define ACFG_SDRAM_RC_DELAY		55	/* ns Row cycle delay */
-#define ACFG_SDRAM_RFC_DELAY		72	/* ns (> 10xddr_clk) */
+#define ACFG_SDRAM_RCD_DELAY		25 	/* ns Row to Column delay */
+#define ACFG_SDRAM_RC_DELAY		68	/* ns Row cycle delay */
+#define ACFG_SDRAM_RFC_DELAY		110	/* ns (> 10xddr_clk) */
 #define ACFG_SDRAM_PARTIAL_ARRAY_SR	0	/* 0..4 */
 #define ACFG_SDRAM_DRIVE_STRENGH	0	/* 0..3 */
 #define ACFG_SDRAM_BURST_LENGTH		3	/* 2^N BYTES (N=0..3) */


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